| commit | 19449bfc10d163f0024dd5ae5808e28cda32e7b4 | |
| author | avisconti <armando.visconti@st.com> | |
| Mon, 25 Oct 2010 18:58:14 +0000 (25 18:58 +0000) | ||
| committer | David S. Miller <davem@davemloft.net> | |
| Thu, 28 Oct 2010 18:47:54 +0000 (28 11:47 -0700) | ||
| tree | b32bcc4f66ac12f1a6c94d73a0ada36412cfa8a7 | treesnapshot (tar.gz zip) |
| parent | d1abc9a9aca06ceb795eb5405264eaafe016ec5c | commitdiff |
stmmac: enable/disable rx/tx in the core with a single write.
This patch enables and disables the rx and tx bits in the MAC control reg
by using a single write operation.
This also solves a possible problem (spotted on SPEAr platforms) at 10Mbps
where two consecutive writes to a MAC control register can take more than
4 phy_clk cycles.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch enables and disables the rx and tx bits in the MAC control reg
by using a single write operation.
This also solves a possible problem (spotted on SPEAr platforms) at 10Mbps
where two consecutive writes to a MAC control register can take more than
4 phy_clk cycles.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| drivers/net/stmmac/stmmac_main.c | diffblobblamehistory |