ibm_newemac: PowerPC 440GX EMAC PHY clock workaround
commit0925ab5d385b6cd1c435c82bfc01898c81f3d062
authorValentine Barshak <vbarshak@ru.mvista.com>
Tue, 22 Apr 2008 00:46:46 +0000 (22 10:46 +1000)
committerJeff Garzik <jgarzik@redhat.com>
Fri, 25 Apr 2008 06:08:07 +0000 (25 02:08 -0400)
tree55a8cf446bc641a8c1c47a43426043b314d7e5fe
parentbe63c09afe9153be6ba4373d1b69848cf2b32268
ibm_newemac: PowerPC 440GX EMAC PHY clock workaround

The PowerPC 440GX Taishan board fails to reset EMAC3 (reset timeout
error) if there's no link. Because of that it fails to find PHY
chip. The older ibm_emac driver had a workaround for that: the
EMAC_CLK_INTERNAL/EMAC_CLK_EXTERNAL macros, which toggle the Ethernet
Clock Select bit in the SDR0_MFR register. This patch does the same for
"ibm,emac-440gx" compatible chips. The workaround forces clock on -all-
EMACs, so we select clock under global emac_phy_map_lock.

BenH: Made that #ifdef CONFIG_PPC_DCR_NATIVE for now as dcri_* stuff
doesn't exist for MMIO type DCRs like Cell. Some future rework &
improvements of the DCR infrastructure will make that cleaner but
for now, this makes it work.

Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
drivers/net/ibm_newemac/core.c
drivers/net/ibm_newemac/core.h