2 * Driver for Ensoniq ES1370/ES1371 AudioPCI soundcard
3 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
4 * Thomas Sailer <sailer@ife.ee.ethz.ch>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* Power-Management-Code ( CONFIG_PM )
23 * for ens1371 only ( FIXME )
24 * derived from cs4281.c, atiixp.c and via82xx.c
25 * using http://www.alsa-project.org/~iwai/writing-an-alsa-driver/c1540.htm
29 #include <sound/driver.h>
31 #include <linux/delay.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/slab.h>
36 #include <linux/gameport.h>
37 #include <linux/moduleparam.h>
38 #include <sound/core.h>
39 #include <sound/control.h>
40 #include <sound/pcm.h>
41 #include <sound/rawmidi.h>
43 #include <sound/ac97_codec.h>
45 #include <sound/ak4531_codec.h>
47 #include <sound/initval.h>
48 #include <sound/asoundef.h>
56 #define DRIVER_NAME "ENS1370"
58 #define DRIVER_NAME "ENS1371"
62 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Thomas Sailer <sailer@ife.ee.ethz.ch>");
63 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Ensoniq AudioPCI ES1370");
66 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI-97 ES1370},"
67 "{Creative Labs,SB PCI64/128 (ES1370)}}");
70 MODULE_DESCRIPTION("Ensoniq/Creative AudioPCI ES1371+");
71 MODULE_SUPPORTED_DEVICE("{{Ensoniq,AudioPCI ES1371/73},"
72 "{Ensoniq,AudioPCI ES1373},"
73 "{Creative Labs,Ectiva EV1938},"
74 "{Creative Labs,SB PCI64/128 (ES1371/73)},"
75 "{Creative Labs,Vibra PCI128},"
79 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
80 #define SUPPORT_JOYSTICK
83 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
84 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
85 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable switches */
86 #ifdef SUPPORT_JOYSTICK
88 static int joystick_port
[SNDRV_CARDS
];
90 static int joystick
[SNDRV_CARDS
];
94 module_param_array(index
, int, NULL
, 0444);
95 MODULE_PARM_DESC(index
, "Index value for Ensoniq AudioPCI soundcard.");
96 module_param_array(id
, charp
, NULL
, 0444);
97 MODULE_PARM_DESC(id
, "ID string for Ensoniq AudioPCI soundcard.");
98 module_param_array(enable
, bool, NULL
, 0444);
99 MODULE_PARM_DESC(enable
, "Enable Ensoniq AudioPCI soundcard.");
100 #ifdef SUPPORT_JOYSTICK
102 module_param_array(joystick_port
, int, NULL
, 0444);
103 MODULE_PARM_DESC(joystick_port
, "Joystick port address.");
105 module_param_array(joystick
, bool, NULL
, 0444);
106 MODULE_PARM_DESC(joystick
, "Enable joystick.");
108 #endif /* SUPPORT_JOYSTICK */
111 /* This is a little confusing because all ES1371 compatible chips have the
112 same DEVICE_ID, the only thing differentiating them is the REV_ID field.
113 This is only significant if you want to enable features on the later parts.
114 Yes, I know it's stupid and why didn't we use the sub IDs?
116 #define ES1371REV_ES1373_A 0x04
117 #define ES1371REV_ES1373_B 0x06
118 #define ES1371REV_CT5880_A 0x07
119 #define CT5880REV_CT5880_C 0x02
120 #define CT5880REV_CT5880_D 0x03 /* ??? -jk */
121 #define CT5880REV_CT5880_E 0x04 /* mw */
122 #define ES1371REV_ES1371_B 0x09
123 #define EV1938REV_EV1938_A 0x00
124 #define ES1371REV_ES1373_8 0x08
130 #define ES_REG(ensoniq, x) ((ensoniq)->port + ES_REG_##x)
132 #define ES_REG_CONTROL 0x00 /* R/W: Interrupt/Chip select control register */
133 #define ES_1370_ADC_STOP (1<<31) /* disable capture buffer transfers */
134 #define ES_1370_XCTL1 (1<<30) /* general purpose output bit */
135 #define ES_1373_BYPASS_P1 (1<<31) /* bypass SRC for PB1 */
136 #define ES_1373_BYPASS_P2 (1<<30) /* bypass SRC for PB2 */
137 #define ES_1373_BYPASS_R (1<<29) /* bypass SRC for REC */
138 #define ES_1373_TEST_BIT (1<<28) /* should be set to 0 for normal operation */
139 #define ES_1373_RECEN_B (1<<27) /* mix record with playback for I2S/SPDIF out */
140 #define ES_1373_SPDIF_THRU (1<<26) /* 0 = SPDIF thru mode, 1 = SPDIF == dig out */
141 #define ES_1371_JOY_ASEL(o) (((o)&0x03)<<24)/* joystick port mapping */
142 #define ES_1371_JOY_ASELM (0x03<<24) /* mask for above */
143 #define ES_1371_JOY_ASELI(i) (((i)>>24)&0x03)
144 #define ES_1371_GPIO_IN(i) (((i)>>20)&0x0f)/* GPIO in [3:0] pins - R/O */
145 #define ES_1370_PCLKDIVO(o) (((o)&0x1fff)<<16)/* clock divide ratio for DAC2 */
146 #define ES_1370_PCLKDIVM ((0x1fff)<<16) /* mask for above */
147 #define ES_1370_PCLKDIVI(i) (((i)>>16)&0x1fff)/* clock divide ratio for DAC2 */
148 #define ES_1371_GPIO_OUT(o) (((o)&0x0f)<<16)/* GPIO out [3:0] pins - W/R */
149 #define ES_1371_GPIO_OUTM (0x0f<<16) /* mask for above */
150 #define ES_MSFMTSEL (1<<15) /* MPEG serial data format; 0 = SONY, 1 = I2S */
151 #define ES_1370_M_SBB (1<<14) /* clock source for DAC - 0 = clock generator; 1 = MPEG clocks */
152 #define ES_1371_SYNC_RES (1<<14) /* Warm AC97 reset */
153 #define ES_1370_WTSRSEL(o) (((o)&0x03)<<12)/* fixed frequency clock for DAC1 */
154 #define ES_1370_WTSRSELM (0x03<<12) /* mask for above */
155 #define ES_1371_ADC_STOP (1<<13) /* disable CCB transfer capture information */
156 #define ES_1371_PWR_INTRM (1<<12) /* power level change interrupts enable */
157 #define ES_1370_DAC_SYNC (1<<11) /* DAC's are synchronous */
158 #define ES_1371_M_CB (1<<11) /* capture clock source; 0 = AC'97 ADC; 1 = I2S */
159 #define ES_CCB_INTRM (1<<10) /* CCB voice interrupts enable */
160 #define ES_1370_M_CB (1<<9) /* capture clock source; 0 = ADC; 1 = MPEG */
161 #define ES_1370_XCTL0 (1<<8) /* generap purpose output bit */
162 #define ES_1371_PDLEV(o) (((o)&0x03)<<8) /* current power down level */
163 #define ES_1371_PDLEVM (0x03<<8) /* mask for above */
164 #define ES_BREQ (1<<7) /* memory bus request enable */
165 #define ES_DAC1_EN (1<<6) /* DAC1 playback channel enable */
166 #define ES_DAC2_EN (1<<5) /* DAC2 playback channel enable */
167 #define ES_ADC_EN (1<<4) /* ADC capture channel enable */
168 #define ES_UART_EN (1<<3) /* UART enable */
169 #define ES_JYSTK_EN (1<<2) /* Joystick module enable */
170 #define ES_1370_CDC_EN (1<<1) /* Codec interface enable */
171 #define ES_1371_XTALCKDIS (1<<1) /* Xtal clock disable */
172 #define ES_1370_SERR_DISABLE (1<<0) /* PCI serr signal disable */
173 #define ES_1371_PCICLKDIS (1<<0) /* PCI clock disable */
174 #define ES_REG_STATUS 0x04 /* R/O: Interrupt/Chip select status register */
175 #define ES_INTR (1<<31) /* Interrupt is pending */
176 #define ES_1371_ST_AC97_RST (1<<29) /* CT5880 AC'97 Reset bit */
177 #define ES_1373_REAR_BIT27 (1<<27) /* rear bits: 000 - front, 010 - mirror, 101 - separate */
178 #define ES_1373_REAR_BIT26 (1<<26)
179 #define ES_1373_REAR_BIT24 (1<<24)
180 #define ES_1373_GPIO_INT_EN(o)(((o)&0x0f)<<20)/* GPIO [3:0] pins - interrupt enable */
181 #define ES_1373_SPDIF_EN (1<<18) /* SPDIF enable */
182 #define ES_1373_SPDIF_TEST (1<<17) /* SPDIF test */
183 #define ES_1371_TEST (1<<16) /* test ASIC */
184 #define ES_1373_GPIO_INT(i) (((i)&0x0f)>>12)/* GPIO [3:0] pins - interrupt pending */
185 #define ES_1370_CSTAT (1<<10) /* CODEC is busy or register write in progress */
186 #define ES_1370_CBUSY (1<<9) /* CODEC is busy */
187 #define ES_1370_CWRIP (1<<8) /* CODEC register write in progress */
188 #define ES_1371_SYNC_ERR (1<<8) /* CODEC synchronization error occurred */
189 #define ES_1371_VC(i) (((i)>>6)&0x03) /* voice code from CCB module */
190 #define ES_1370_VC(i) (((i)>>5)&0x03) /* voice code from CCB module */
191 #define ES_1371_MPWR (1<<5) /* power level interrupt pending */
192 #define ES_MCCB (1<<4) /* CCB interrupt pending */
193 #define ES_UART (1<<3) /* UART interrupt pending */
194 #define ES_DAC1 (1<<2) /* DAC1 channel interrupt pending */
195 #define ES_DAC2 (1<<1) /* DAC2 channel interrupt pending */
196 #define ES_ADC (1<<0) /* ADC channel interrupt pending */
197 #define ES_REG_UART_DATA 0x08 /* R/W: UART data register */
198 #define ES_REG_UART_STATUS 0x09 /* R/O: UART status register */
199 #define ES_RXINT (1<<7) /* RX interrupt occurred */
200 #define ES_TXINT (1<<2) /* TX interrupt occurred */
201 #define ES_TXRDY (1<<1) /* transmitter ready */
202 #define ES_RXRDY (1<<0) /* receiver ready */
203 #define ES_REG_UART_CONTROL 0x09 /* W/O: UART control register */
204 #define ES_RXINTEN (1<<7) /* RX interrupt enable */
205 #define ES_TXINTENO(o) (((o)&0x03)<<5) /* TX interrupt enable */
206 #define ES_TXINTENM (0x03<<5) /* mask for above */
207 #define ES_TXINTENI(i) (((i)>>5)&0x03)
208 #define ES_CNTRL(o) (((o)&0x03)<<0) /* control */
209 #define ES_CNTRLM (0x03<<0) /* mask for above */
210 #define ES_REG_UART_RES 0x0a /* R/W: UART reserver register */
211 #define ES_TEST_MODE (1<<0) /* test mode enabled */
212 #define ES_REG_MEM_PAGE 0x0c /* R/W: Memory page register */
213 #define ES_MEM_PAGEO(o) (((o)&0x0f)<<0) /* memory page select - out */
214 #define ES_MEM_PAGEM (0x0f<<0) /* mask for above */
215 #define ES_MEM_PAGEI(i) (((i)>>0)&0x0f) /* memory page select - in */
216 #define ES_REG_1370_CODEC 0x10 /* W/O: Codec write register address */
217 #define ES_1370_CODEC_WRITE(a,d) ((((a)&0xff)<<8)|(((d)&0xff)<<0))
218 #define ES_REG_1371_CODEC 0x14 /* W/R: Codec Read/Write register address */
219 #define ES_1371_CODEC_RDY (1<<31) /* codec ready */
220 #define ES_1371_CODEC_WIP (1<<30) /* codec register access in progress */
221 #define ES_1371_CODEC_PIRD (1<<23) /* codec read/write select register */
222 #define ES_1371_CODEC_WRITE(a,d) ((((a)&0x7f)<<16)|(((d)&0xffff)<<0))
223 #define ES_1371_CODEC_READS(a) ((((a)&0x7f)<<16)|ES_1371_CODEC_PIRD)
224 #define ES_1371_CODEC_READ(i) (((i)>>0)&0xffff)
226 #define ES_REG_1371_SMPRATE 0x10 /* W/R: Codec rate converter interface register */
227 #define ES_1371_SRC_RAM_ADDRO(o) (((o)&0x7f)<<25)/* address of the sample rate converter */
228 #define ES_1371_SRC_RAM_ADDRM (0x7f<<25) /* mask for above */
229 #define ES_1371_SRC_RAM_ADDRI(i) (((i)>>25)&0x7f)/* address of the sample rate converter */
230 #define ES_1371_SRC_RAM_WE (1<<24) /* R/W: read/write control for sample rate converter */
231 #define ES_1371_SRC_RAM_BUSY (1<<23) /* R/O: sample rate memory is busy */
232 #define ES_1371_SRC_DISABLE (1<<22) /* sample rate converter disable */
233 #define ES_1371_DIS_P1 (1<<21) /* playback channel 1 accumulator update disable */
234 #define ES_1371_DIS_P2 (1<<20) /* playback channel 1 accumulator update disable */
235 #define ES_1371_DIS_R1 (1<<19) /* capture channel accumulator update disable */
236 #define ES_1371_SRC_RAM_DATAO(o) (((o)&0xffff)<<0)/* current value of the sample rate converter */
237 #define ES_1371_SRC_RAM_DATAM (0xffff<<0) /* mask for above */
238 #define ES_1371_SRC_RAM_DATAI(i) (((i)>>0)&0xffff)/* current value of the sample rate converter */
240 #define ES_REG_1371_LEGACY 0x18 /* W/R: Legacy control/status register */
241 #define ES_1371_JFAST (1<<31) /* fast joystick timing */
242 #define ES_1371_HIB (1<<30) /* host interrupt blocking enable */
243 #define ES_1371_VSB (1<<29) /* SB; 0 = addr 0x220xH, 1 = 0x22FxH */
244 #define ES_1371_VMPUO(o) (((o)&0x03)<<27)/* base register address; 0 = 0x320xH; 1 = 0x330xH; 2 = 0x340xH; 3 = 0x350xH */
245 #define ES_1371_VMPUM (0x03<<27) /* mask for above */
246 #define ES_1371_VMPUI(i) (((i)>>27)&0x03)/* base register address */
247 #define ES_1371_VCDCO(o) (((o)&0x03)<<25)/* CODEC; 0 = 0x530xH; 1 = undefined; 2 = 0xe80xH; 3 = 0xF40xH */
248 #define ES_1371_VCDCM (0x03<<25) /* mask for above */
249 #define ES_1371_VCDCI(i) (((i)>>25)&0x03)/* CODEC address */
250 #define ES_1371_FIRQ (1<<24) /* force an interrupt */
251 #define ES_1371_SDMACAP (1<<23) /* enable event capture for slave DMA controller */
252 #define ES_1371_SPICAP (1<<22) /* enable event capture for slave IRQ controller */
253 #define ES_1371_MDMACAP (1<<21) /* enable event capture for master DMA controller */
254 #define ES_1371_MPICAP (1<<20) /* enable event capture for master IRQ controller */
255 #define ES_1371_ADCAP (1<<19) /* enable event capture for ADLIB register; 0x388xH */
256 #define ES_1371_SVCAP (1<<18) /* enable event capture for SB registers */
257 #define ES_1371_CDCCAP (1<<17) /* enable event capture for CODEC registers */
258 #define ES_1371_BACAP (1<<16) /* enable event capture for SoundScape base address */
259 #define ES_1371_EXI(i) (((i)>>8)&0x07) /* event number */
260 #define ES_1371_AI(i) (((i)>>3)&0x1f) /* event significant I/O address */
261 #define ES_1371_WR (1<<2) /* event capture; 0 = read; 1 = write */
262 #define ES_1371_LEGINT (1<<0) /* interrupt for legacy events; 0 = interrupt did occur */
264 #define ES_REG_CHANNEL_STATUS 0x1c /* R/W: first 32-bits from S/PDIF channel status block, es1373 */
266 #define ES_REG_SERIAL 0x20 /* R/W: Serial interface control register */
267 #define ES_1371_DAC_TEST (1<<22) /* DAC test mode enable */
268 #define ES_P2_END_INCO(o) (((o)&0x07)<<19)/* binary offset value to increment / loop end */
269 #define ES_P2_END_INCM (0x07<<19) /* mask for above */
270 #define ES_P2_END_INCI(i) (((i)>>16)&0x07)/* binary offset value to increment / loop end */
271 #define ES_P2_ST_INCO(o) (((o)&0x07)<<16)/* binary offset value to increment / start */
272 #define ES_P2_ST_INCM (0x07<<16) /* mask for above */
273 #define ES_P2_ST_INCI(i) (((i)<<16)&0x07)/* binary offset value to increment / start */
274 #define ES_R1_LOOP_SEL (1<<15) /* ADC; 0 - loop mode; 1 = stop mode */
275 #define ES_P2_LOOP_SEL (1<<14) /* DAC2; 0 - loop mode; 1 = stop mode */
276 #define ES_P1_LOOP_SEL (1<<13) /* DAC1; 0 - loop mode; 1 = stop mode */
277 #define ES_P2_PAUSE (1<<12) /* DAC2; 0 - play mode; 1 = pause mode */
278 #define ES_P1_PAUSE (1<<11) /* DAC1; 0 - play mode; 1 = pause mode */
279 #define ES_R1_INT_EN (1<<10) /* ADC interrupt enable */
280 #define ES_P2_INT_EN (1<<9) /* DAC2 interrupt enable */
281 #define ES_P1_INT_EN (1<<8) /* DAC1 interrupt enable */
282 #define ES_P1_SCT_RLD (1<<7) /* force sample counter reload for DAC1 */
283 #define ES_P2_DAC_SEN (1<<6) /* when stop mode: 0 - DAC2 play back zeros; 1 = DAC2 play back last sample */
284 #define ES_R1_MODEO(o) (((o)&0x03)<<4) /* ADC mode; 0 = 8-bit mono; 1 = 8-bit stereo; 2 = 16-bit mono; 3 = 16-bit stereo */
285 #define ES_R1_MODEM (0x03<<4) /* mask for above */
286 #define ES_R1_MODEI(i) (((i)>>4)&0x03)
287 #define ES_P2_MODEO(o) (((o)&0x03)<<2) /* DAC2 mode; -- '' -- */
288 #define ES_P2_MODEM (0x03<<2) /* mask for above */
289 #define ES_P2_MODEI(i) (((i)>>2)&0x03)
290 #define ES_P1_MODEO(o) (((o)&0x03)<<0) /* DAC1 mode; -- '' -- */
291 #define ES_P1_MODEM (0x03<<0) /* mask for above */
292 #define ES_P1_MODEI(i) (((i)>>0)&0x03)
294 #define ES_REG_DAC1_COUNT 0x24 /* R/W: DAC1 sample count register */
295 #define ES_REG_DAC2_COUNT 0x28 /* R/W: DAC2 sample count register */
296 #define ES_REG_ADC_COUNT 0x2c /* R/W: ADC sample count register */
297 #define ES_REG_CURR_COUNT(i) (((i)>>16)&0xffff)
298 #define ES_REG_COUNTO(o) (((o)&0xffff)<<0)
299 #define ES_REG_COUNTM (0xffff<<0)
300 #define ES_REG_COUNTI(i) (((i)>>0)&0xffff)
302 #define ES_REG_DAC1_FRAME 0x30 /* R/W: PAGE 0x0c; DAC1 frame address */
303 #define ES_REG_DAC1_SIZE 0x34 /* R/W: PAGE 0x0c; DAC1 frame size */
304 #define ES_REG_DAC2_FRAME 0x38 /* R/W: PAGE 0x0c; DAC2 frame address */
305 #define ES_REG_DAC2_SIZE 0x3c /* R/W: PAGE 0x0c; DAC2 frame size */
306 #define ES_REG_ADC_FRAME 0x30 /* R/W: PAGE 0x0d; ADC frame address */
307 #define ES_REG_ADC_SIZE 0x34 /* R/W: PAGE 0x0d; ADC frame size */
308 #define ES_REG_FCURR_COUNTO(o) (((o)&0xffff)<<16)
309 #define ES_REG_FCURR_COUNTM (0xffff<<16)
310 #define ES_REG_FCURR_COUNTI(i) (((i)>>14)&0x3fffc)
311 #define ES_REG_FSIZEO(o) (((o)&0xffff)<<0)
312 #define ES_REG_FSIZEM (0xffff<<0)
313 #define ES_REG_FSIZEI(i) (((i)>>0)&0xffff)
314 #define ES_REG_PHANTOM_FRAME 0x38 /* R/W: PAGE 0x0d: phantom frame address */
315 #define ES_REG_PHANTOM_COUNT 0x3c /* R/W: PAGE 0x0d: phantom frame count */
317 #define ES_REG_UART_FIFO 0x30 /* R/W: PAGE 0x0e; UART FIFO register */
318 #define ES_REG_UF_VALID (1<<8)
319 #define ES_REG_UF_BYTEO(o) (((o)&0xff)<<0)
320 #define ES_REG_UF_BYTEM (0xff<<0)
321 #define ES_REG_UF_BYTEI(i) (((i)>>0)&0xff)
328 #define ES_PAGE_DAC 0x0c
329 #define ES_PAGE_ADC 0x0d
330 #define ES_PAGE_UART 0x0e
331 #define ES_PAGE_UART1 0x0f
334 * Sample rate converter addresses
337 #define ES_SMPREG_DAC1 0x70
338 #define ES_SMPREG_DAC2 0x74
339 #define ES_SMPREG_ADC 0x78
340 #define ES_SMPREG_VOL_ADC 0x6c
341 #define ES_SMPREG_VOL_DAC1 0x7c
342 #define ES_SMPREG_VOL_DAC2 0x7e
343 #define ES_SMPREG_TRUNC_N 0x00
344 #define ES_SMPREG_INT_REGS 0x01
345 #define ES_SMPREG_ACCUM_FRAC 0x02
346 #define ES_SMPREG_VFREQ_FRAC 0x03
352 #define ES_1370_SRCLOCK 1411200
353 #define ES_1370_SRTODIV(x) (ES_1370_SRCLOCK/(x)-2)
359 #define ES_MODE_PLAY1 0x0001
360 #define ES_MODE_PLAY2 0x0002
361 #define ES_MODE_CAPTURE 0x0004
363 #define ES_MODE_OUTPUT 0x0001 /* for MIDI */
364 #define ES_MODE_INPUT 0x0002 /* for MIDI */
372 struct semaphore src_mutex
;
376 unsigned long playback1size
;
377 unsigned long playback2size
;
378 unsigned long capture3size
;
382 unsigned int uartm
; /* UART mode */
384 unsigned int ctrl
; /* control register */
385 unsigned int sctrl
; /* serial control register */
386 unsigned int cssr
; /* control status register */
387 unsigned int uartc
; /* uart control register */
388 unsigned int rev
; /* chip revision */
393 struct snd_ac97
*ac97
;
398 struct snd_ak4531
*ak4531
;
404 unsigned short subsystem_vendor_id
;
405 unsigned short subsystem_device_id
;
406 struct snd_card
*card
;
407 struct snd_pcm
*pcm1
; /* DAC1/ADC PCM */
408 struct snd_pcm
*pcm2
; /* DAC2 PCM */
409 struct snd_pcm_substream
*playback1_substream
;
410 struct snd_pcm_substream
*playback2_substream
;
411 struct snd_pcm_substream
*capture_substream
;
412 unsigned int p1_dma_size
;
413 unsigned int p2_dma_size
;
414 unsigned int c_dma_size
;
415 unsigned int p1_period_size
;
416 unsigned int p2_period_size
;
417 unsigned int c_period_size
;
418 struct snd_rawmidi
*rmidi
;
419 struct snd_rawmidi_substream
*midi_input
;
420 struct snd_rawmidi_substream
*midi_output
;
423 unsigned int spdif_default
;
424 unsigned int spdif_stream
;
427 struct snd_dma_buffer dma_bug
;
430 #ifdef SUPPORT_JOYSTICK
431 struct gameport
*gameport
;
435 static irqreturn_t
snd_audiopci_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
);
437 static struct pci_device_id snd_audiopci_ids
[] = {
439 { 0x1274, 0x5000, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, }, /* ES1370 */
442 { 0x1274, 0x1371, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, }, /* ES1371 */
443 { 0x1274, 0x5880, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, }, /* ES1373 - CT5880 */
444 { 0x1102, 0x8938, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0, }, /* Ectiva EV1938 */
449 MODULE_DEVICE_TABLE(pci
, snd_audiopci_ids
);
455 #define POLL_COUNT 0xa000
458 static unsigned int snd_es1370_fixed_rates
[] =
459 {5512, 11025, 22050, 44100};
460 static struct snd_pcm_hw_constraint_list snd_es1370_hw_constraints_rates
= {
462 .list
= snd_es1370_fixed_rates
,
465 static struct snd_ratnum es1370_clock
= {
466 .num
= ES_1370_SRCLOCK
,
471 static struct snd_pcm_hw_constraint_ratnums snd_es1370_hw_constraints_clock
= {
473 .rats
= &es1370_clock
,
476 static struct snd_ratden es1371_dac_clock
= {
477 .num_min
= 3000 * (1 << 15),
478 .num_max
= 48000 * (1 << 15),
482 static struct snd_pcm_hw_constraint_ratdens snd_es1371_hw_constraints_dac_clock
= {
484 .rats
= &es1371_dac_clock
,
486 static struct snd_ratnum es1371_adc_clock
= {
492 static struct snd_pcm_hw_constraint_ratnums snd_es1371_hw_constraints_adc_clock
= {
494 .rats
= &es1371_adc_clock
,
497 static const unsigned int snd_ensoniq_sample_shift
[] =
501 * common I/O routines
506 static unsigned int snd_es1371_wait_src_ready(struct ensoniq
* ensoniq
)
508 unsigned int t
, r
= 0;
510 for (t
= 0; t
< POLL_COUNT
; t
++) {
511 r
= inl(ES_REG(ensoniq
, 1371_SMPRATE
));
512 if ((r
& ES_1371_SRC_RAM_BUSY
) == 0)
516 snd_printk(KERN_ERR
"wait source ready timeout 0x%lx [0x%x]\n",
517 ES_REG(ensoniq
, 1371_SMPRATE
), r
);
521 static unsigned int snd_es1371_src_read(struct ensoniq
* ensoniq
, unsigned short reg
)
523 unsigned int temp
, i
, orig
, r
;
526 temp
= orig
= snd_es1371_wait_src_ready(ensoniq
);
528 /* expose the SRC state bits */
529 r
= temp
& (ES_1371_SRC_DISABLE
| ES_1371_DIS_P1
|
530 ES_1371_DIS_P2
| ES_1371_DIS_R1
);
531 r
|= ES_1371_SRC_RAM_ADDRO(reg
) | 0x10000;
532 outl(r
, ES_REG(ensoniq
, 1371_SMPRATE
));
534 /* now, wait for busy and the correct time to read */
535 temp
= snd_es1371_wait_src_ready(ensoniq
);
537 if ((temp
& 0x00870000) != 0x00010000) {
538 /* wait for the right state */
539 for (i
= 0; i
< POLL_COUNT
; i
++) {
540 temp
= inl(ES_REG(ensoniq
, 1371_SMPRATE
));
541 if ((temp
& 0x00870000) == 0x00010000)
546 /* hide the state bits */
547 r
= orig
& (ES_1371_SRC_DISABLE
| ES_1371_DIS_P1
|
548 ES_1371_DIS_P2
| ES_1371_DIS_R1
);
549 r
|= ES_1371_SRC_RAM_ADDRO(reg
);
550 outl(r
, ES_REG(ensoniq
, 1371_SMPRATE
));
555 static void snd_es1371_src_write(struct ensoniq
* ensoniq
,
556 unsigned short reg
, unsigned short data
)
560 r
= snd_es1371_wait_src_ready(ensoniq
) &
561 (ES_1371_SRC_DISABLE
| ES_1371_DIS_P1
|
562 ES_1371_DIS_P2
| ES_1371_DIS_R1
);
563 r
|= ES_1371_SRC_RAM_ADDRO(reg
) | ES_1371_SRC_RAM_DATAO(data
);
564 outl(r
| ES_1371_SRC_RAM_WE
, ES_REG(ensoniq
, 1371_SMPRATE
));
567 #endif /* CHIP1371 */
571 static void snd_es1370_codec_write(struct snd_ak4531
*ak4531
,
572 unsigned short reg
, unsigned short val
)
574 struct ensoniq
*ensoniq
= ak4531
->private_data
;
575 unsigned long end_time
= jiffies
+ HZ
/ 10;
578 printk("CODEC WRITE: reg = 0x%x, val = 0x%x (0x%x), creg = 0x%x\n",
579 reg
, val
, ES_1370_CODEC_WRITE(reg
, val
), ES_REG(ensoniq
, 1370_CODEC
));
582 if (!(inl(ES_REG(ensoniq
, STATUS
)) & ES_1370_CSTAT
)) {
583 outw(ES_1370_CODEC_WRITE(reg
, val
), ES_REG(ensoniq
, 1370_CODEC
));
586 schedule_timeout_uninterruptible(1);
587 } while (time_after(end_time
, jiffies
));
588 snd_printk(KERN_ERR
"codec write timeout, status = 0x%x\n",
589 inl(ES_REG(ensoniq
, STATUS
)));
592 #endif /* CHIP1370 */
596 static void snd_es1371_codec_write(struct snd_ac97
*ac97
,
597 unsigned short reg
, unsigned short val
)
599 struct ensoniq
*ensoniq
= ac97
->private_data
;
602 down(&ensoniq
->src_mutex
);
603 for (t
= 0; t
< POLL_COUNT
; t
++) {
604 if (!(inl(ES_REG(ensoniq
, 1371_CODEC
)) & ES_1371_CODEC_WIP
)) {
605 /* save the current state for latter */
606 x
= snd_es1371_wait_src_ready(ensoniq
);
607 outl((x
& (ES_1371_SRC_DISABLE
| ES_1371_DIS_P1
|
608 ES_1371_DIS_P2
| ES_1371_DIS_R1
)) | 0x00010000,
609 ES_REG(ensoniq
, 1371_SMPRATE
));
610 /* wait for not busy (state 0) first to avoid
612 for (t
= 0; t
< POLL_COUNT
; t
++) {
613 if ((inl(ES_REG(ensoniq
, 1371_SMPRATE
)) & 0x00870000) ==
617 /* wait for a SAFE time to write addr/data and then do it, dammit */
618 for (t
= 0; t
< POLL_COUNT
; t
++) {
619 if ((inl(ES_REG(ensoniq
, 1371_SMPRATE
)) & 0x00870000) ==
623 outl(ES_1371_CODEC_WRITE(reg
, val
), ES_REG(ensoniq
, 1371_CODEC
));
624 /* restore SRC reg */
625 snd_es1371_wait_src_ready(ensoniq
);
626 outl(x
, ES_REG(ensoniq
, 1371_SMPRATE
));
627 up(&ensoniq
->src_mutex
);
631 up(&ensoniq
->src_mutex
);
632 snd_printk(KERN_ERR
"codec write timeout at 0x%lx [0x%x]\n",
633 ES_REG(ensoniq
, 1371_CODEC
), inl(ES_REG(ensoniq
, 1371_CODEC
)));
636 static unsigned short snd_es1371_codec_read(struct snd_ac97
*ac97
,
639 struct ensoniq
*ensoniq
= ac97
->private_data
;
640 unsigned int t
, x
, fail
= 0;
643 down(&ensoniq
->src_mutex
);
644 for (t
= 0; t
< POLL_COUNT
; t
++) {
645 if (!(inl(ES_REG(ensoniq
, 1371_CODEC
)) & ES_1371_CODEC_WIP
)) {
646 /* save the current state for latter */
647 x
= snd_es1371_wait_src_ready(ensoniq
);
648 outl((x
& (ES_1371_SRC_DISABLE
| ES_1371_DIS_P1
|
649 ES_1371_DIS_P2
| ES_1371_DIS_R1
)) | 0x00010000,
650 ES_REG(ensoniq
, 1371_SMPRATE
));
651 /* wait for not busy (state 0) first to avoid
653 for (t
= 0; t
< POLL_COUNT
; t
++) {
654 if ((inl(ES_REG(ensoniq
, 1371_SMPRATE
)) & 0x00870000) ==
658 /* wait for a SAFE time to write addr/data and then do it, dammit */
659 for (t
= 0; t
< POLL_COUNT
; t
++) {
660 if ((inl(ES_REG(ensoniq
, 1371_SMPRATE
)) & 0x00870000) ==
664 outl(ES_1371_CODEC_READS(reg
), ES_REG(ensoniq
, 1371_CODEC
));
665 /* restore SRC reg */
666 snd_es1371_wait_src_ready(ensoniq
);
667 outl(x
, ES_REG(ensoniq
, 1371_SMPRATE
));
668 /* wait for WIP again */
669 for (t
= 0; t
< POLL_COUNT
; t
++) {
670 if (!(inl(ES_REG(ensoniq
, 1371_CODEC
)) & ES_1371_CODEC_WIP
))
673 /* now wait for the stinkin' data (RDY) */
674 for (t
= 0; t
< POLL_COUNT
; t
++) {
675 if ((x
= inl(ES_REG(ensoniq
, 1371_CODEC
))) & ES_1371_CODEC_RDY
) {
676 up(&ensoniq
->src_mutex
);
677 return ES_1371_CODEC_READ(x
);
680 up(&ensoniq
->src_mutex
);
682 snd_printk(KERN_ERR
"codec read timeout (final) "
683 "at 0x%lx, reg = 0x%x [0x%x]\n",
684 ES_REG(ensoniq
, 1371_CODEC
), reg
,
685 inl(ES_REG(ensoniq
, 1371_CODEC
)));
691 up(&ensoniq
->src_mutex
);
692 snd_printk(KERN_ERR
"es1371: codec read timeout at 0x%lx [0x%x]\n",
693 ES_REG(ensoniq
, 1371_CODEC
), inl(ES_REG(ensoniq
, 1371_CODEC
)));
697 static void snd_es1371_codec_wait(struct snd_ac97
*ac97
)
700 snd_es1371_codec_read(ac97
, AC97_RESET
);
701 snd_es1371_codec_read(ac97
, AC97_VENDOR_ID1
);
702 snd_es1371_codec_read(ac97
, AC97_VENDOR_ID2
);
706 static void snd_es1371_adc_rate(struct ensoniq
* ensoniq
, unsigned int rate
)
708 unsigned int n
, truncm
, freq
, result
;
710 down(&ensoniq
->src_mutex
);
712 if ((1 << n
) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
714 truncm
= (21 * n
- 1) | 1;
715 freq
= ((48000UL << 15) / rate
) * n
;
716 result
= (48000UL << 15) / (freq
/ n
);
720 snd_es1371_src_write(ensoniq
, ES_SMPREG_ADC
+ ES_SMPREG_TRUNC_N
,
721 (((239 - truncm
) >> 1) << 9) | (n
<< 4));
725 snd_es1371_src_write(ensoniq
, ES_SMPREG_ADC
+ ES_SMPREG_TRUNC_N
,
726 0x8000 | (((119 - truncm
) >> 1) << 9) | (n
<< 4));
728 snd_es1371_src_write(ensoniq
, ES_SMPREG_ADC
+ ES_SMPREG_INT_REGS
,
729 (snd_es1371_src_read(ensoniq
, ES_SMPREG_ADC
+
730 ES_SMPREG_INT_REGS
) & 0x00ff) |
731 ((freq
>> 5) & 0xfc00));
732 snd_es1371_src_write(ensoniq
, ES_SMPREG_ADC
+ ES_SMPREG_VFREQ_FRAC
, freq
& 0x7fff);
733 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_ADC
, n
<< 8);
734 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_ADC
+ 1, n
<< 8);
735 up(&ensoniq
->src_mutex
);
738 static void snd_es1371_dac1_rate(struct ensoniq
* ensoniq
, unsigned int rate
)
740 unsigned int freq
, r
;
742 down(&ensoniq
->src_mutex
);
743 freq
= ((rate
<< 15) + 1500) / 3000;
744 r
= (snd_es1371_wait_src_ready(ensoniq
) & (ES_1371_SRC_DISABLE
|
745 ES_1371_DIS_P2
| ES_1371_DIS_R1
)) |
747 outl(r
, ES_REG(ensoniq
, 1371_SMPRATE
));
748 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC1
+ ES_SMPREG_INT_REGS
,
749 (snd_es1371_src_read(ensoniq
, ES_SMPREG_DAC1
+
750 ES_SMPREG_INT_REGS
) & 0x00ff) |
751 ((freq
>> 5) & 0xfc00));
752 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC1
+ ES_SMPREG_VFREQ_FRAC
, freq
& 0x7fff);
753 r
= (snd_es1371_wait_src_ready(ensoniq
) & (ES_1371_SRC_DISABLE
|
754 ES_1371_DIS_P2
| ES_1371_DIS_R1
));
755 outl(r
, ES_REG(ensoniq
, 1371_SMPRATE
));
756 up(&ensoniq
->src_mutex
);
759 static void snd_es1371_dac2_rate(struct ensoniq
* ensoniq
, unsigned int rate
)
761 unsigned int freq
, r
;
763 down(&ensoniq
->src_mutex
);
764 freq
= ((rate
<< 15) + 1500) / 3000;
765 r
= (snd_es1371_wait_src_ready(ensoniq
) & (ES_1371_SRC_DISABLE
|
766 ES_1371_DIS_P1
| ES_1371_DIS_R1
)) |
768 outl(r
, ES_REG(ensoniq
, 1371_SMPRATE
));
769 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC2
+ ES_SMPREG_INT_REGS
,
770 (snd_es1371_src_read(ensoniq
, ES_SMPREG_DAC2
+
771 ES_SMPREG_INT_REGS
) & 0x00ff) |
772 ((freq
>> 5) & 0xfc00));
773 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC2
+ ES_SMPREG_VFREQ_FRAC
,
775 r
= (snd_es1371_wait_src_ready(ensoniq
) & (ES_1371_SRC_DISABLE
|
776 ES_1371_DIS_P1
| ES_1371_DIS_R1
));
777 outl(r
, ES_REG(ensoniq
, 1371_SMPRATE
));
778 up(&ensoniq
->src_mutex
);
781 #endif /* CHIP1371 */
783 static int snd_ensoniq_trigger(struct snd_pcm_substream
*substream
, int cmd
)
785 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
787 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
788 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
790 unsigned int what
= 0;
791 struct list_head
*pos
;
792 struct snd_pcm_substream
*s
;
793 snd_pcm_group_for_each(pos
, substream
) {
794 s
= snd_pcm_group_substream_entry(pos
);
795 if (s
== ensoniq
->playback1_substream
) {
797 snd_pcm_trigger_done(s
, substream
);
798 } else if (s
== ensoniq
->playback2_substream
) {
800 snd_pcm_trigger_done(s
, substream
);
801 } else if (s
== ensoniq
->capture_substream
)
804 spin_lock(&ensoniq
->reg_lock
);
805 if (cmd
== SNDRV_PCM_TRIGGER_PAUSE_PUSH
)
806 ensoniq
->sctrl
|= what
;
808 ensoniq
->sctrl
&= ~what
;
809 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
810 spin_unlock(&ensoniq
->reg_lock
);
813 case SNDRV_PCM_TRIGGER_START
:
814 case SNDRV_PCM_TRIGGER_STOP
:
816 unsigned int what
= 0;
817 struct list_head
*pos
;
818 struct snd_pcm_substream
*s
;
819 snd_pcm_group_for_each(pos
, substream
) {
820 s
= snd_pcm_group_substream_entry(pos
);
821 if (s
== ensoniq
->playback1_substream
) {
823 snd_pcm_trigger_done(s
, substream
);
824 } else if (s
== ensoniq
->playback2_substream
) {
826 snd_pcm_trigger_done(s
, substream
);
827 } else if (s
== ensoniq
->capture_substream
) {
829 snd_pcm_trigger_done(s
, substream
);
832 spin_lock(&ensoniq
->reg_lock
);
833 if (cmd
== SNDRV_PCM_TRIGGER_START
)
834 ensoniq
->ctrl
|= what
;
836 ensoniq
->ctrl
&= ~what
;
837 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
838 spin_unlock(&ensoniq
->reg_lock
);
851 static int snd_ensoniq_hw_params(struct snd_pcm_substream
*substream
,
852 struct snd_pcm_hw_params
*hw_params
)
854 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
857 static int snd_ensoniq_hw_free(struct snd_pcm_substream
*substream
)
859 return snd_pcm_lib_free_pages(substream
);
862 static int snd_ensoniq_playback1_prepare(struct snd_pcm_substream
*substream
)
864 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
865 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
866 unsigned int mode
= 0;
868 ensoniq
->p1_dma_size
= snd_pcm_lib_buffer_bytes(substream
);
869 ensoniq
->p1_period_size
= snd_pcm_lib_period_bytes(substream
);
870 if (snd_pcm_format_width(runtime
->format
) == 16)
872 if (runtime
->channels
> 1)
874 spin_lock_irq(&ensoniq
->reg_lock
);
875 ensoniq
->ctrl
&= ~ES_DAC1_EN
;
877 /* 48k doesn't need SRC (it breaks AC3-passthru) */
878 if (runtime
->rate
== 48000)
879 ensoniq
->ctrl
|= ES_1373_BYPASS_P1
;
881 ensoniq
->ctrl
&= ~ES_1373_BYPASS_P1
;
883 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
884 outl(ES_MEM_PAGEO(ES_PAGE_DAC
), ES_REG(ensoniq
, MEM_PAGE
));
885 outl(runtime
->dma_addr
, ES_REG(ensoniq
, DAC1_FRAME
));
886 outl((ensoniq
->p1_dma_size
>> 2) - 1, ES_REG(ensoniq
, DAC1_SIZE
));
887 ensoniq
->sctrl
&= ~(ES_P1_LOOP_SEL
| ES_P1_PAUSE
| ES_P1_SCT_RLD
| ES_P1_MODEM
);
888 ensoniq
->sctrl
|= ES_P1_INT_EN
| ES_P1_MODEO(mode
);
889 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
890 outl((ensoniq
->p1_period_size
>> snd_ensoniq_sample_shift
[mode
]) - 1,
891 ES_REG(ensoniq
, DAC1_COUNT
));
893 ensoniq
->ctrl
&= ~ES_1370_WTSRSELM
;
894 switch (runtime
->rate
) {
895 case 5512: ensoniq
->ctrl
|= ES_1370_WTSRSEL(0); break;
896 case 11025: ensoniq
->ctrl
|= ES_1370_WTSRSEL(1); break;
897 case 22050: ensoniq
->ctrl
|= ES_1370_WTSRSEL(2); break;
898 case 44100: ensoniq
->ctrl
|= ES_1370_WTSRSEL(3); break;
902 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
903 spin_unlock_irq(&ensoniq
->reg_lock
);
905 snd_es1371_dac1_rate(ensoniq
, runtime
->rate
);
910 static int snd_ensoniq_playback2_prepare(struct snd_pcm_substream
*substream
)
912 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
913 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
914 unsigned int mode
= 0;
916 ensoniq
->p2_dma_size
= snd_pcm_lib_buffer_bytes(substream
);
917 ensoniq
->p2_period_size
= snd_pcm_lib_period_bytes(substream
);
918 if (snd_pcm_format_width(runtime
->format
) == 16)
920 if (runtime
->channels
> 1)
922 spin_lock_irq(&ensoniq
->reg_lock
);
923 ensoniq
->ctrl
&= ~ES_DAC2_EN
;
924 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
925 outl(ES_MEM_PAGEO(ES_PAGE_DAC
), ES_REG(ensoniq
, MEM_PAGE
));
926 outl(runtime
->dma_addr
, ES_REG(ensoniq
, DAC2_FRAME
));
927 outl((ensoniq
->p2_dma_size
>> 2) - 1, ES_REG(ensoniq
, DAC2_SIZE
));
928 ensoniq
->sctrl
&= ~(ES_P2_LOOP_SEL
| ES_P2_PAUSE
| ES_P2_DAC_SEN
|
929 ES_P2_END_INCM
| ES_P2_ST_INCM
| ES_P2_MODEM
);
930 ensoniq
->sctrl
|= ES_P2_INT_EN
| ES_P2_MODEO(mode
) |
931 ES_P2_END_INCO(mode
& 2 ? 2 : 1) | ES_P2_ST_INCO(0);
932 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
933 outl((ensoniq
->p2_period_size
>> snd_ensoniq_sample_shift
[mode
]) - 1,
934 ES_REG(ensoniq
, DAC2_COUNT
));
936 if (!(ensoniq
->u
.es1370
.pclkdiv_lock
& ES_MODE_CAPTURE
)) {
937 ensoniq
->ctrl
&= ~ES_1370_PCLKDIVM
;
938 ensoniq
->ctrl
|= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime
->rate
));
939 ensoniq
->u
.es1370
.pclkdiv_lock
|= ES_MODE_PLAY2
;
942 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
943 spin_unlock_irq(&ensoniq
->reg_lock
);
945 snd_es1371_dac2_rate(ensoniq
, runtime
->rate
);
950 static int snd_ensoniq_capture_prepare(struct snd_pcm_substream
*substream
)
952 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
953 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
954 unsigned int mode
= 0;
956 ensoniq
->c_dma_size
= snd_pcm_lib_buffer_bytes(substream
);
957 ensoniq
->c_period_size
= snd_pcm_lib_period_bytes(substream
);
958 if (snd_pcm_format_width(runtime
->format
) == 16)
960 if (runtime
->channels
> 1)
962 spin_lock_irq(&ensoniq
->reg_lock
);
963 ensoniq
->ctrl
&= ~ES_ADC_EN
;
964 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
965 outl(ES_MEM_PAGEO(ES_PAGE_ADC
), ES_REG(ensoniq
, MEM_PAGE
));
966 outl(runtime
->dma_addr
, ES_REG(ensoniq
, ADC_FRAME
));
967 outl((ensoniq
->c_dma_size
>> 2) - 1, ES_REG(ensoniq
, ADC_SIZE
));
968 ensoniq
->sctrl
&= ~(ES_R1_LOOP_SEL
| ES_R1_MODEM
);
969 ensoniq
->sctrl
|= ES_R1_INT_EN
| ES_R1_MODEO(mode
);
970 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
971 outl((ensoniq
->c_period_size
>> snd_ensoniq_sample_shift
[mode
]) - 1,
972 ES_REG(ensoniq
, ADC_COUNT
));
974 if (!(ensoniq
->u
.es1370
.pclkdiv_lock
& ES_MODE_PLAY2
)) {
975 ensoniq
->ctrl
&= ~ES_1370_PCLKDIVM
;
976 ensoniq
->ctrl
|= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime
->rate
));
977 ensoniq
->u
.es1370
.pclkdiv_lock
|= ES_MODE_CAPTURE
;
980 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
981 spin_unlock_irq(&ensoniq
->reg_lock
);
983 snd_es1371_adc_rate(ensoniq
, runtime
->rate
);
988 static snd_pcm_uframes_t
snd_ensoniq_playback1_pointer(struct snd_pcm_substream
*substream
)
990 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
993 spin_lock(&ensoniq
->reg_lock
);
994 if (inl(ES_REG(ensoniq
, CONTROL
)) & ES_DAC1_EN
) {
995 outl(ES_MEM_PAGEO(ES_PAGE_DAC
), ES_REG(ensoniq
, MEM_PAGE
));
996 ptr
= ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq
, DAC1_SIZE
)));
997 ptr
= bytes_to_frames(substream
->runtime
, ptr
);
1001 spin_unlock(&ensoniq
->reg_lock
);
1005 static snd_pcm_uframes_t
snd_ensoniq_playback2_pointer(struct snd_pcm_substream
*substream
)
1007 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1010 spin_lock(&ensoniq
->reg_lock
);
1011 if (inl(ES_REG(ensoniq
, CONTROL
)) & ES_DAC2_EN
) {
1012 outl(ES_MEM_PAGEO(ES_PAGE_DAC
), ES_REG(ensoniq
, MEM_PAGE
));
1013 ptr
= ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq
, DAC2_SIZE
)));
1014 ptr
= bytes_to_frames(substream
->runtime
, ptr
);
1018 spin_unlock(&ensoniq
->reg_lock
);
1022 static snd_pcm_uframes_t
snd_ensoniq_capture_pointer(struct snd_pcm_substream
*substream
)
1024 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1027 spin_lock(&ensoniq
->reg_lock
);
1028 if (inl(ES_REG(ensoniq
, CONTROL
)) & ES_ADC_EN
) {
1029 outl(ES_MEM_PAGEO(ES_PAGE_ADC
), ES_REG(ensoniq
, MEM_PAGE
));
1030 ptr
= ES_REG_FCURR_COUNTI(inl(ES_REG(ensoniq
, ADC_SIZE
)));
1031 ptr
= bytes_to_frames(substream
->runtime
, ptr
);
1035 spin_unlock(&ensoniq
->reg_lock
);
1039 static struct snd_pcm_hardware snd_ensoniq_playback1
=
1041 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1042 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1043 SNDRV_PCM_INFO_MMAP_VALID
|
1044 SNDRV_PCM_INFO_PAUSE
| SNDRV_PCM_INFO_SYNC_START
),
1045 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1048 SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1050 (SNDRV_PCM_RATE_KNOT
| /* 5512Hz rate */
1051 SNDRV_PCM_RATE_11025
| SNDRV_PCM_RATE_22050
|
1052 SNDRV_PCM_RATE_44100
),
1058 .buffer_bytes_max
= (128*1024),
1059 .period_bytes_min
= 64,
1060 .period_bytes_max
= (128*1024),
1062 .periods_max
= 1024,
1066 static struct snd_pcm_hardware snd_ensoniq_playback2
=
1068 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1069 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1070 SNDRV_PCM_INFO_MMAP_VALID
| SNDRV_PCM_INFO_PAUSE
|
1071 SNDRV_PCM_INFO_SYNC_START
),
1072 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1073 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1078 .buffer_bytes_max
= (128*1024),
1079 .period_bytes_min
= 64,
1080 .period_bytes_max
= (128*1024),
1082 .periods_max
= 1024,
1086 static struct snd_pcm_hardware snd_ensoniq_capture
=
1088 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1089 SNDRV_PCM_INFO_BLOCK_TRANSFER
|
1090 SNDRV_PCM_INFO_MMAP_VALID
| SNDRV_PCM_INFO_SYNC_START
),
1091 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1092 .rates
= SNDRV_PCM_RATE_CONTINUOUS
| SNDRV_PCM_RATE_8000_48000
,
1097 .buffer_bytes_max
= (128*1024),
1098 .period_bytes_min
= 64,
1099 .period_bytes_max
= (128*1024),
1101 .periods_max
= 1024,
1105 static int snd_ensoniq_playback1_open(struct snd_pcm_substream
*substream
)
1107 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1108 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1110 ensoniq
->mode
|= ES_MODE_PLAY1
;
1111 ensoniq
->playback1_substream
= substream
;
1112 runtime
->hw
= snd_ensoniq_playback1
;
1113 snd_pcm_set_sync(substream
);
1114 spin_lock_irq(&ensoniq
->reg_lock
);
1115 if (ensoniq
->spdif
&& ensoniq
->playback2_substream
== NULL
)
1116 ensoniq
->spdif_stream
= ensoniq
->spdif_default
;
1117 spin_unlock_irq(&ensoniq
->reg_lock
);
1119 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
1120 &snd_es1370_hw_constraints_rates
);
1122 snd_pcm_hw_constraint_ratdens(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
1123 &snd_es1371_hw_constraints_dac_clock
);
1128 static int snd_ensoniq_playback2_open(struct snd_pcm_substream
*substream
)
1130 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1131 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1133 ensoniq
->mode
|= ES_MODE_PLAY2
;
1134 ensoniq
->playback2_substream
= substream
;
1135 runtime
->hw
= snd_ensoniq_playback2
;
1136 snd_pcm_set_sync(substream
);
1137 spin_lock_irq(&ensoniq
->reg_lock
);
1138 if (ensoniq
->spdif
&& ensoniq
->playback1_substream
== NULL
)
1139 ensoniq
->spdif_stream
= ensoniq
->spdif_default
;
1140 spin_unlock_irq(&ensoniq
->reg_lock
);
1142 snd_pcm_hw_constraint_ratnums(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
1143 &snd_es1370_hw_constraints_clock
);
1145 snd_pcm_hw_constraint_ratdens(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
1146 &snd_es1371_hw_constraints_dac_clock
);
1151 static int snd_ensoniq_capture_open(struct snd_pcm_substream
*substream
)
1153 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1154 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
1156 ensoniq
->mode
|= ES_MODE_CAPTURE
;
1157 ensoniq
->capture_substream
= substream
;
1158 runtime
->hw
= snd_ensoniq_capture
;
1159 snd_pcm_set_sync(substream
);
1161 snd_pcm_hw_constraint_ratnums(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
1162 &snd_es1370_hw_constraints_clock
);
1164 snd_pcm_hw_constraint_ratnums(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
1165 &snd_es1371_hw_constraints_adc_clock
);
1170 static int snd_ensoniq_playback1_close(struct snd_pcm_substream
*substream
)
1172 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1174 ensoniq
->playback1_substream
= NULL
;
1175 ensoniq
->mode
&= ~ES_MODE_PLAY1
;
1179 static int snd_ensoniq_playback2_close(struct snd_pcm_substream
*substream
)
1181 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1183 ensoniq
->playback2_substream
= NULL
;
1184 spin_lock_irq(&ensoniq
->reg_lock
);
1186 ensoniq
->u
.es1370
.pclkdiv_lock
&= ~ES_MODE_PLAY2
;
1188 ensoniq
->mode
&= ~ES_MODE_PLAY2
;
1189 spin_unlock_irq(&ensoniq
->reg_lock
);
1193 static int snd_ensoniq_capture_close(struct snd_pcm_substream
*substream
)
1195 struct ensoniq
*ensoniq
= snd_pcm_substream_chip(substream
);
1197 ensoniq
->capture_substream
= NULL
;
1198 spin_lock_irq(&ensoniq
->reg_lock
);
1200 ensoniq
->u
.es1370
.pclkdiv_lock
&= ~ES_MODE_CAPTURE
;
1202 ensoniq
->mode
&= ~ES_MODE_CAPTURE
;
1203 spin_unlock_irq(&ensoniq
->reg_lock
);
1207 static struct snd_pcm_ops snd_ensoniq_playback1_ops
= {
1208 .open
= snd_ensoniq_playback1_open
,
1209 .close
= snd_ensoniq_playback1_close
,
1210 .ioctl
= snd_pcm_lib_ioctl
,
1211 .hw_params
= snd_ensoniq_hw_params
,
1212 .hw_free
= snd_ensoniq_hw_free
,
1213 .prepare
= snd_ensoniq_playback1_prepare
,
1214 .trigger
= snd_ensoniq_trigger
,
1215 .pointer
= snd_ensoniq_playback1_pointer
,
1218 static struct snd_pcm_ops snd_ensoniq_playback2_ops
= {
1219 .open
= snd_ensoniq_playback2_open
,
1220 .close
= snd_ensoniq_playback2_close
,
1221 .ioctl
= snd_pcm_lib_ioctl
,
1222 .hw_params
= snd_ensoniq_hw_params
,
1223 .hw_free
= snd_ensoniq_hw_free
,
1224 .prepare
= snd_ensoniq_playback2_prepare
,
1225 .trigger
= snd_ensoniq_trigger
,
1226 .pointer
= snd_ensoniq_playback2_pointer
,
1229 static struct snd_pcm_ops snd_ensoniq_capture_ops
= {
1230 .open
= snd_ensoniq_capture_open
,
1231 .close
= snd_ensoniq_capture_close
,
1232 .ioctl
= snd_pcm_lib_ioctl
,
1233 .hw_params
= snd_ensoniq_hw_params
,
1234 .hw_free
= snd_ensoniq_hw_free
,
1235 .prepare
= snd_ensoniq_capture_prepare
,
1236 .trigger
= snd_ensoniq_trigger
,
1237 .pointer
= snd_ensoniq_capture_pointer
,
1240 static int __devinit
snd_ensoniq_pcm(struct ensoniq
* ensoniq
, int device
,
1241 struct snd_pcm
** rpcm
)
1243 struct snd_pcm
*pcm
;
1249 err
= snd_pcm_new(ensoniq
->card
, "ES1370/1", device
, 1, 1, &pcm
);
1251 err
= snd_pcm_new(ensoniq
->card
, "ES1371/1", device
, 1, 1, &pcm
);
1257 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_ensoniq_playback2_ops
);
1259 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_ensoniq_playback1_ops
);
1261 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_ensoniq_capture_ops
);
1263 pcm
->private_data
= ensoniq
;
1264 pcm
->info_flags
= 0;
1266 strcpy(pcm
->name
, "ES1370 DAC2/ADC");
1268 strcpy(pcm
->name
, "ES1371 DAC2/ADC");
1270 ensoniq
->pcm1
= pcm
;
1272 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1273 snd_dma_pci_data(ensoniq
->pci
), 64*1024, 128*1024);
1280 static int __devinit
snd_ensoniq_pcm2(struct ensoniq
* ensoniq
, int device
,
1281 struct snd_pcm
** rpcm
)
1283 struct snd_pcm
*pcm
;
1289 err
= snd_pcm_new(ensoniq
->card
, "ES1370/2", device
, 1, 0, &pcm
);
1291 err
= snd_pcm_new(ensoniq
->card
, "ES1371/2", device
, 1, 0, &pcm
);
1297 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_ensoniq_playback1_ops
);
1299 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_ensoniq_playback2_ops
);
1301 pcm
->private_data
= ensoniq
;
1302 pcm
->info_flags
= 0;
1304 strcpy(pcm
->name
, "ES1370 DAC1");
1306 strcpy(pcm
->name
, "ES1371 DAC1");
1308 ensoniq
->pcm2
= pcm
;
1310 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1311 snd_dma_pci_data(ensoniq
->pci
), 64*1024, 128*1024);
1323 * ENS1371 mixer (including SPDIF interface)
1326 static int snd_ens1373_spdif_info(struct snd_kcontrol
*kcontrol
,
1327 struct snd_ctl_elem_info
*uinfo
)
1329 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1334 static int snd_ens1373_spdif_default_get(struct snd_kcontrol
*kcontrol
,
1335 struct snd_ctl_elem_value
*ucontrol
)
1337 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1338 spin_lock_irq(&ensoniq
->reg_lock
);
1339 ucontrol
->value
.iec958
.status
[0] = (ensoniq
->spdif_default
>> 0) & 0xff;
1340 ucontrol
->value
.iec958
.status
[1] = (ensoniq
->spdif_default
>> 8) & 0xff;
1341 ucontrol
->value
.iec958
.status
[2] = (ensoniq
->spdif_default
>> 16) & 0xff;
1342 ucontrol
->value
.iec958
.status
[3] = (ensoniq
->spdif_default
>> 24) & 0xff;
1343 spin_unlock_irq(&ensoniq
->reg_lock
);
1347 static int snd_ens1373_spdif_default_put(struct snd_kcontrol
*kcontrol
,
1348 struct snd_ctl_elem_value
*ucontrol
)
1350 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1354 val
= ((u32
)ucontrol
->value
.iec958
.status
[0] << 0) |
1355 ((u32
)ucontrol
->value
.iec958
.status
[1] << 8) |
1356 ((u32
)ucontrol
->value
.iec958
.status
[2] << 16) |
1357 ((u32
)ucontrol
->value
.iec958
.status
[3] << 24);
1358 spin_lock_irq(&ensoniq
->reg_lock
);
1359 change
= ensoniq
->spdif_default
!= val
;
1360 ensoniq
->spdif_default
= val
;
1361 if (change
&& ensoniq
->playback1_substream
== NULL
&&
1362 ensoniq
->playback2_substream
== NULL
)
1363 outl(val
, ES_REG(ensoniq
, CHANNEL_STATUS
));
1364 spin_unlock_irq(&ensoniq
->reg_lock
);
1368 static int snd_ens1373_spdif_mask_get(struct snd_kcontrol
*kcontrol
,
1369 struct snd_ctl_elem_value
*ucontrol
)
1371 ucontrol
->value
.iec958
.status
[0] = 0xff;
1372 ucontrol
->value
.iec958
.status
[1] = 0xff;
1373 ucontrol
->value
.iec958
.status
[2] = 0xff;
1374 ucontrol
->value
.iec958
.status
[3] = 0xff;
1378 static int snd_ens1373_spdif_stream_get(struct snd_kcontrol
*kcontrol
,
1379 struct snd_ctl_elem_value
*ucontrol
)
1381 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1382 spin_lock_irq(&ensoniq
->reg_lock
);
1383 ucontrol
->value
.iec958
.status
[0] = (ensoniq
->spdif_stream
>> 0) & 0xff;
1384 ucontrol
->value
.iec958
.status
[1] = (ensoniq
->spdif_stream
>> 8) & 0xff;
1385 ucontrol
->value
.iec958
.status
[2] = (ensoniq
->spdif_stream
>> 16) & 0xff;
1386 ucontrol
->value
.iec958
.status
[3] = (ensoniq
->spdif_stream
>> 24) & 0xff;
1387 spin_unlock_irq(&ensoniq
->reg_lock
);
1391 static int snd_ens1373_spdif_stream_put(struct snd_kcontrol
*kcontrol
,
1392 struct snd_ctl_elem_value
*ucontrol
)
1394 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1398 val
= ((u32
)ucontrol
->value
.iec958
.status
[0] << 0) |
1399 ((u32
)ucontrol
->value
.iec958
.status
[1] << 8) |
1400 ((u32
)ucontrol
->value
.iec958
.status
[2] << 16) |
1401 ((u32
)ucontrol
->value
.iec958
.status
[3] << 24);
1402 spin_lock_irq(&ensoniq
->reg_lock
);
1403 change
= ensoniq
->spdif_stream
!= val
;
1404 ensoniq
->spdif_stream
= val
;
1405 if (change
&& (ensoniq
->playback1_substream
!= NULL
||
1406 ensoniq
->playback2_substream
!= NULL
))
1407 outl(val
, ES_REG(ensoniq
, CHANNEL_STATUS
));
1408 spin_unlock_irq(&ensoniq
->reg_lock
);
1412 #define ES1371_SPDIF(xname) \
1413 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_es1371_spdif_info, \
1414 .get = snd_es1371_spdif_get, .put = snd_es1371_spdif_put }
1416 static int snd_es1371_spdif_info(struct snd_kcontrol
*kcontrol
,
1417 struct snd_ctl_elem_info
*uinfo
)
1419 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
1421 uinfo
->value
.integer
.min
= 0;
1422 uinfo
->value
.integer
.max
= 1;
1426 static int snd_es1371_spdif_get(struct snd_kcontrol
*kcontrol
,
1427 struct snd_ctl_elem_value
*ucontrol
)
1429 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1431 spin_lock_irq(&ensoniq
->reg_lock
);
1432 ucontrol
->value
.integer
.value
[0] = ensoniq
->ctrl
& ES_1373_SPDIF_THRU
? 1 : 0;
1433 spin_unlock_irq(&ensoniq
->reg_lock
);
1437 static int snd_es1371_spdif_put(struct snd_kcontrol
*kcontrol
,
1438 struct snd_ctl_elem_value
*ucontrol
)
1440 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1441 unsigned int nval1
, nval2
;
1444 nval1
= ucontrol
->value
.integer
.value
[0] ? ES_1373_SPDIF_THRU
: 0;
1445 nval2
= ucontrol
->value
.integer
.value
[0] ? ES_1373_SPDIF_EN
: 0;
1446 spin_lock_irq(&ensoniq
->reg_lock
);
1447 change
= (ensoniq
->ctrl
& ES_1373_SPDIF_THRU
) != nval1
;
1448 ensoniq
->ctrl
&= ~ES_1373_SPDIF_THRU
;
1449 ensoniq
->ctrl
|= nval1
;
1450 ensoniq
->cssr
&= ~ES_1373_SPDIF_EN
;
1451 ensoniq
->cssr
|= nval2
;
1452 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1453 outl(ensoniq
->cssr
, ES_REG(ensoniq
, STATUS
));
1454 spin_unlock_irq(&ensoniq
->reg_lock
);
1459 /* spdif controls */
1460 static struct snd_kcontrol_new snd_es1371_mixer_spdif
[] __devinitdata
= {
1461 ES1371_SPDIF(SNDRV_CTL_NAME_IEC958("",PLAYBACK
,SWITCH
)),
1463 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1464 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
1465 .info
= snd_ens1373_spdif_info
,
1466 .get
= snd_ens1373_spdif_default_get
,
1467 .put
= snd_ens1373_spdif_default_put
,
1470 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
1471 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1472 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,MASK
),
1473 .info
= snd_ens1373_spdif_info
,
1474 .get
= snd_ens1373_spdif_mask_get
1477 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1478 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
1479 .info
= snd_ens1373_spdif_info
,
1480 .get
= snd_ens1373_spdif_stream_get
,
1481 .put
= snd_ens1373_spdif_stream_put
1486 static int snd_es1373_rear_info(struct snd_kcontrol
*kcontrol
,
1487 struct snd_ctl_elem_info
*uinfo
)
1489 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
1491 uinfo
->value
.integer
.min
= 0;
1492 uinfo
->value
.integer
.max
= 1;
1496 static int snd_es1373_rear_get(struct snd_kcontrol
*kcontrol
,
1497 struct snd_ctl_elem_value
*ucontrol
)
1499 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1502 spin_lock_irq(&ensoniq
->reg_lock
);
1503 if ((ensoniq
->cssr
& (ES_1373_REAR_BIT27
|ES_1373_REAR_BIT26
|
1504 ES_1373_REAR_BIT24
)) == ES_1373_REAR_BIT26
)
1506 ucontrol
->value
.integer
.value
[0] = val
;
1507 spin_unlock_irq(&ensoniq
->reg_lock
);
1511 static int snd_es1373_rear_put(struct snd_kcontrol
*kcontrol
,
1512 struct snd_ctl_elem_value
*ucontrol
)
1514 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1518 nval1
= ucontrol
->value
.integer
.value
[0] ?
1519 ES_1373_REAR_BIT26
: (ES_1373_REAR_BIT27
|ES_1373_REAR_BIT24
);
1520 spin_lock_irq(&ensoniq
->reg_lock
);
1521 change
= (ensoniq
->cssr
& (ES_1373_REAR_BIT27
|
1522 ES_1373_REAR_BIT26
|ES_1373_REAR_BIT24
)) != nval1
;
1523 ensoniq
->cssr
&= ~(ES_1373_REAR_BIT27
|ES_1373_REAR_BIT26
|ES_1373_REAR_BIT24
);
1524 ensoniq
->cssr
|= nval1
;
1525 outl(ensoniq
->cssr
, ES_REG(ensoniq
, STATUS
));
1526 spin_unlock_irq(&ensoniq
->reg_lock
);
1530 static struct snd_kcontrol_new snd_ens1373_rear __devinitdata
=
1532 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
1533 .name
= "AC97 2ch->4ch Copy Switch",
1534 .info
= snd_es1373_rear_info
,
1535 .get
= snd_es1373_rear_get
,
1536 .put
= snd_es1373_rear_put
,
1539 static int snd_es1373_line_info(struct snd_kcontrol
*kcontrol
,
1540 struct snd_ctl_elem_info
*uinfo
)
1542 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
1544 uinfo
->value
.integer
.min
= 0;
1545 uinfo
->value
.integer
.max
= 1;
1549 static int snd_es1373_line_get(struct snd_kcontrol
*kcontrol
,
1550 struct snd_ctl_elem_value
*ucontrol
)
1552 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1555 spin_lock_irq(&ensoniq
->reg_lock
);
1556 if ((ensoniq
->ctrl
& ES_1371_GPIO_OUTM
) >= 4)
1558 ucontrol
->value
.integer
.value
[0] = val
;
1559 spin_unlock_irq(&ensoniq
->reg_lock
);
1563 static int snd_es1373_line_put(struct snd_kcontrol
*kcontrol
,
1564 struct snd_ctl_elem_value
*ucontrol
)
1566 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1570 spin_lock_irq(&ensoniq
->reg_lock
);
1571 ctrl
= ensoniq
->ctrl
;
1572 if (ucontrol
->value
.integer
.value
[0])
1573 ensoniq
->ctrl
|= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */
1575 ensoniq
->ctrl
&= ~ES_1371_GPIO_OUT(4);
1576 changed
= (ctrl
!= ensoniq
->ctrl
);
1578 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1579 spin_unlock_irq(&ensoniq
->reg_lock
);
1583 static struct snd_kcontrol_new snd_ens1373_line __devinitdata
=
1585 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
1586 .name
= "Line In->Rear Out Switch",
1587 .info
= snd_es1373_line_info
,
1588 .get
= snd_es1373_line_get
,
1589 .put
= snd_es1373_line_put
,
1592 static void snd_ensoniq_mixer_free_ac97(struct snd_ac97
*ac97
)
1594 struct ensoniq
*ensoniq
= ac97
->private_data
;
1595 ensoniq
->u
.es1371
.ac97
= NULL
;
1599 unsigned short vid
; /* vendor ID */
1600 unsigned short did
; /* device ID */
1601 unsigned char rev
; /* revision */
1602 } es1371_spdif_present
[] __devinitdata
= {
1603 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_CT5880
, .rev
= CT5880REV_CT5880_C
},
1604 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_CT5880
, .rev
= CT5880REV_CT5880_D
},
1605 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_CT5880
, .rev
= CT5880REV_CT5880_E
},
1606 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_ES1371
, .rev
= ES1371REV_CT5880_A
},
1607 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_ES1371
, .rev
= ES1371REV_ES1373_8
},
1608 { .vid
= PCI_ANY_ID
, .did
= PCI_ANY_ID
}
1611 static int snd_ensoniq_1371_mixer(struct ensoniq
* ensoniq
)
1613 struct snd_card
*card
= ensoniq
->card
;
1614 struct snd_ac97_bus
*pbus
;
1615 struct snd_ac97_template ac97
;
1617 static struct snd_ac97_bus_ops ops
= {
1618 .write
= snd_es1371_codec_write
,
1619 .read
= snd_es1371_codec_read
,
1620 .wait
= snd_es1371_codec_wait
,
1623 if ((err
= snd_ac97_bus(card
, 0, &ops
, NULL
, &pbus
)) < 0)
1626 memset(&ac97
, 0, sizeof(ac97
));
1627 ac97
.private_data
= ensoniq
;
1628 ac97
.private_free
= snd_ensoniq_mixer_free_ac97
;
1629 ac97
.scaps
= AC97_SCAP_AUDIO
;
1630 if ((err
= snd_ac97_mixer(pbus
, &ac97
, &ensoniq
->u
.es1371
.ac97
)) < 0)
1632 for (idx
= 0; es1371_spdif_present
[idx
].vid
!= (unsigned short)PCI_ANY_ID
; idx
++)
1633 if (ensoniq
->pci
->vendor
== es1371_spdif_present
[idx
].vid
&&
1634 ensoniq
->pci
->device
== es1371_spdif_present
[idx
].did
&&
1635 ensoniq
->rev
== es1371_spdif_present
[idx
].rev
) {
1636 struct snd_kcontrol
*kctl
;
1639 ensoniq
->spdif_default
= ensoniq
->spdif_stream
=
1640 SNDRV_PCM_DEFAULT_CON_SPDIF
;
1641 outl(ensoniq
->spdif_default
, ES_REG(ensoniq
, CHANNEL_STATUS
));
1643 if (ensoniq
->u
.es1371
.ac97
->ext_id
& AC97_EI_SPDIF
)
1646 for (i
= 0; i
< (int)ARRAY_SIZE(snd_es1371_mixer_spdif
); i
++) {
1647 kctl
= snd_ctl_new1(&snd_es1371_mixer_spdif
[i
], ensoniq
);
1650 kctl
->id
.index
= index
;
1651 if ((err
= snd_ctl_add(card
, kctl
)) < 0)
1656 if (ensoniq
->u
.es1371
.ac97
->ext_id
& AC97_EI_SDAC
) {
1657 /* mirror rear to front speakers */
1658 ensoniq
->cssr
&= ~(ES_1373_REAR_BIT27
|ES_1373_REAR_BIT24
);
1659 ensoniq
->cssr
|= ES_1373_REAR_BIT26
;
1660 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_ens1373_rear
, ensoniq
));
1664 if (((ensoniq
->subsystem_vendor_id
== 0x1274) &&
1665 (ensoniq
->subsystem_device_id
== 0x2000)) || /* GA-7DXR */
1666 ((ensoniq
->subsystem_vendor_id
== 0x1458) &&
1667 (ensoniq
->subsystem_device_id
== 0xa000))) { /* GA-8IEXP */
1668 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_ens1373_line
, ensoniq
));
1676 #endif /* CHIP1371 */
1678 /* generic control callbacks for ens1370 */
1680 #define ENSONIQ_CONTROL(xname, mask) \
1681 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, .name = xname, .info = snd_ensoniq_control_info, \
1682 .get = snd_ensoniq_control_get, .put = snd_ensoniq_control_put, \
1683 .private_value = mask }
1685 static int snd_ensoniq_control_info(struct snd_kcontrol
*kcontrol
,
1686 struct snd_ctl_elem_info
*uinfo
)
1688 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
1690 uinfo
->value
.integer
.min
= 0;
1691 uinfo
->value
.integer
.max
= 1;
1695 static int snd_ensoniq_control_get(struct snd_kcontrol
*kcontrol
,
1696 struct snd_ctl_elem_value
*ucontrol
)
1698 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1699 int mask
= kcontrol
->private_value
;
1701 spin_lock_irq(&ensoniq
->reg_lock
);
1702 ucontrol
->value
.integer
.value
[0] = ensoniq
->ctrl
& mask
? 1 : 0;
1703 spin_unlock_irq(&ensoniq
->reg_lock
);
1707 static int snd_ensoniq_control_put(struct snd_kcontrol
*kcontrol
,
1708 struct snd_ctl_elem_value
*ucontrol
)
1710 struct ensoniq
*ensoniq
= snd_kcontrol_chip(kcontrol
);
1711 int mask
= kcontrol
->private_value
;
1715 nval
= ucontrol
->value
.integer
.value
[0] ? mask
: 0;
1716 spin_lock_irq(&ensoniq
->reg_lock
);
1717 change
= (ensoniq
->ctrl
& mask
) != nval
;
1718 ensoniq
->ctrl
&= ~mask
;
1719 ensoniq
->ctrl
|= nval
;
1720 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1721 spin_unlock_irq(&ensoniq
->reg_lock
);
1729 static struct snd_kcontrol_new snd_es1370_controls
[2] __devinitdata
= {
1730 ENSONIQ_CONTROL("PCM 0 Output also on Line-In Jack", ES_1370_XCTL0
),
1731 ENSONIQ_CONTROL("Mic +5V bias", ES_1370_XCTL1
)
1734 #define ES1370_CONTROLS ARRAY_SIZE(snd_es1370_controls)
1736 static void snd_ensoniq_mixer_free_ak4531(struct snd_ak4531
*ak4531
)
1738 struct ensoniq
*ensoniq
= ak4531
->private_data
;
1739 ensoniq
->u
.es1370
.ak4531
= NULL
;
1742 static int __devinit
snd_ensoniq_1370_mixer(struct ensoniq
* ensoniq
)
1744 struct snd_card
*card
= ensoniq
->card
;
1745 struct snd_ak4531 ak4531
;
1749 /* try reset AK4531 */
1750 outw(ES_1370_CODEC_WRITE(AK4531_RESET
, 0x02), ES_REG(ensoniq
, 1370_CODEC
));
1751 inw(ES_REG(ensoniq
, 1370_CODEC
));
1753 outw(ES_1370_CODEC_WRITE(AK4531_RESET
, 0x03), ES_REG(ensoniq
, 1370_CODEC
));
1754 inw(ES_REG(ensoniq
, 1370_CODEC
));
1757 memset(&ak4531
, 0, sizeof(ak4531
));
1758 ak4531
.write
= snd_es1370_codec_write
;
1759 ak4531
.private_data
= ensoniq
;
1760 ak4531
.private_free
= snd_ensoniq_mixer_free_ak4531
;
1761 if ((err
= snd_ak4531_mixer(card
, &ak4531
, &ensoniq
->u
.es1370
.ak4531
)) < 0)
1763 for (idx
= 0; idx
< ES1370_CONTROLS
; idx
++) {
1764 err
= snd_ctl_add(card
, snd_ctl_new1(&snd_es1370_controls
[idx
], ensoniq
));
1771 #endif /* CHIP1370 */
1773 #ifdef SUPPORT_JOYSTICK
1776 static int __devinit
snd_ensoniq_get_joystick_port(int dev
)
1778 switch (joystick_port
[dev
]) {
1779 case 0: /* disabled */
1780 case 1: /* auto-detect */
1785 return joystick_port
[dev
];
1788 printk(KERN_ERR
"ens1371: invalid joystick port %#x", joystick_port
[dev
]);
1793 static inline int snd_ensoniq_get_joystick_port(int dev
)
1795 return joystick
[dev
] ? 0x200 : 0;
1799 static int __devinit
snd_ensoniq_create_gameport(struct ensoniq
*ensoniq
, int dev
)
1801 struct gameport
*gp
;
1804 io_port
= snd_ensoniq_get_joystick_port(dev
);
1810 case 1: /* auto_detect */
1811 for (io_port
= 0x200; io_port
<= 0x218; io_port
+= 8)
1812 if (request_region(io_port
, 8, "ens137x: gameport"))
1814 if (io_port
> 0x218) {
1815 printk(KERN_WARNING
"ens137x: no gameport ports available\n");
1821 if (!request_region(io_port
, 8, "ens137x: gameport")) {
1822 printk(KERN_WARNING
"ens137x: gameport io port 0x%#x in use\n",
1829 ensoniq
->gameport
= gp
= gameport_allocate_port();
1831 printk(KERN_ERR
"ens137x: cannot allocate memory for gameport\n");
1832 release_region(io_port
, 8);
1836 gameport_set_name(gp
, "ES137x");
1837 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(ensoniq
->pci
));
1838 gameport_set_dev_parent(gp
, &ensoniq
->pci
->dev
);
1841 ensoniq
->ctrl
|= ES_JYSTK_EN
;
1843 ensoniq
->ctrl
&= ~ES_1371_JOY_ASELM
;
1844 ensoniq
->ctrl
|= ES_1371_JOY_ASEL((io_port
- 0x200) / 8);
1846 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1848 gameport_register_port(ensoniq
->gameport
);
1853 static void snd_ensoniq_free_gameport(struct ensoniq
*ensoniq
)
1855 if (ensoniq
->gameport
) {
1856 int port
= ensoniq
->gameport
->io
;
1858 gameport_unregister_port(ensoniq
->gameport
);
1859 ensoniq
->gameport
= NULL
;
1860 ensoniq
->ctrl
&= ~ES_JYSTK_EN
;
1861 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1862 release_region(port
, 8);
1866 static inline int snd_ensoniq_create_gameport(struct ensoniq
*ensoniq
, long port
) { return -ENOSYS
; }
1867 static inline void snd_ensoniq_free_gameport(struct ensoniq
*ensoniq
) { }
1868 #endif /* SUPPORT_JOYSTICK */
1874 static void snd_ensoniq_proc_read(struct snd_info_entry
*entry
,
1875 struct snd_info_buffer
*buffer
)
1877 struct ensoniq
*ensoniq
= entry
->private_data
;
1880 snd_iprintf(buffer
, "Ensoniq AudioPCI ES1370\n\n");
1882 snd_iprintf(buffer
, "Ensoniq AudioPCI ES1371\n\n");
1884 snd_iprintf(buffer
, "Joystick enable : %s\n",
1885 ensoniq
->ctrl
& ES_JYSTK_EN
? "on" : "off");
1887 snd_iprintf(buffer
, "MIC +5V bias : %s\n",
1888 ensoniq
->ctrl
& ES_1370_XCTL1
? "on" : "off");
1889 snd_iprintf(buffer
, "Line In to AOUT : %s\n",
1890 ensoniq
->ctrl
& ES_1370_XCTL0
? "on" : "off");
1892 snd_iprintf(buffer
, "Joystick port : 0x%x\n",
1893 (ES_1371_JOY_ASELI(ensoniq
->ctrl
) * 8) + 0x200);
1897 static void __devinit
snd_ensoniq_proc_init(struct ensoniq
* ensoniq
)
1899 struct snd_info_entry
*entry
;
1901 if (! snd_card_proc_new(ensoniq
->card
, "audiopci", &entry
))
1902 snd_info_set_text_ops(entry
, ensoniq
, 1024, snd_ensoniq_proc_read
);
1909 static int snd_ensoniq_free(struct ensoniq
*ensoniq
)
1911 snd_ensoniq_free_gameport(ensoniq
);
1912 if (ensoniq
->irq
< 0)
1915 outl(ES_1370_SERR_DISABLE
, ES_REG(ensoniq
, CONTROL
)); /* switch everything off */
1916 outl(0, ES_REG(ensoniq
, SERIAL
)); /* clear serial interface */
1918 outl(0, ES_REG(ensoniq
, CONTROL
)); /* switch everything off */
1919 outl(0, ES_REG(ensoniq
, SERIAL
)); /* clear serial interface */
1921 synchronize_irq(ensoniq
->irq
);
1922 pci_set_power_state(ensoniq
->pci
, 3);
1925 if (ensoniq
->dma_bug
.area
)
1926 snd_dma_free_pages(&ensoniq
->dma_bug
);
1928 if (ensoniq
->irq
>= 0)
1929 free_irq(ensoniq
->irq
, ensoniq
);
1930 pci_release_regions(ensoniq
->pci
);
1931 pci_disable_device(ensoniq
->pci
);
1936 static int snd_ensoniq_dev_free(struct snd_device
*device
)
1938 struct ensoniq
*ensoniq
= device
->device_data
;
1939 return snd_ensoniq_free(ensoniq
);
1944 unsigned short svid
; /* subsystem vendor ID */
1945 unsigned short sdid
; /* subsystem device ID */
1946 } es1371_amplifier_hack
[] = {
1947 { .svid
= 0x107b, .sdid
= 0x2150 }, /* Gateway Solo 2150 */
1948 { .svid
= 0x13bd, .sdid
= 0x100c }, /* EV1938 on Mebius PC-MJ100V */
1949 { .svid
= 0x1102, .sdid
= 0x5938 }, /* Targa Xtender300 */
1950 { .svid
= 0x1102, .sdid
= 0x8938 }, /* IPC Topnote G notebook */
1951 { .svid
= PCI_ANY_ID
, .sdid
= PCI_ANY_ID
}
1954 unsigned short vid
; /* vendor ID */
1955 unsigned short did
; /* device ID */
1956 unsigned char rev
; /* revision */
1957 } es1371_ac97_reset_hack
[] = {
1958 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_CT5880
, .rev
= CT5880REV_CT5880_C
},
1959 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_CT5880
, .rev
= CT5880REV_CT5880_D
},
1960 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_CT5880
, .rev
= CT5880REV_CT5880_E
},
1961 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_ES1371
, .rev
= ES1371REV_CT5880_A
},
1962 { .vid
= PCI_VENDOR_ID_ENSONIQ
, .did
= PCI_DEVICE_ID_ENSONIQ_ES1371
, .rev
= ES1371REV_ES1373_8
},
1963 { .vid
= PCI_ANY_ID
, .did
= PCI_ANY_ID
}
1967 static void snd_ensoniq_chip_init(struct ensoniq
*ensoniq
)
1971 struct pci_dev
*pci
= ensoniq
->pci
;
1973 /* this code was part of snd_ensoniq_create before intruduction
1977 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1978 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
1979 outl(ES_MEM_PAGEO(ES_PAGE_ADC
), ES_REG(ensoniq
, MEM_PAGE
));
1980 outl(ensoniq
->dma_bug
.addr
, ES_REG(ensoniq
, PHANTOM_FRAME
));
1981 outl(0, ES_REG(ensoniq
, PHANTOM_COUNT
));
1983 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
1984 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
1985 outl(0, ES_REG(ensoniq
, 1371_LEGACY
));
1986 for (idx
= 0; es1371_ac97_reset_hack
[idx
].vid
!= (unsigned short)PCI_ANY_ID
; idx
++)
1987 if (pci
->vendor
== es1371_ac97_reset_hack
[idx
].vid
&&
1988 pci
->device
== es1371_ac97_reset_hack
[idx
].did
&&
1989 ensoniq
->rev
== es1371_ac97_reset_hack
[idx
].rev
) {
1990 outl(ensoniq
->cssr
, ES_REG(ensoniq
, STATUS
));
1991 /* need to delay around 20ms(bleech) to give
1992 some CODECs enough time to wakeup */
1996 /* AC'97 warm reset to start the bitclk */
1997 outl(ensoniq
->ctrl
| ES_1371_SYNC_RES
, ES_REG(ensoniq
, CONTROL
));
1998 inl(ES_REG(ensoniq
, CONTROL
));
2000 outl(ensoniq
->ctrl
, ES_REG(ensoniq
, CONTROL
));
2001 /* Init the sample rate converter */
2002 snd_es1371_wait_src_ready(ensoniq
);
2003 outl(ES_1371_SRC_DISABLE
, ES_REG(ensoniq
, 1371_SMPRATE
));
2004 for (idx
= 0; idx
< 0x80; idx
++)
2005 snd_es1371_src_write(ensoniq
, idx
, 0);
2006 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC1
+ ES_SMPREG_TRUNC_N
, 16 << 4);
2007 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC1
+ ES_SMPREG_INT_REGS
, 16 << 10);
2008 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC2
+ ES_SMPREG_TRUNC_N
, 16 << 4);
2009 snd_es1371_src_write(ensoniq
, ES_SMPREG_DAC2
+ ES_SMPREG_INT_REGS
, 16 << 10);
2010 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_ADC
, 1 << 12);
2011 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_ADC
+ 1, 1 << 12);
2012 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_DAC1
, 1 << 12);
2013 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_DAC1
+ 1, 1 << 12);
2014 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_DAC2
, 1 << 12);
2015 snd_es1371_src_write(ensoniq
, ES_SMPREG_VOL_DAC2
+ 1, 1 << 12);
2016 snd_es1371_adc_rate(ensoniq
, 22050);
2017 snd_es1371_dac1_rate(ensoniq
, 22050);
2018 snd_es1371_dac2_rate(ensoniq
, 22050);
2020 * enabling the sample rate converter without properly programming
2021 * its parameters causes the chip to lock up (the SRC busy bit will
2022 * be stuck high, and I've found no way to rectify this other than
2023 * power cycle) - Thomas Sailer
2025 snd_es1371_wait_src_ready(ensoniq
);
2026 outl(0, ES_REG(ensoniq
, 1371_SMPRATE
));
2027 /* try reset codec directly */
2028 outl(ES_1371_CODEC_WRITE(0, 0), ES_REG(ensoniq
, 1371_CODEC
));
2030 outb(ensoniq
->uartc
= 0x00, ES_REG(ensoniq
, UART_CONTROL
));
2031 outb(0x00, ES_REG(ensoniq
, UART_RES
));
2032 outl(ensoniq
->cssr
, ES_REG(ensoniq
, STATUS
));
2033 synchronize_irq(ensoniq
->irq
);
2037 static int snd_ensoniq_suspend(struct pci_dev
*pci
, pm_message_t state
)
2039 struct snd_card
*card
= pci_get_drvdata(pci
);
2040 struct ensoniq
*ensoniq
= card
->private_data
;
2042 snd_power_change_state(card
, SNDRV_CTL_POWER_D3hot
);
2044 snd_pcm_suspend_all(ensoniq
->pcm1
);
2045 snd_pcm_suspend_all(ensoniq
->pcm2
);
2048 snd_ac97_suspend(ensoniq
->u
.es1371
.ac97
);
2050 snd_ak4531_suspend(ensoniq
->u
.es1370
.ak4531
);
2052 pci_set_power_state(pci
, PCI_D3hot
);
2053 pci_disable_device(pci
);
2054 pci_save_state(pci
);
2058 static int snd_ensoniq_resume(struct pci_dev
*pci
)
2060 struct snd_card
*card
= pci_get_drvdata(pci
);
2061 struct ensoniq
*ensoniq
= card
->private_data
;
2063 pci_restore_state(pci
);
2064 pci_enable_device(pci
);
2065 pci_set_power_state(pci
, PCI_D0
);
2066 pci_set_master(pci
);
2068 snd_ensoniq_chip_init(ensoniq
);
2071 snd_ac97_resume(ensoniq
->u
.es1371
.ac97
);
2073 snd_ak4531_resume(ensoniq
->u
.es1370
.ak4531
);
2075 snd_power_change_state(card
, SNDRV_CTL_POWER_D0
);
2078 #endif /* CONFIG_PM */
2081 static int __devinit
snd_ensoniq_create(struct snd_card
*card
,
2082 struct pci_dev
*pci
,
2083 struct ensoniq
** rensoniq
)
2085 struct ensoniq
*ensoniq
;
2086 unsigned short cmdw
;
2092 static struct snd_device_ops ops
= {
2093 .dev_free
= snd_ensoniq_dev_free
,
2097 if ((err
= pci_enable_device(pci
)) < 0)
2099 ensoniq
= kzalloc(sizeof(*ensoniq
), GFP_KERNEL
);
2100 if (ensoniq
== NULL
) {
2101 pci_disable_device(pci
);
2104 spin_lock_init(&ensoniq
->reg_lock
);
2105 init_MUTEX(&ensoniq
->src_mutex
);
2106 ensoniq
->card
= card
;
2109 if ((err
= pci_request_regions(pci
, "Ensoniq AudioPCI")) < 0) {
2111 pci_disable_device(pci
);
2114 ensoniq
->port
= pci_resource_start(pci
, 0);
2115 if (request_irq(pci
->irq
, snd_audiopci_interrupt
, SA_INTERRUPT
|SA_SHIRQ
,
2116 "Ensoniq AudioPCI", ensoniq
)) {
2117 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
2118 snd_ensoniq_free(ensoniq
);
2121 ensoniq
->irq
= pci
->irq
;
2123 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV
, snd_dma_pci_data(pci
),
2124 16, &ensoniq
->dma_bug
) < 0) {
2125 snd_printk(KERN_ERR
"unable to allocate space for phantom area - dma_bug\n");
2126 snd_ensoniq_free(ensoniq
);
2130 pci_set_master(pci
);
2131 pci_read_config_byte(pci
, PCI_REVISION_ID
, &cmdb
);
2132 ensoniq
->rev
= cmdb
;
2133 pci_read_config_word(pci
, PCI_SUBSYSTEM_VENDOR_ID
, &cmdw
);
2134 ensoniq
->subsystem_vendor_id
= cmdw
;
2135 pci_read_config_word(pci
, PCI_SUBSYSTEM_ID
, &cmdw
);
2136 ensoniq
->subsystem_device_id
= cmdw
;
2139 ensoniq
->ctrl
= ES_1370_CDC_EN
| ES_1370_SERR_DISABLE
|
2140 ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2141 #else /* get microphone working */
2142 ensoniq
->ctrl
= ES_1370_CDC_EN
| ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000));
2149 for (idx
= 0; es1371_amplifier_hack
[idx
].svid
!= (unsigned short)PCI_ANY_ID
; idx
++)
2150 if (ensoniq
->subsystem_vendor_id
== es1371_amplifier_hack
[idx
].svid
&&
2151 ensoniq
->subsystem_device_id
== es1371_amplifier_hack
[idx
].sdid
) {
2152 ensoniq
->ctrl
|= ES_1371_GPIO_OUT(1); /* turn amplifier on */
2155 for (idx
= 0; es1371_ac97_reset_hack
[idx
].vid
!= (unsigned short)PCI_ANY_ID
; idx
++)
2156 if (pci
->vendor
== es1371_ac97_reset_hack
[idx
].vid
&&
2157 pci
->device
== es1371_ac97_reset_hack
[idx
].did
&&
2158 ensoniq
->rev
== es1371_ac97_reset_hack
[idx
].rev
) {
2159 ensoniq
->cssr
|= ES_1371_ST_AC97_RST
;
2164 snd_ensoniq_chip_init(ensoniq
);
2166 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, ensoniq
, &ops
)) < 0) {
2167 snd_ensoniq_free(ensoniq
);
2171 snd_ensoniq_proc_init(ensoniq
);
2173 snd_card_set_dev(card
, &pci
->dev
);
2175 *rensoniq
= ensoniq
;
2183 static void snd_ensoniq_midi_interrupt(struct ensoniq
* ensoniq
)
2185 struct snd_rawmidi
*rmidi
= ensoniq
->rmidi
;
2186 unsigned char status
, mask
, byte
;
2190 /* do Rx at first */
2191 spin_lock(&ensoniq
->reg_lock
);
2192 mask
= ensoniq
->uartm
& ES_MODE_INPUT
? ES_RXRDY
: 0;
2194 status
= inb(ES_REG(ensoniq
, UART_STATUS
));
2195 if ((status
& mask
) == 0)
2197 byte
= inb(ES_REG(ensoniq
, UART_DATA
));
2198 snd_rawmidi_receive(ensoniq
->midi_input
, &byte
, 1);
2200 spin_unlock(&ensoniq
->reg_lock
);
2202 /* do Tx at second */
2203 spin_lock(&ensoniq
->reg_lock
);
2204 mask
= ensoniq
->uartm
& ES_MODE_OUTPUT
? ES_TXRDY
: 0;
2206 status
= inb(ES_REG(ensoniq
, UART_STATUS
));
2207 if ((status
& mask
) == 0)
2209 if (snd_rawmidi_transmit(ensoniq
->midi_output
, &byte
, 1) != 1) {
2210 ensoniq
->uartc
&= ~ES_TXINTENM
;
2211 outb(ensoniq
->uartc
, ES_REG(ensoniq
, UART_CONTROL
));
2214 outb(byte
, ES_REG(ensoniq
, UART_DATA
));
2217 spin_unlock(&ensoniq
->reg_lock
);
2220 static int snd_ensoniq_midi_input_open(struct snd_rawmidi_substream
*substream
)
2222 struct ensoniq
*ensoniq
= substream
->rmidi
->private_data
;
2224 spin_lock_irq(&ensoniq
->reg_lock
);
2225 ensoniq
->uartm
|= ES_MODE_INPUT
;
2226 ensoniq
->midi_input
= substream
;
2227 if (!(ensoniq
->uartm
& ES_MODE_OUTPUT
)) {
2228 outb(ES_CNTRL(3), ES_REG(ensoniq
, UART_CONTROL
));
2229 outb(ensoniq
->uartc
= 0, ES_REG(ensoniq
, UART_CONTROL
));
2230 outl(ensoniq
->ctrl
|= ES_UART_EN
, ES_REG(ensoniq
, CONTROL
));
2232 spin_unlock_irq(&ensoniq
->reg_lock
);
2236 static int snd_ensoniq_midi_input_close(struct snd_rawmidi_substream
*substream
)
2238 struct ensoniq
*ensoniq
= substream
->rmidi
->private_data
;
2240 spin_lock_irq(&ensoniq
->reg_lock
);
2241 if (!(ensoniq
->uartm
& ES_MODE_OUTPUT
)) {
2242 outb(ensoniq
->uartc
= 0, ES_REG(ensoniq
, UART_CONTROL
));
2243 outl(ensoniq
->ctrl
&= ~ES_UART_EN
, ES_REG(ensoniq
, CONTROL
));
2245 outb(ensoniq
->uartc
&= ~ES_RXINTEN
, ES_REG(ensoniq
, UART_CONTROL
));
2247 ensoniq
->midi_input
= NULL
;
2248 ensoniq
->uartm
&= ~ES_MODE_INPUT
;
2249 spin_unlock_irq(&ensoniq
->reg_lock
);
2253 static int snd_ensoniq_midi_output_open(struct snd_rawmidi_substream
*substream
)
2255 struct ensoniq
*ensoniq
= substream
->rmidi
->private_data
;
2257 spin_lock_irq(&ensoniq
->reg_lock
);
2258 ensoniq
->uartm
|= ES_MODE_OUTPUT
;
2259 ensoniq
->midi_output
= substream
;
2260 if (!(ensoniq
->uartm
& ES_MODE_INPUT
)) {
2261 outb(ES_CNTRL(3), ES_REG(ensoniq
, UART_CONTROL
));
2262 outb(ensoniq
->uartc
= 0, ES_REG(ensoniq
, UART_CONTROL
));
2263 outl(ensoniq
->ctrl
|= ES_UART_EN
, ES_REG(ensoniq
, CONTROL
));
2265 spin_unlock_irq(&ensoniq
->reg_lock
);
2269 static int snd_ensoniq_midi_output_close(struct snd_rawmidi_substream
*substream
)
2271 struct ensoniq
*ensoniq
= substream
->rmidi
->private_data
;
2273 spin_lock_irq(&ensoniq
->reg_lock
);
2274 if (!(ensoniq
->uartm
& ES_MODE_INPUT
)) {
2275 outb(ensoniq
->uartc
= 0, ES_REG(ensoniq
, UART_CONTROL
));
2276 outl(ensoniq
->ctrl
&= ~ES_UART_EN
, ES_REG(ensoniq
, CONTROL
));
2278 outb(ensoniq
->uartc
&= ~ES_TXINTENM
, ES_REG(ensoniq
, UART_CONTROL
));
2280 ensoniq
->midi_output
= NULL
;
2281 ensoniq
->uartm
&= ~ES_MODE_OUTPUT
;
2282 spin_unlock_irq(&ensoniq
->reg_lock
);
2286 static void snd_ensoniq_midi_input_trigger(struct snd_rawmidi_substream
*substream
, int up
)
2288 unsigned long flags
;
2289 struct ensoniq
*ensoniq
= substream
->rmidi
->private_data
;
2292 spin_lock_irqsave(&ensoniq
->reg_lock
, flags
);
2294 if ((ensoniq
->uartc
& ES_RXINTEN
) == 0) {
2295 /* empty input FIFO */
2296 for (idx
= 0; idx
< 32; idx
++)
2297 inb(ES_REG(ensoniq
, UART_DATA
));
2298 ensoniq
->uartc
|= ES_RXINTEN
;
2299 outb(ensoniq
->uartc
, ES_REG(ensoniq
, UART_CONTROL
));
2302 if (ensoniq
->uartc
& ES_RXINTEN
) {
2303 ensoniq
->uartc
&= ~ES_RXINTEN
;
2304 outb(ensoniq
->uartc
, ES_REG(ensoniq
, UART_CONTROL
));
2307 spin_unlock_irqrestore(&ensoniq
->reg_lock
, flags
);
2310 static void snd_ensoniq_midi_output_trigger(struct snd_rawmidi_substream
*substream
, int up
)
2312 unsigned long flags
;
2313 struct ensoniq
*ensoniq
= substream
->rmidi
->private_data
;
2316 spin_lock_irqsave(&ensoniq
->reg_lock
, flags
);
2318 if (ES_TXINTENI(ensoniq
->uartc
) == 0) {
2319 ensoniq
->uartc
|= ES_TXINTENO(1);
2320 /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2321 while (ES_TXINTENI(ensoniq
->uartc
) == 1 &&
2322 (inb(ES_REG(ensoniq
, UART_STATUS
)) & ES_TXRDY
)) {
2323 if (snd_rawmidi_transmit(substream
, &byte
, 1) != 1) {
2324 ensoniq
->uartc
&= ~ES_TXINTENM
;
2326 outb(byte
, ES_REG(ensoniq
, UART_DATA
));
2329 outb(ensoniq
->uartc
, ES_REG(ensoniq
, UART_CONTROL
));
2332 if (ES_TXINTENI(ensoniq
->uartc
) == 1) {
2333 ensoniq
->uartc
&= ~ES_TXINTENM
;
2334 outb(ensoniq
->uartc
, ES_REG(ensoniq
, UART_CONTROL
));
2337 spin_unlock_irqrestore(&ensoniq
->reg_lock
, flags
);
2340 static struct snd_rawmidi_ops snd_ensoniq_midi_output
=
2342 .open
= snd_ensoniq_midi_output_open
,
2343 .close
= snd_ensoniq_midi_output_close
,
2344 .trigger
= snd_ensoniq_midi_output_trigger
,
2347 static struct snd_rawmidi_ops snd_ensoniq_midi_input
=
2349 .open
= snd_ensoniq_midi_input_open
,
2350 .close
= snd_ensoniq_midi_input_close
,
2351 .trigger
= snd_ensoniq_midi_input_trigger
,
2354 static int __devinit
snd_ensoniq_midi(struct ensoniq
* ensoniq
, int device
,
2355 struct snd_rawmidi
**rrawmidi
)
2357 struct snd_rawmidi
*rmidi
;
2362 if ((err
= snd_rawmidi_new(ensoniq
->card
, "ES1370/1", device
, 1, 1, &rmidi
)) < 0)
2365 strcpy(rmidi
->name
, "ES1370");
2367 strcpy(rmidi
->name
, "ES1371");
2369 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_OUTPUT
, &snd_ensoniq_midi_output
);
2370 snd_rawmidi_set_ops(rmidi
, SNDRV_RAWMIDI_STREAM_INPUT
, &snd_ensoniq_midi_input
);
2371 rmidi
->info_flags
|= SNDRV_RAWMIDI_INFO_OUTPUT
| SNDRV_RAWMIDI_INFO_INPUT
|
2372 SNDRV_RAWMIDI_INFO_DUPLEX
;
2373 rmidi
->private_data
= ensoniq
;
2374 ensoniq
->rmidi
= rmidi
;
2384 static irqreturn_t
snd_audiopci_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
2386 struct ensoniq
*ensoniq
= dev_id
;
2387 unsigned int status
, sctrl
;
2389 if (ensoniq
== NULL
)
2392 status
= inl(ES_REG(ensoniq
, STATUS
));
2393 if (!(status
& ES_INTR
))
2396 spin_lock(&ensoniq
->reg_lock
);
2397 sctrl
= ensoniq
->sctrl
;
2398 if (status
& ES_DAC1
)
2399 sctrl
&= ~ES_P1_INT_EN
;
2400 if (status
& ES_DAC2
)
2401 sctrl
&= ~ES_P2_INT_EN
;
2402 if (status
& ES_ADC
)
2403 sctrl
&= ~ES_R1_INT_EN
;
2404 outl(sctrl
, ES_REG(ensoniq
, SERIAL
));
2405 outl(ensoniq
->sctrl
, ES_REG(ensoniq
, SERIAL
));
2406 spin_unlock(&ensoniq
->reg_lock
);
2408 if (status
& ES_UART
)
2409 snd_ensoniq_midi_interrupt(ensoniq
);
2410 if ((status
& ES_DAC2
) && ensoniq
->playback2_substream
)
2411 snd_pcm_period_elapsed(ensoniq
->playback2_substream
);
2412 if ((status
& ES_ADC
) && ensoniq
->capture_substream
)
2413 snd_pcm_period_elapsed(ensoniq
->capture_substream
);
2414 if ((status
& ES_DAC1
) && ensoniq
->playback1_substream
)
2415 snd_pcm_period_elapsed(ensoniq
->playback1_substream
);
2419 static int __devinit
snd_audiopci_probe(struct pci_dev
*pci
,
2420 const struct pci_device_id
*pci_id
)
2423 struct snd_card
*card
;
2424 struct ensoniq
*ensoniq
;
2425 int err
, pcm_devs
[2];
2427 if (dev
>= SNDRV_CARDS
)
2434 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
2438 if ((err
= snd_ensoniq_create(card
, pci
, &ensoniq
)) < 0) {
2439 snd_card_free(card
);
2442 card
->private_data
= ensoniq
;
2444 pcm_devs
[0] = 0; pcm_devs
[1] = 1;
2446 if ((err
= snd_ensoniq_1370_mixer(ensoniq
)) < 0) {
2447 snd_card_free(card
);
2452 if ((err
= snd_ensoniq_1371_mixer(ensoniq
)) < 0) {
2453 snd_card_free(card
);
2457 if ((err
= snd_ensoniq_pcm(ensoniq
, 0, NULL
)) < 0) {
2458 snd_card_free(card
);
2461 if ((err
= snd_ensoniq_pcm2(ensoniq
, 1, NULL
)) < 0) {
2462 snd_card_free(card
);
2465 if ((err
= snd_ensoniq_midi(ensoniq
, 0, NULL
)) < 0) {
2466 snd_card_free(card
);
2470 snd_ensoniq_create_gameport(ensoniq
, dev
);
2472 strcpy(card
->driver
, DRIVER_NAME
);
2474 strcpy(card
->shortname
, "Ensoniq AudioPCI");
2475 sprintf(card
->longname
, "%s %s at 0x%lx, irq %i",
2481 if ((err
= snd_card_register(card
)) < 0) {
2482 snd_card_free(card
);
2486 pci_set_drvdata(pci
, card
);
2491 static void __devexit
snd_audiopci_remove(struct pci_dev
*pci
)
2493 snd_card_free(pci_get_drvdata(pci
));
2494 pci_set_drvdata(pci
, NULL
);
2497 static struct pci_driver driver
= {
2498 .name
= DRIVER_NAME
,
2499 .id_table
= snd_audiopci_ids
,
2500 .probe
= snd_audiopci_probe
,
2501 .remove
= __devexit_p(snd_audiopci_remove
),
2503 .suspend
= snd_ensoniq_suspend
,
2504 .resume
= snd_ensoniq_resume
,
2508 static int __init
alsa_card_ens137x_init(void)
2510 return pci_register_driver(&driver
);
2513 static void __exit
alsa_card_ens137x_exit(void)
2515 pci_unregister_driver(&driver
);
2518 module_init(alsa_card_ens137x_init
)
2519 module_exit(alsa_card_ens137x_exit
)