2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
10 #include <linux/interrupt.h>
11 #include <linux/seq_file.h>
12 #include <linux/debugfs.h>
13 #include <linux/pfn.h>
14 #include <linux/percpu.h>
15 #include <linux/gfp.h>
18 #include <asm/processor.h>
19 #include <asm/tlbflush.h>
20 #include <asm/sections.h>
21 #include <asm/setup.h>
22 #include <asm/uaccess.h>
23 #include <asm/pgalloc.h>
24 #include <asm/proto.h>
28 * The current flushing context - we pass it instead of 5 arguments:
37 unsigned force_split
: 1;
43 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
44 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
45 * entries change the page attribute in parallel to some other cpu
46 * splitting a large page entry along with changing the attribute.
48 static DEFINE_SPINLOCK(cpa_lock
);
50 #define CPA_FLUSHTLB 1
52 #define CPA_PAGES_ARRAY 4
55 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
57 void update_page_count(int level
, unsigned long pages
)
59 /* Protect against CPA */
61 direct_pages_count
[level
] += pages
;
62 spin_unlock(&pgd_lock
);
65 static void split_page_count(int level
)
67 direct_pages_count
[level
]--;
68 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
71 void arch_report_meminfo(struct seq_file
*m
)
73 seq_printf(m
, "DirectMap4k: %8lu kB\n",
74 direct_pages_count
[PG_LEVEL_4K
] << 2);
75 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
76 seq_printf(m
, "DirectMap2M: %8lu kB\n",
77 direct_pages_count
[PG_LEVEL_2M
] << 11);
79 seq_printf(m
, "DirectMap4M: %8lu kB\n",
80 direct_pages_count
[PG_LEVEL_2M
] << 12);
84 seq_printf(m
, "DirectMap1G: %8lu kB\n",
85 direct_pages_count
[PG_LEVEL_1G
] << 20);
89 static inline void split_page_count(int level
) { }
94 static inline unsigned long highmap_start_pfn(void)
96 return __pa(_text
) >> PAGE_SHIFT
;
99 static inline unsigned long highmap_end_pfn(void)
101 return __pa(roundup(_brk_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
106 #ifdef CONFIG_DEBUG_PAGEALLOC
107 # define debug_pagealloc 1
109 # define debug_pagealloc 0
113 within(unsigned long addr
, unsigned long start
, unsigned long end
)
115 return addr
>= start
&& addr
< end
;
123 * clflush_cache_range - flush a cache range with clflush
124 * @addr: virtual start address
125 * @size: number of bytes to flush
127 * clflush is an unordered instruction which needs fencing with mfence
128 * to avoid ordering issues.
130 void clflush_cache_range(void *vaddr
, unsigned int size
)
132 void *vend
= vaddr
+ size
- 1;
136 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
139 * Flush any possible final partial cacheline:
145 EXPORT_SYMBOL_GPL(clflush_cache_range
);
147 static void __cpa_flush_all(void *arg
)
149 unsigned long cache
= (unsigned long)arg
;
152 * Flush all to work around Errata in early athlons regarding
153 * large page flushing.
157 if (cache
&& boot_cpu_data
.x86
>= 4)
161 static void cpa_flush_all(unsigned long cache
)
163 BUG_ON(irqs_disabled());
165 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
168 static void __cpa_flush_range(void *arg
)
171 * We could optimize that further and do individual per page
172 * tlb invalidates for a low number of pages. Caveat: we must
173 * flush the high aliases on 64bit as well.
178 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
180 unsigned int i
, level
;
183 BUG_ON(irqs_disabled());
184 WARN_ON(PAGE_ALIGN(start
) != start
);
186 on_each_cpu(__cpa_flush_range
, NULL
, 1);
192 * We only need to flush on one CPU,
193 * clflush is a MESI-coherent instruction that
194 * will cause all other CPUs to flush the same
197 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
198 pte_t
*pte
= lookup_address(addr
, &level
);
201 * Only flush present addresses:
203 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
204 clflush_cache_range((void *) addr
, PAGE_SIZE
);
208 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
,
209 int in_flags
, struct page
**pages
)
211 unsigned int i
, level
;
212 unsigned long do_wbinvd
= cache
&& numpages
>= 1024; /* 4M threshold */
214 BUG_ON(irqs_disabled());
216 on_each_cpu(__cpa_flush_all
, (void *) do_wbinvd
, 1);
218 if (!cache
|| do_wbinvd
)
222 * We only need to flush on one CPU,
223 * clflush is a MESI-coherent instruction that
224 * will cause all other CPUs to flush the same
227 for (i
= 0; i
< numpages
; i
++) {
231 if (in_flags
& CPA_PAGES_ARRAY
)
232 addr
= (unsigned long)page_address(pages
[i
]);
236 pte
= lookup_address(addr
, &level
);
239 * Only flush present addresses:
241 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
242 clflush_cache_range((void *)addr
, PAGE_SIZE
);
247 * Certain areas of memory on x86 require very specific protection flags,
248 * for example the BIOS area or kernel text. Callers don't always get this
249 * right (again, ioremap() on BIOS memory is not uncommon) so this function
250 * checks and fixes these known static required protection bits.
252 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
255 pgprot_t forbidden
= __pgprot(0);
258 * The BIOS area between 640k and 1Mb needs to be executable for
259 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
261 if (within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
262 pgprot_val(forbidden
) |= _PAGE_NX
;
265 * The kernel text needs to be executable for obvious reasons
266 * Does not cover __inittext since that is gone later on. On
267 * 64bit we do not enforce !NX on the low mapping
269 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
270 pgprot_val(forbidden
) |= _PAGE_NX
;
273 * The .rodata section needs to be read-only. Using the pfn
274 * catches all aliases.
276 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
277 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
278 pgprot_val(forbidden
) |= _PAGE_RW
;
280 #if defined(CONFIG_X86_64) && defined(CONFIG_DEBUG_RODATA)
282 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
283 * kernel text mappings for the large page aligned text, rodata sections
284 * will be always read-only. For the kernel identity mappings covering
285 * the holes caused by this alignment can be anything that user asks.
287 * This will preserve the large page mappings for kernel text/data
290 if (kernel_set_to_readonly
&&
291 within(address
, (unsigned long)_text
,
292 (unsigned long)__end_rodata_hpage_align
)) {
296 * Don't enforce the !RW mapping for the kernel text mapping,
297 * if the current mapping is already using small page mapping.
298 * No need to work hard to preserve large page mappings in this
301 * This also fixes the Linux Xen paravirt guest boot failure
302 * (because of unexpected read-only mappings for kernel identity
303 * mappings). In this paravirt guest case, the kernel text
304 * mapping and the kernel identity mapping share the same
305 * page-table pages. Thus we can't really use different
306 * protections for the kernel text and identity mappings. Also,
307 * these shared mappings are made of small page mappings.
308 * Thus this don't enforce !RW mapping for small page kernel
309 * text mapping logic will help Linux Xen parvirt guest boot
312 if (lookup_address(address
, &level
) && (level
!= PG_LEVEL_4K
))
313 pgprot_val(forbidden
) |= _PAGE_RW
;
317 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
323 * Lookup the page table entry for a virtual address. Return a pointer
324 * to the entry and the level of the mapping.
326 * Note: We return pud and pmd either when the entry is marked large
327 * or when the present bit is not set. Otherwise we would return a
328 * pointer to a nonexisting mapping.
330 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
332 pgd_t
*pgd
= pgd_offset_k(address
);
336 *level
= PG_LEVEL_NONE
;
341 pud
= pud_offset(pgd
, address
);
345 *level
= PG_LEVEL_1G
;
346 if (pud_large(*pud
) || !pud_present(*pud
))
349 pmd
= pmd_offset(pud
, address
);
353 *level
= PG_LEVEL_2M
;
354 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
357 *level
= PG_LEVEL_4K
;
359 return pte_offset_kernel(pmd
, address
);
361 EXPORT_SYMBOL_GPL(lookup_address
);
364 * Set the new pmd in all the pgds we know about:
366 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
369 set_pte_atomic(kpte
, pte
);
371 if (!SHARED_KERNEL_PMD
) {
374 list_for_each_entry(page
, &pgd_list
, lru
) {
379 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
380 pud
= pud_offset(pgd
, address
);
381 pmd
= pmd_offset(pud
, address
);
382 set_pte_atomic((pte_t
*)pmd
, pte
);
389 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
390 struct cpa_data
*cpa
)
392 unsigned long nextpage_addr
, numpages
, pmask
, psize
, addr
, pfn
;
393 pte_t new_pte
, old_pte
, *tmp
;
394 pgprot_t old_prot
, new_prot
;
398 if (cpa
->force_split
)
401 spin_lock(&pgd_lock
);
403 * Check for races, another CPU might have split this page
406 tmp
= lookup_address(address
, &level
);
412 psize
= PMD_PAGE_SIZE
;
413 pmask
= PMD_PAGE_MASK
;
417 psize
= PUD_PAGE_SIZE
;
418 pmask
= PUD_PAGE_MASK
;
427 * Calculate the number of pages, which fit into this large
428 * page starting at address:
430 nextpage_addr
= (address
+ psize
) & pmask
;
431 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
432 if (numpages
< cpa
->numpages
)
433 cpa
->numpages
= numpages
;
436 * We are safe now. Check whether the new pgprot is the same:
439 old_prot
= new_prot
= pte_pgprot(old_pte
);
441 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
442 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
445 * old_pte points to the large page base address. So we need
446 * to add the offset of the virtual address:
448 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
451 new_prot
= static_protections(new_prot
, address
, pfn
);
454 * We need to check the full range, whether
455 * static_protection() requires a different pgprot for one of
456 * the pages in the range we try to preserve:
458 addr
= address
+ PAGE_SIZE
;
460 for (i
= 1; i
< cpa
->numpages
; i
++, addr
+= PAGE_SIZE
, pfn
++) {
461 pgprot_t chk_prot
= static_protections(new_prot
, addr
, pfn
);
463 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
468 * If there are no changes, return. maxpages has been updated
471 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
477 * We need to change the attributes. Check, whether we can
478 * change the large page in one go. We request a split, when
479 * the address is not aligned and the number of pages is
480 * smaller than the number of pages in the large page. Note
481 * that we limited the number of possible pages already to
482 * the number of pages in the large page.
484 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
486 * The address is aligned and the number of pages
487 * covers the full page.
489 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
490 __set_pmd_pte(kpte
, address
, new_pte
);
491 cpa
->flags
|= CPA_FLUSHTLB
;
496 spin_unlock(&pgd_lock
);
501 static int split_large_page(pte_t
*kpte
, unsigned long address
)
503 unsigned long pfn
, pfninc
= 1;
504 unsigned int i
, level
;
509 if (!debug_pagealloc
)
510 spin_unlock(&cpa_lock
);
511 base
= alloc_pages(GFP_KERNEL
| __GFP_NOTRACK
, 0);
512 if (!debug_pagealloc
)
513 spin_lock(&cpa_lock
);
517 spin_lock(&pgd_lock
);
519 * Check for races, another CPU might have split this page
522 tmp
= lookup_address(address
, &level
);
526 pbase
= (pte_t
*)page_address(base
);
527 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
528 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
530 * If we ever want to utilize the PAT bit, we need to
531 * update this function to make sure it's converted from
532 * bit 12 to bit 7 when we cross from the 2MB level to
535 WARN_ON_ONCE(pgprot_val(ref_prot
) & _PAGE_PAT_LARGE
);
538 if (level
== PG_LEVEL_1G
) {
539 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
540 pgprot_val(ref_prot
) |= _PAGE_PSE
;
545 * Get the target pfn from the original entry:
547 pfn
= pte_pfn(*kpte
);
548 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
549 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
551 if (address
>= (unsigned long)__va(0) &&
552 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
553 split_page_count(level
);
556 if (address
>= (unsigned long)__va(1UL<<32) &&
557 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
558 split_page_count(level
);
562 * Install the new, split up pagetable.
564 * We use the standard kernel pagetable protections for the new
565 * pagetable protections, the actual ptes set above control the
566 * primary protection behavior:
568 __set_pmd_pte(kpte
, address
, mk_pte(base
, __pgprot(_KERNPG_TABLE
)));
571 * Intel Atom errata AAH41 workaround.
573 * The real fix should be in hw or in a microcode update, but
574 * we also probabilistically try to reduce the window of having
575 * a large TLB mixed with 4K TLBs while instruction fetches are
584 * If we dropped out via the lookup_address check under
585 * pgd_lock then stick the page back into the pool:
589 spin_unlock(&pgd_lock
);
594 static int __cpa_process_fault(struct cpa_data
*cpa
, unsigned long vaddr
,
598 * Ignore all non primary paths.
604 * Ignore the NULL PTE for kernel identity mapping, as it is expected
606 * Also set numpages to '1' indicating that we processed cpa req for
607 * one virtual address page and its pfn. TBD: numpages can be set based
608 * on the initial value and the level returned by lookup_address().
610 if (within(vaddr
, PAGE_OFFSET
,
611 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))) {
613 cpa
->pfn
= __pa(vaddr
) >> PAGE_SHIFT
;
616 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
617 "vaddr = %lx cpa->vaddr = %lx\n", vaddr
,
624 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
626 unsigned long address
;
629 pte_t
*kpte
, old_pte
;
631 if (cpa
->flags
& CPA_PAGES_ARRAY
) {
632 struct page
*page
= cpa
->pages
[cpa
->curpage
];
633 if (unlikely(PageHighMem(page
)))
635 address
= (unsigned long)page_address(page
);
636 } else if (cpa
->flags
& CPA_ARRAY
)
637 address
= cpa
->vaddr
[cpa
->curpage
];
639 address
= *cpa
->vaddr
;
641 kpte
= lookup_address(address
, &level
);
643 return __cpa_process_fault(cpa
, address
, primary
);
646 if (!pte_val(old_pte
))
647 return __cpa_process_fault(cpa
, address
, primary
);
649 if (level
== PG_LEVEL_4K
) {
651 pgprot_t new_prot
= pte_pgprot(old_pte
);
652 unsigned long pfn
= pte_pfn(old_pte
);
654 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
655 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
657 new_prot
= static_protections(new_prot
, address
, pfn
);
660 * We need to keep the pfn from the existing PTE,
661 * after all we're only going to change it's attributes
662 * not the memory it points to
664 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
667 * Do we really change anything ?
669 if (pte_val(old_pte
) != pte_val(new_pte
)) {
670 set_pte_atomic(kpte
, new_pte
);
671 cpa
->flags
|= CPA_FLUSHTLB
;
678 * Check, whether we can keep the large page intact
679 * and just change the pte:
681 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
683 * When the range fits into the existing large page,
684 * return. cp->numpages and cpa->tlbflush have been updated in
691 * We have to split the large page:
693 err
= split_large_page(kpte
, address
);
696 * Do a global flush tlb after splitting the large page
697 * and before we do the actual change page attribute in the PTE.
699 * With out this, we violate the TLB application note, that says
700 * "The TLBs may contain both ordinary and large-page
701 * translations for a 4-KByte range of linear addresses. This
702 * may occur if software modifies the paging structures so that
703 * the page size used for the address range changes. If the two
704 * translations differ with respect to page frame or attributes
705 * (e.g., permissions), processor behavior is undefined and may
706 * be implementation-specific."
708 * We do this global tlb flush inside the cpa_lock, so that we
709 * don't allow any other cpu, with stale tlb entries change the
710 * page attribute in parallel, that also falls into the
711 * just split large page entry.
720 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
722 static int cpa_process_alias(struct cpa_data
*cpa
)
724 struct cpa_data alias_cpa
;
725 unsigned long laddr
= (unsigned long)__va(cpa
->pfn
<< PAGE_SHIFT
);
729 if (cpa
->pfn
>= max_pfn_mapped
)
733 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
737 * No need to redo, when the primary call touched the direct
740 if (cpa
->flags
& CPA_PAGES_ARRAY
) {
741 struct page
*page
= cpa
->pages
[cpa
->curpage
];
742 if (unlikely(PageHighMem(page
)))
744 vaddr
= (unsigned long)page_address(page
);
745 } else if (cpa
->flags
& CPA_ARRAY
)
746 vaddr
= cpa
->vaddr
[cpa
->curpage
];
750 if (!(within(vaddr
, PAGE_OFFSET
,
751 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
)))) {
754 alias_cpa
.vaddr
= &laddr
;
755 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
757 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
764 * If the primary call didn't touch the high mapping already
765 * and the physical address is inside the kernel map, we need
766 * to touch the high mapped kernel as well:
768 if (!within(vaddr
, (unsigned long)_text
, _brk_end
) &&
769 within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn())) {
770 unsigned long temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) +
771 __START_KERNEL_map
- phys_base
;
773 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
774 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
777 * The high mapping range is imprecise, so ignore the
780 __change_page_attr_set_clr(&alias_cpa
, 0);
787 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
789 int ret
, numpages
= cpa
->numpages
;
793 * Store the remaining nr of pages for the large page
794 * preservation check.
796 cpa
->numpages
= numpages
;
797 /* for array changes, we can't use large page */
798 if (cpa
->flags
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
801 if (!debug_pagealloc
)
802 spin_lock(&cpa_lock
);
803 ret
= __change_page_attr(cpa
, checkalias
);
804 if (!debug_pagealloc
)
805 spin_unlock(&cpa_lock
);
810 ret
= cpa_process_alias(cpa
);
816 * Adjust the number of pages with the result of the
817 * CPA operation. Either a large page has been
818 * preserved or a single page update happened.
820 BUG_ON(cpa
->numpages
> numpages
);
821 numpages
-= cpa
->numpages
;
822 if (cpa
->flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
))
825 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
831 static inline int cache_attr(pgprot_t attr
)
833 return pgprot_val(attr
) &
834 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
837 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
838 pgprot_t mask_set
, pgprot_t mask_clr
,
839 int force_split
, int in_flag
,
843 int ret
, cache
, checkalias
;
844 unsigned long baddr
= 0;
847 * Check, if we are requested to change a not supported
850 mask_set
= canon_pgprot(mask_set
);
851 mask_clr
= canon_pgprot(mask_clr
);
852 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
855 /* Ensure we are PAGE_SIZE aligned */
856 if (in_flag
& CPA_ARRAY
) {
858 for (i
= 0; i
< numpages
; i
++) {
859 if (addr
[i
] & ~PAGE_MASK
) {
860 addr
[i
] &= PAGE_MASK
;
864 } else if (!(in_flag
& CPA_PAGES_ARRAY
)) {
866 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
867 * No need to cehck in that case
869 if (*addr
& ~PAGE_MASK
) {
872 * People should not be passing in unaligned addresses:
877 * Save address for cache flush. *addr is modified in the call
878 * to __change_page_attr_set_clr() below.
883 /* Must avoid aliasing mappings in the highmem code */
890 cpa
.numpages
= numpages
;
891 cpa
.mask_set
= mask_set
;
892 cpa
.mask_clr
= mask_clr
;
895 cpa
.force_split
= force_split
;
897 if (in_flag
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
898 cpa
.flags
|= in_flag
;
900 /* No alias checking for _NX bit modifications */
901 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
903 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
906 * Check whether we really changed something:
908 if (!(cpa
.flags
& CPA_FLUSHTLB
))
912 * No need to flush, when we did not set any of the caching
915 cache
= cache_attr(mask_set
);
918 * On success we use clflush, when the CPU supports it to
919 * avoid the wbindv. If the CPU does not support it and in the
920 * error case we fall back to cpa_flush_all (which uses
923 if (!ret
&& cpu_has_clflush
) {
924 if (cpa
.flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
)) {
925 cpa_flush_array(addr
, numpages
, cache
,
928 cpa_flush_range(baddr
, numpages
, cache
);
930 cpa_flush_all(cache
);
936 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
937 pgprot_t mask
, int array
)
939 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
940 (array
? CPA_ARRAY
: 0), NULL
);
943 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
944 pgprot_t mask
, int array
)
946 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
947 (array
? CPA_ARRAY
: 0), NULL
);
950 static inline int cpa_set_pages_array(struct page
**pages
, int numpages
,
953 return change_page_attr_set_clr(NULL
, numpages
, mask
, __pgprot(0), 0,
954 CPA_PAGES_ARRAY
, pages
);
957 static inline int cpa_clear_pages_array(struct page
**pages
, int numpages
,
960 return change_page_attr_set_clr(NULL
, numpages
, __pgprot(0), mask
, 0,
961 CPA_PAGES_ARRAY
, pages
);
964 int _set_memory_uc(unsigned long addr
, int numpages
)
967 * for now UC MINUS. see comments in ioremap_nocache()
969 return change_page_attr_set(&addr
, numpages
,
970 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
973 int set_memory_uc(unsigned long addr
, int numpages
)
978 * for now UC MINUS. see comments in ioremap_nocache()
980 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
981 _PAGE_CACHE_UC_MINUS
, NULL
);
985 ret
= _set_memory_uc(addr
, numpages
);
992 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
996 EXPORT_SYMBOL(set_memory_uc
);
998 int _set_memory_array(unsigned long *addr
, int addrinarray
,
999 unsigned long new_type
)
1005 * for now UC MINUS. see comments in ioremap_nocache()
1007 for (i
= 0; i
< addrinarray
; i
++) {
1008 ret
= reserve_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
,
1014 ret
= change_page_attr_set(addr
, addrinarray
,
1015 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
1017 if (!ret
&& new_type
== _PAGE_CACHE_WC
)
1018 ret
= change_page_attr_set_clr(addr
, addrinarray
,
1019 __pgprot(_PAGE_CACHE_WC
),
1020 __pgprot(_PAGE_CACHE_MASK
),
1021 0, CPA_ARRAY
, NULL
);
1028 for (j
= 0; j
< i
; j
++)
1029 free_memtype(__pa(addr
[j
]), __pa(addr
[j
]) + PAGE_SIZE
);
1034 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
1036 return _set_memory_array(addr
, addrinarray
, _PAGE_CACHE_UC_MINUS
);
1038 EXPORT_SYMBOL(set_memory_array_uc
);
1040 int set_memory_array_wc(unsigned long *addr
, int addrinarray
)
1042 return _set_memory_array(addr
, addrinarray
, _PAGE_CACHE_WC
);
1044 EXPORT_SYMBOL(set_memory_array_wc
);
1046 int _set_memory_wc(unsigned long addr
, int numpages
)
1049 unsigned long addr_copy
= addr
;
1051 ret
= change_page_attr_set(&addr
, numpages
,
1052 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
1054 ret
= change_page_attr_set_clr(&addr_copy
, numpages
,
1055 __pgprot(_PAGE_CACHE_WC
),
1056 __pgprot(_PAGE_CACHE_MASK
),
1062 int set_memory_wc(unsigned long addr
, int numpages
)
1067 return set_memory_uc(addr
, numpages
);
1069 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
1070 _PAGE_CACHE_WC
, NULL
);
1074 ret
= _set_memory_wc(addr
, numpages
);
1081 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1085 EXPORT_SYMBOL(set_memory_wc
);
1087 int _set_memory_wb(unsigned long addr
, int numpages
)
1089 return change_page_attr_clear(&addr
, numpages
,
1090 __pgprot(_PAGE_CACHE_MASK
), 0);
1093 int set_memory_wb(unsigned long addr
, int numpages
)
1097 ret
= _set_memory_wb(addr
, numpages
);
1101 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1104 EXPORT_SYMBOL(set_memory_wb
);
1106 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
1111 ret
= change_page_attr_clear(addr
, addrinarray
,
1112 __pgprot(_PAGE_CACHE_MASK
), 1);
1116 for (i
= 0; i
< addrinarray
; i
++)
1117 free_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
);
1121 EXPORT_SYMBOL(set_memory_array_wb
);
1123 int set_memory_x(unsigned long addr
, int numpages
)
1125 if (!(__supported_pte_mask
& _PAGE_NX
))
1128 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1130 EXPORT_SYMBOL(set_memory_x
);
1132 int set_memory_nx(unsigned long addr
, int numpages
)
1134 if (!(__supported_pte_mask
& _PAGE_NX
))
1137 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1139 EXPORT_SYMBOL(set_memory_nx
);
1141 int set_memory_ro(unsigned long addr
, int numpages
)
1143 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1145 EXPORT_SYMBOL_GPL(set_memory_ro
);
1147 int set_memory_rw(unsigned long addr
, int numpages
)
1149 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1151 EXPORT_SYMBOL_GPL(set_memory_rw
);
1153 int set_memory_np(unsigned long addr
, int numpages
)
1155 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
1158 int set_memory_4k(unsigned long addr
, int numpages
)
1160 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1161 __pgprot(0), 1, 0, NULL
);
1164 int set_pages_uc(struct page
*page
, int numpages
)
1166 unsigned long addr
= (unsigned long)page_address(page
);
1168 return set_memory_uc(addr
, numpages
);
1170 EXPORT_SYMBOL(set_pages_uc
);
1172 static int _set_pages_array(struct page
**pages
, int addrinarray
,
1173 unsigned long new_type
)
1175 unsigned long start
;
1181 for (i
= 0; i
< addrinarray
; i
++) {
1182 if (PageHighMem(pages
[i
]))
1184 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1185 end
= start
+ PAGE_SIZE
;
1186 if (reserve_memtype(start
, end
, new_type
, NULL
))
1190 ret
= cpa_set_pages_array(pages
, addrinarray
,
1191 __pgprot(_PAGE_CACHE_UC_MINUS
));
1192 if (!ret
&& new_type
== _PAGE_CACHE_WC
)
1193 ret
= change_page_attr_set_clr(NULL
, addrinarray
,
1194 __pgprot(_PAGE_CACHE_WC
),
1195 __pgprot(_PAGE_CACHE_MASK
),
1196 0, CPA_PAGES_ARRAY
, pages
);
1199 return 0; /* Success */
1202 for (i
= 0; i
< free_idx
; i
++) {
1203 if (PageHighMem(pages
[i
]))
1205 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1206 end
= start
+ PAGE_SIZE
;
1207 free_memtype(start
, end
);
1212 int set_pages_array_uc(struct page
**pages
, int addrinarray
)
1214 return _set_pages_array(pages
, addrinarray
, _PAGE_CACHE_UC_MINUS
);
1216 EXPORT_SYMBOL(set_pages_array_uc
);
1218 int set_pages_array_wc(struct page
**pages
, int addrinarray
)
1220 return _set_pages_array(pages
, addrinarray
, _PAGE_CACHE_WC
);
1222 EXPORT_SYMBOL(set_pages_array_wc
);
1224 int set_pages_wb(struct page
*page
, int numpages
)
1226 unsigned long addr
= (unsigned long)page_address(page
);
1228 return set_memory_wb(addr
, numpages
);
1230 EXPORT_SYMBOL(set_pages_wb
);
1232 int set_pages_array_wb(struct page
**pages
, int addrinarray
)
1235 unsigned long start
;
1239 retval
= cpa_clear_pages_array(pages
, addrinarray
,
1240 __pgprot(_PAGE_CACHE_MASK
));
1244 for (i
= 0; i
< addrinarray
; i
++) {
1245 if (PageHighMem(pages
[i
]))
1247 start
= page_to_pfn(pages
[i
]) << PAGE_SHIFT
;
1248 end
= start
+ PAGE_SIZE
;
1249 free_memtype(start
, end
);
1254 EXPORT_SYMBOL(set_pages_array_wb
);
1256 int set_pages_x(struct page
*page
, int numpages
)
1258 unsigned long addr
= (unsigned long)page_address(page
);
1260 return set_memory_x(addr
, numpages
);
1262 EXPORT_SYMBOL(set_pages_x
);
1264 int set_pages_nx(struct page
*page
, int numpages
)
1266 unsigned long addr
= (unsigned long)page_address(page
);
1268 return set_memory_nx(addr
, numpages
);
1270 EXPORT_SYMBOL(set_pages_nx
);
1272 int set_pages_ro(struct page
*page
, int numpages
)
1274 unsigned long addr
= (unsigned long)page_address(page
);
1276 return set_memory_ro(addr
, numpages
);
1279 int set_pages_rw(struct page
*page
, int numpages
)
1281 unsigned long addr
= (unsigned long)page_address(page
);
1283 return set_memory_rw(addr
, numpages
);
1286 #ifdef CONFIG_DEBUG_PAGEALLOC
1288 static int __set_pages_p(struct page
*page
, int numpages
)
1290 unsigned long tempaddr
= (unsigned long) page_address(page
);
1291 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1292 .numpages
= numpages
,
1293 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1294 .mask_clr
= __pgprot(0),
1298 * No alias checking needed for setting present flag. otherwise,
1299 * we may need to break large pages for 64-bit kernel text
1300 * mappings (this adds to complexity if we want to do this from
1301 * atomic context especially). Let's keep it simple!
1303 return __change_page_attr_set_clr(&cpa
, 0);
1306 static int __set_pages_np(struct page
*page
, int numpages
)
1308 unsigned long tempaddr
= (unsigned long) page_address(page
);
1309 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1310 .numpages
= numpages
,
1311 .mask_set
= __pgprot(0),
1312 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1316 * No alias checking needed for setting not present flag. otherwise,
1317 * we may need to break large pages for 64-bit kernel text
1318 * mappings (this adds to complexity if we want to do this from
1319 * atomic context especially). Let's keep it simple!
1321 return __change_page_attr_set_clr(&cpa
, 0);
1324 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1326 if (PageHighMem(page
))
1329 debug_check_no_locks_freed(page_address(page
),
1330 numpages
* PAGE_SIZE
);
1334 * If page allocator is not up yet then do not call c_p_a():
1336 if (!debug_pagealloc_enabled
)
1340 * The return value is ignored as the calls cannot fail.
1341 * Large pages for identity mappings are not used at boot time
1342 * and hence no memory allocations during large page split.
1345 __set_pages_p(page
, numpages
);
1347 __set_pages_np(page
, numpages
);
1350 * We should perform an IPI and flush all tlbs,
1351 * but that can deadlock->flush only current cpu:
1356 #ifdef CONFIG_HIBERNATION
1358 bool kernel_page_present(struct page
*page
)
1363 if (PageHighMem(page
))
1366 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1367 return (pte_val(*pte
) & _PAGE_PRESENT
);
1370 #endif /* CONFIG_HIBERNATION */
1372 #endif /* CONFIG_DEBUG_PAGEALLOC */
1375 * The testcases use internal knowledge of the implementation that shouldn't
1376 * be exposed to the rest of the kernel. Include these directly here.
1378 #ifdef CONFIG_CPA_DEBUG
1379 #include "pageattr-test.c"