2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ohci fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
18 * This file is licenced under the GPL.
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38 #include <linux/workqueue.h>
42 #include <asm/system.h>
43 #include <asm/unaligned.h>
44 #include <asm/byteorder.h>
46 #include "../core/hcd.h"
48 #define DRIVER_VERSION "2006 August 04"
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
52 /*-------------------------------------------------------------------------*/
54 #undef OHCI_VERBOSE_DEBUG /* not always helpful */
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58 #define OHCI_INTR_INIT \
59 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
60 | OHCI_INTR_RD | OHCI_INTR_WDH)
63 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
67 #ifdef CONFIG_ARCH_OMAP
68 /* OMAP doesn't support IR (no SMM; not needed) */
72 /*-------------------------------------------------------------------------*/
74 static const char hcd_name
[] = "ohci_hcd";
76 #define STATECHANGE_DELAY msecs_to_jiffies(300)
80 static void ohci_dump (struct ohci_hcd
*ohci
, int verbose
);
81 static int ohci_init (struct ohci_hcd
*ohci
);
82 static void ohci_stop (struct usb_hcd
*hcd
);
83 static int ohci_restart (struct ohci_hcd
*ohci
);
84 static void ohci_quirk_nec_worker (struct work_struct
*work
);
93 * On architectures with edge-triggered interrupts we must never return
96 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
97 #define IRQ_NOTMINE IRQ_HANDLED
99 #define IRQ_NOTMINE IRQ_NONE
103 /* Some boards misreport power switching/overcurrent */
104 static int distrust_firmware
= 1;
105 module_param (distrust_firmware
, bool, 0);
106 MODULE_PARM_DESC (distrust_firmware
,
107 "true to distrust firmware power/overcurrent setup");
109 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
110 static int no_handshake
= 0;
111 module_param (no_handshake
, bool, 0);
112 MODULE_PARM_DESC (no_handshake
, "true (not default) disables BIOS handshake");
114 /*-------------------------------------------------------------------------*/
117 * queue up an urb for anything except the root hub
119 static int ohci_urb_enqueue (
121 struct usb_host_endpoint
*ep
,
125 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
127 urb_priv_t
*urb_priv
;
128 unsigned int pipe
= urb
->pipe
;
133 #ifdef OHCI_VERBOSE_DEBUG
134 urb_print (urb
, "SUB", usb_pipein (pipe
));
137 /* every endpoint has a ed, locate and maybe (re)initialize it */
138 if (! (ed
= ed_get (ohci
, ep
, urb
->dev
, pipe
, urb
->interval
)))
141 /* for the private part of the URB we need the number of TDs (size) */
144 /* td_submit_urb() doesn't yet handle these */
145 if (urb
->transfer_buffer_length
> 4096)
148 /* 1 TD for setup, 1 for ACK, plus ... */
151 // case PIPE_INTERRUPT:
154 /* one TD for every 4096 Bytes (can be upto 8K) */
155 size
+= urb
->transfer_buffer_length
/ 4096;
156 /* ... and for any remaining bytes ... */
157 if ((urb
->transfer_buffer_length
% 4096) != 0)
159 /* ... and maybe a zero length packet to wrap it up */
162 else if ((urb
->transfer_flags
& URB_ZERO_PACKET
) != 0
163 && (urb
->transfer_buffer_length
164 % usb_maxpacket (urb
->dev
, pipe
,
165 usb_pipeout (pipe
))) == 0)
168 case PIPE_ISOCHRONOUS
: /* number of packets from URB */
169 size
= urb
->number_of_packets
;
173 /* allocate the private part of the URB */
174 urb_priv
= kzalloc (sizeof (urb_priv_t
) + size
* sizeof (struct td
*),
178 INIT_LIST_HEAD (&urb_priv
->pending
);
179 urb_priv
->length
= size
;
182 /* allocate the TDs (deferring hash chain updates) */
183 for (i
= 0; i
< size
; i
++) {
184 urb_priv
->td
[i
] = td_alloc (ohci
, mem_flags
);
185 if (!urb_priv
->td
[i
]) {
186 urb_priv
->length
= i
;
187 urb_free_priv (ohci
, urb_priv
);
192 spin_lock_irqsave (&ohci
->lock
, flags
);
194 /* don't submit to a dead HC */
195 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE
, &hcd
->flags
)) {
199 if (!HC_IS_RUNNING(hcd
->state
)) {
204 /* in case of unlink-during-submit */
205 spin_lock (&urb
->lock
);
206 if (urb
->status
!= -EINPROGRESS
) {
207 spin_unlock (&urb
->lock
);
208 urb
->hcpriv
= urb_priv
;
209 finish_urb (ohci
, urb
);
214 /* schedule the ed if needed */
215 if (ed
->state
== ED_IDLE
) {
216 retval
= ed_schedule (ohci
, ed
);
219 if (ed
->type
== PIPE_ISOCHRONOUS
) {
220 u16 frame
= ohci_frame_no(ohci
);
222 /* delay a few frames before the first TD */
223 frame
+= max_t (u16
, 8, ed
->interval
);
224 frame
&= ~(ed
->interval
- 1);
226 urb
->start_frame
= frame
;
228 /* yes, only URB_ISO_ASAP is supported, and
229 * urb->start_frame is never used as input.
232 } else if (ed
->type
== PIPE_ISOCHRONOUS
)
233 urb
->start_frame
= ed
->last_iso
+ ed
->interval
;
235 /* fill the TDs and link them to the ed; and
236 * enable that part of the schedule, if needed
237 * and update count of queued periodic urbs
239 urb
->hcpriv
= urb_priv
;
240 td_submit_urb (ohci
, urb
);
243 spin_unlock (&urb
->lock
);
246 urb_free_priv (ohci
, urb_priv
);
247 spin_unlock_irqrestore (&ohci
->lock
, flags
);
252 * decouple the URB from the HC queues (TDs, urb_priv); it's
253 * already marked using urb->status. reporting is always done
254 * asynchronously, and we might be dealing with an urb that's
255 * partially transferred, or an ED with other urbs being unlinked.
257 static int ohci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
259 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
262 #ifdef OHCI_VERBOSE_DEBUG
263 urb_print (urb
, "UNLINK", 1);
266 spin_lock_irqsave (&ohci
->lock
, flags
);
267 if (HC_IS_RUNNING(hcd
->state
)) {
268 urb_priv_t
*urb_priv
;
270 /* Unless an IRQ completed the unlink while it was being
271 * handed to us, flag it for unlink and giveback, and force
272 * some upcoming INTR_SF to call finish_unlinks()
274 urb_priv
= urb
->hcpriv
;
276 if (urb_priv
->ed
->state
== ED_OPER
)
277 start_ed_unlink (ohci
, urb_priv
->ed
);
281 * with HC dead, we won't respect hc queue pointers
282 * any more ... just clean up every urb's memory.
285 finish_urb (ohci
, urb
);
287 spin_unlock_irqrestore (&ohci
->lock
, flags
);
291 /*-------------------------------------------------------------------------*/
293 /* frees config/altsetting state for endpoints,
294 * including ED memory, dummy TD, and bulk/intr data toggle
298 ohci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
300 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
302 struct ed
*ed
= ep
->hcpriv
;
303 unsigned limit
= 1000;
305 /* ASSERT: any requests/urbs are being unlinked */
306 /* ASSERT: nobody can be submitting urbs for this any more */
312 spin_lock_irqsave (&ohci
->lock
, flags
);
314 if (!HC_IS_RUNNING (hcd
->state
)) {
317 finish_unlinks (ohci
, 0);
321 case ED_UNLINK
: /* wait for hw to finish? */
322 /* major IRQ delivery trouble loses INTR_SF too... */
324 ohci_warn (ohci
, "IRQ INTR_SF lossage\n");
327 spin_unlock_irqrestore (&ohci
->lock
, flags
);
328 schedule_timeout_uninterruptible(1);
330 case ED_IDLE
: /* fully unlinked */
331 if (list_empty (&ed
->td_list
)) {
332 td_free (ohci
, ed
->dummy
);
336 /* else FALL THROUGH */
338 /* caller was supposed to have unlinked any requests;
339 * that's not our job. can't recover; must leak ed.
341 ohci_err (ohci
, "leak ed %p (#%02x) state %d%s\n",
342 ed
, ep
->desc
.bEndpointAddress
, ed
->state
,
343 list_empty (&ed
->td_list
) ? "" : " (has tds)");
344 td_free (ohci
, ed
->dummy
);
348 spin_unlock_irqrestore (&ohci
->lock
, flags
);
352 static int ohci_get_frame (struct usb_hcd
*hcd
)
354 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
356 return ohci_frame_no(ohci
);
359 static void ohci_usb_reset (struct ohci_hcd
*ohci
)
361 ohci
->hc_control
= ohci_readl (ohci
, &ohci
->regs
->control
);
362 ohci
->hc_control
&= OHCI_CTRL_RWC
;
363 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
366 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
367 * other cases where the next software may expect clean state from the
368 * "firmware". this is bus-neutral, unlike shutdown() methods.
371 ohci_shutdown (struct usb_hcd
*hcd
)
373 struct ohci_hcd
*ohci
;
375 ohci
= hcd_to_ohci (hcd
);
376 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
377 ohci_usb_reset (ohci
);
378 /* flush the writes */
379 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
382 /*-------------------------------------------------------------------------*
384 *-------------------------------------------------------------------------*/
386 /* init memory, and kick BIOS/SMM off */
388 static int ohci_init (struct ohci_hcd
*ohci
)
391 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
394 ohci
->regs
= hcd
->regs
;
396 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
397 * was never needed for most non-PCI systems ... remove the code?
401 /* SMM owns the HC? not for long! */
402 if (!no_handshake
&& ohci_readl (ohci
,
403 &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
406 ohci_dbg (ohci
, "USB HC TakeOver from BIOS/SMM\n");
408 /* this timeout is arbitrary. we make it long, so systems
409 * depending on usb keyboards may be usable even if the
410 * BIOS/SMM code seems pretty broken.
412 temp
= 500; /* arbitrary: five seconds */
414 ohci_writel (ohci
, OHCI_INTR_OC
, &ohci
->regs
->intrenable
);
415 ohci_writel (ohci
, OHCI_OCR
, &ohci
->regs
->cmdstatus
);
416 while (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_IR
) {
419 ohci_err (ohci
, "USB HC takeover failed!"
420 " (BIOS/SMM bug)\n");
424 ohci_usb_reset (ohci
);
428 /* Disable HC interrupts */
429 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
431 /* flush the writes, and save key bits like RWC */
432 if (ohci_readl (ohci
, &ohci
->regs
->control
) & OHCI_CTRL_RWC
)
433 ohci
->hc_control
|= OHCI_CTRL_RWC
;
435 /* Read the number of ports unless overridden */
436 if (ohci
->num_ports
== 0)
437 ohci
->num_ports
= roothub_a(ohci
) & RH_A_NDP
;
442 ohci
->hcca
= dma_alloc_coherent (hcd
->self
.controller
,
443 sizeof *ohci
->hcca
, &ohci
->hcca_dma
, 0);
447 if ((ret
= ohci_mem_init (ohci
)) < 0)
450 create_debug_files (ohci
);
456 /*-------------------------------------------------------------------------*/
458 /* Start an OHCI controller, set the BUS operational
459 * resets USB and controller
462 static int ohci_run (struct ohci_hcd
*ohci
)
465 int first
= ohci
->fminterval
== 0;
466 struct usb_hcd
*hcd
= ohci_to_hcd(ohci
);
470 /* boot firmware should have set this up (5.1.1.3.1) */
473 temp
= ohci_readl (ohci
, &ohci
->regs
->fminterval
);
474 ohci
->fminterval
= temp
& 0x3fff;
475 if (ohci
->fminterval
!= FI
)
476 ohci_dbg (ohci
, "fminterval delta %d\n",
477 ohci
->fminterval
- FI
);
478 ohci
->fminterval
|= FSMP (ohci
->fminterval
) << 16;
479 /* also: power/overcurrent flags in roothub.a */
482 /* Reset USB nearly "by the book". RemoteWakeupConnected was
483 * saved if boot firmware (BIOS/SMM/...) told us it's connected,
484 * or if bus glue did the same (e.g. for PCI add-in cards with
487 if ((ohci
->hc_control
& OHCI_CTRL_RWC
) != 0
488 && !device_may_wakeup(hcd
->self
.controller
))
489 device_init_wakeup(hcd
->self
.controller
, 1);
491 switch (ohci
->hc_control
& OHCI_CTRL_HCFS
) {
495 case OHCI_USB_SUSPEND
:
496 case OHCI_USB_RESUME
:
497 ohci
->hc_control
&= OHCI_CTRL_RWC
;
498 ohci
->hc_control
|= OHCI_USB_RESUME
;
499 temp
= 10 /* msec wait */;
501 // case OHCI_USB_RESET:
503 ohci
->hc_control
&= OHCI_CTRL_RWC
;
504 ohci
->hc_control
|= OHCI_USB_RESET
;
505 temp
= 50 /* msec wait */;
508 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
510 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
513 memset (ohci
->hcca
, 0, sizeof (struct ohci_hcca
));
515 /* 2msec timelimit here means no irqs/preempt */
516 spin_lock_irq (&ohci
->lock
);
519 /* HC Reset requires max 10 us delay */
520 ohci_writel (ohci
, OHCI_HCR
, &ohci
->regs
->cmdstatus
);
521 temp
= 30; /* ... allow extra time */
522 while ((ohci_readl (ohci
, &ohci
->regs
->cmdstatus
) & OHCI_HCR
) != 0) {
524 spin_unlock_irq (&ohci
->lock
);
525 ohci_err (ohci
, "USB HC reset timed out!\n");
531 /* now we're in the SUSPEND state ... must go OPERATIONAL
532 * within 2msec else HC enters RESUME
534 * ... but some hardware won't init fmInterval "by the book"
535 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
536 * this if we write fmInterval after we're OPERATIONAL.
537 * Unclear about ALi, ServerWorks, and others ... this could
538 * easily be a longstanding bug in chip init on Linux.
540 if (ohci
->flags
& OHCI_QUIRK_INITRESET
) {
541 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
542 // flush those writes
543 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
546 /* Tell the controller where the control and bulk lists are
547 * The lists are empty now. */
548 ohci_writel (ohci
, 0, &ohci
->regs
->ed_controlhead
);
549 ohci_writel (ohci
, 0, &ohci
->regs
->ed_bulkhead
);
551 /* a reset clears this */
552 ohci_writel (ohci
, (u32
) ohci
->hcca_dma
, &ohci
->regs
->hcca
);
554 periodic_reinit (ohci
);
556 /* some OHCI implementations are finicky about how they init.
557 * bogus values here mean not even enumeration could work.
559 if ((ohci_readl (ohci
, &ohci
->regs
->fminterval
) & 0x3fff0000) == 0
560 || !ohci_readl (ohci
, &ohci
->regs
->periodicstart
)) {
561 if (!(ohci
->flags
& OHCI_QUIRK_INITRESET
)) {
562 ohci
->flags
|= OHCI_QUIRK_INITRESET
;
563 ohci_dbg (ohci
, "enabling initreset quirk\n");
566 spin_unlock_irq (&ohci
->lock
);
567 ohci_err (ohci
, "init err (%08x %04x)\n",
568 ohci_readl (ohci
, &ohci
->regs
->fminterval
),
569 ohci_readl (ohci
, &ohci
->regs
->periodicstart
));
573 /* use rhsc irqs after khubd is fully initialized */
575 hcd
->uses_new_polling
= 1;
577 /* start controller operations */
578 ohci
->hc_control
&= OHCI_CTRL_RWC
;
579 ohci
->hc_control
|= OHCI_CONTROL_INIT
| OHCI_USB_OPER
;
580 ohci_writel (ohci
, ohci
->hc_control
, &ohci
->regs
->control
);
581 hcd
->state
= HC_STATE_RUNNING
;
583 /* wake on ConnectStatusChange, matching external hubs */
584 ohci_writel (ohci
, RH_HS_DRWE
, &ohci
->regs
->roothub
.status
);
586 /* Choose the interrupts we care about now, others later on demand */
587 mask
= OHCI_INTR_INIT
;
588 ohci_writel (ohci
, ~0, &ohci
->regs
->intrstatus
);
589 ohci_writel (ohci
, mask
, &ohci
->regs
->intrenable
);
591 /* handle root hub init quirks ... */
592 temp
= roothub_a (ohci
);
593 temp
&= ~(RH_A_PSM
| RH_A_OCPM
);
594 if (ohci
->flags
& OHCI_QUIRK_SUPERIO
) {
595 /* NSC 87560 and maybe others */
597 temp
&= ~(RH_A_POTPGT
| RH_A_NPS
);
598 ohci_writel (ohci
, temp
, &ohci
->regs
->roothub
.a
);
599 } else if ((ohci
->flags
& OHCI_QUIRK_AMD756
) || distrust_firmware
) {
600 /* hub power always on; required for AMD-756 and some
601 * Mac platforms. ganged overcurrent reporting, if any.
604 ohci_writel (ohci
, temp
, &ohci
->regs
->roothub
.a
);
606 ohci_writel (ohci
, RH_HS_LPSC
, &ohci
->regs
->roothub
.status
);
607 ohci_writel (ohci
, (temp
& RH_A_NPS
) ? 0 : RH_B_PPCM
,
608 &ohci
->regs
->roothub
.b
);
609 // flush those writes
610 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
612 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
613 spin_unlock_irq (&ohci
->lock
);
615 // POTPGT delay is bits 24-31, in 2 ms units.
616 mdelay ((temp
>> 23) & 0x1fe);
617 hcd
->state
= HC_STATE_RUNNING
;
624 /*-------------------------------------------------------------------------*/
626 /* an interrupt happens */
628 static irqreturn_t
ohci_irq (struct usb_hcd
*hcd
)
630 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
631 struct ohci_regs __iomem
*regs
= ohci
->regs
;
634 /* we can eliminate a (slow) ohci_readl()
635 if _only_ WDH caused this irq */
636 if ((ohci
->hcca
->done_head
!= 0)
637 && ! (hc32_to_cpup (ohci
, &ohci
->hcca
->done_head
)
639 ints
= OHCI_INTR_WDH
;
641 /* cardbus/... hardware gone before remove() */
642 } else if ((ints
= ohci_readl (ohci
, ®s
->intrstatus
)) == ~(u32
)0) {
644 ohci_dbg (ohci
, "device removed!\n");
647 /* interrupt for some other device? */
648 } else if ((ints
&= ohci_readl (ohci
, ®s
->intrenable
)) == 0) {
652 if (ints
& OHCI_INTR_UE
) {
653 // e.g. due to PCI Master/Target Abort
654 if (ohci
->flags
& OHCI_QUIRK_NEC
) {
655 /* Workaround for a silicon bug in some NEC chips used
656 * in Apple's PowerBooks. Adapted from Darwin code.
658 ohci_err (ohci
, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
660 ohci_writel (ohci
, OHCI_INTR_UE
, ®s
->intrdisable
);
662 schedule_work (&ohci
->nec_work
);
665 ohci_err (ohci
, "OHCI Unrecoverable Error, disabled\n");
669 ohci_usb_reset (ohci
);
672 if (ints
& OHCI_INTR_RHSC
) {
673 ohci_vdbg(ohci
, "rhsc\n");
674 ohci
->next_statechange
= jiffies
+ STATECHANGE_DELAY
;
675 ohci_writel(ohci
, OHCI_INTR_RD
| OHCI_INTR_RHSC
,
678 /* NOTE: Vendors didn't always make the same implementation
679 * choices for RHSC. Many followed the spec; RHSC triggers
680 * on an edge, like setting and maybe clearing a port status
681 * change bit. With others it's level-triggered, active
682 * until khubd clears all the port status change bits. We'll
683 * always disable it here and rely on polling until khubd
686 ohci_writel(ohci
, OHCI_INTR_RHSC
, ®s
->intrdisable
);
687 usb_hcd_poll_rh_status(hcd
);
690 /* For connect and disconnect events, we expect the controller
691 * to turn on RHSC along with RD. But for remote wakeup events
692 * this might not happen.
694 else if (ints
& OHCI_INTR_RD
) {
695 ohci_vdbg(ohci
, "resume detect\n");
696 ohci_writel(ohci
, OHCI_INTR_RD
, ®s
->intrstatus
);
698 if (ohci
->autostop
) {
699 spin_lock (&ohci
->lock
);
700 ohci_rh_resume (ohci
);
701 spin_unlock (&ohci
->lock
);
703 usb_hcd_resume_root_hub(hcd
);
706 if (ints
& OHCI_INTR_WDH
) {
707 if (HC_IS_RUNNING(hcd
->state
))
708 ohci_writel (ohci
, OHCI_INTR_WDH
, ®s
->intrdisable
);
709 spin_lock (&ohci
->lock
);
711 spin_unlock (&ohci
->lock
);
712 if (HC_IS_RUNNING(hcd
->state
))
713 ohci_writel (ohci
, OHCI_INTR_WDH
, ®s
->intrenable
);
716 /* could track INTR_SO to reduce available PCI/... bandwidth */
718 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
719 * when there's still unlinking to be done (next frame).
721 spin_lock (&ohci
->lock
);
722 if (ohci
->ed_rm_list
)
723 finish_unlinks (ohci
, ohci_frame_no(ohci
));
724 if ((ints
& OHCI_INTR_SF
) != 0 && !ohci
->ed_rm_list
725 && HC_IS_RUNNING(hcd
->state
))
726 ohci_writel (ohci
, OHCI_INTR_SF
, ®s
->intrdisable
);
727 spin_unlock (&ohci
->lock
);
729 if (HC_IS_RUNNING(hcd
->state
)) {
730 ohci_writel (ohci
, ints
, ®s
->intrstatus
);
731 ohci_writel (ohci
, OHCI_INTR_MIE
, ®s
->intrenable
);
732 // flush those writes
733 (void) ohci_readl (ohci
, &ohci
->regs
->control
);
739 /*-------------------------------------------------------------------------*/
741 static void ohci_stop (struct usb_hcd
*hcd
)
743 struct ohci_hcd
*ohci
= hcd_to_ohci (hcd
);
747 flush_scheduled_work();
749 ohci_usb_reset (ohci
);
750 ohci_writel (ohci
, OHCI_INTR_MIE
, &ohci
->regs
->intrdisable
);
751 free_irq(hcd
->irq
, hcd
);
754 remove_debug_files (ohci
);
755 ohci_mem_cleanup (ohci
);
757 dma_free_coherent (hcd
->self
.controller
,
759 ohci
->hcca
, ohci
->hcca_dma
);
765 /*-------------------------------------------------------------------------*/
767 /* must not be called from interrupt context */
768 static int ohci_restart (struct ohci_hcd
*ohci
)
772 struct urb_priv
*priv
;
774 spin_lock_irq(&ohci
->lock
);
777 /* Recycle any "live" eds/tds (and urbs). */
778 if (!list_empty (&ohci
->pending
))
779 ohci_dbg(ohci
, "abort schedule...\n");
780 list_for_each_entry (priv
, &ohci
->pending
, pending
) {
781 struct urb
*urb
= priv
->td
[0]->urb
;
782 struct ed
*ed
= priv
->ed
;
786 ed
->state
= ED_UNLINK
;
787 ed
->hwINFO
|= cpu_to_hc32(ohci
, ED_DEQUEUE
);
788 ed_deschedule (ohci
, ed
);
790 ed
->ed_next
= ohci
->ed_rm_list
;
792 ohci
->ed_rm_list
= ed
;
797 ohci_dbg(ohci
, "bogus ed %p state %d\n",
801 spin_lock (&urb
->lock
);
802 urb
->status
= -ESHUTDOWN
;
803 spin_unlock (&urb
->lock
);
805 finish_unlinks (ohci
, 0);
806 spin_unlock_irq(&ohci
->lock
);
808 /* paranoia, in case that didn't work: */
810 /* empty the interrupt branches */
811 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->load
[i
] = 0;
812 for (i
= 0; i
< NUM_INTS
; i
++) ohci
->hcca
->int_table
[i
] = 0;
814 /* no EDs to remove */
815 ohci
->ed_rm_list
= NULL
;
817 /* empty control and bulk lists */
818 ohci
->ed_controltail
= NULL
;
819 ohci
->ed_bulktail
= NULL
;
821 if ((temp
= ohci_run (ohci
)) < 0) {
822 ohci_err (ohci
, "can't restart, %d\n", temp
);
825 ohci_dbg(ohci
, "restart complete\n");
829 /*-------------------------------------------------------------------------*/
832 static void ohci_quirk_nec_worker(struct work_struct
*work
)
834 struct ohci_hcd
*ohci
= container_of(work
, struct ohci_hcd
, nec_work
);
837 status
= ohci_init(ohci
);
839 ohci_err(ohci
, "Restarting NEC controller failed "
840 "in ohci_init, %d\n", status
);
844 status
= ohci_restart(ohci
);
846 ohci_err(ohci
, "Restarting NEC controller failed "
847 "in ohci_restart, %d\n", status
);
850 /*-------------------------------------------------------------------------*/
852 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
854 MODULE_AUTHOR (DRIVER_AUTHOR
);
855 MODULE_DESCRIPTION (DRIVER_INFO
);
856 MODULE_LICENSE ("GPL");
859 #include "ohci-pci.c"
860 #define PCI_DRIVER ohci_pci_driver
864 #include "ohci-sa1111.c"
865 #define SA1111_DRIVER ohci_hcd_sa1111_driver
868 #ifdef CONFIG_ARCH_S3C2410
869 #include "ohci-s3c2410.c"
870 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver
873 #ifdef CONFIG_ARCH_OMAP
874 #include "ohci-omap.c"
875 #define PLATFORM_DRIVER ohci_hcd_omap_driver
878 #ifdef CONFIG_ARCH_LH7A404
879 #include "ohci-lh7a404.c"
880 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver
884 #include "ohci-pxa27x.c"
885 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver
888 #ifdef CONFIG_ARCH_EP93XX
889 #include "ohci-ep93xx.c"
890 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver
893 #ifdef CONFIG_SOC_AU1X00
894 #include "ohci-au1xxx.c"
895 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver
898 #ifdef CONFIG_PNX8550
899 #include "ohci-pnx8550.c"
900 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver
903 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC
904 #include "ohci-ppc-soc.c"
905 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver
908 #ifdef CONFIG_ARCH_AT91
909 #include "ohci-at91.c"
910 #define PLATFORM_DRIVER ohci_hcd_at91_driver
913 #ifdef CONFIG_ARCH_PNX4008
914 #include "ohci-pnx4008.c"
915 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver
919 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
920 #include "ohci-ppc-of.c"
921 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
924 #ifdef CONFIG_PPC_PS3
925 #include "ohci-ps3.c"
926 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
929 #if !defined(PCI_DRIVER) && \
930 !defined(PLATFORM_DRIVER) && \
931 !defined(OF_PLATFORM_DRIVER) && \
932 !defined(SA1111_DRIVER) && \
933 !defined(PS3_SYSTEM_BUS_DRIVER)
934 #error "missing bus glue for ohci-hcd"
937 static int __init
ohci_hcd_mod_init(void)
944 printk (KERN_DEBUG
"%s: " DRIVER_INFO
"\n", hcd_name
);
945 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name
,
946 sizeof (struct ed
), sizeof (struct td
));
948 #ifdef PS3_SYSTEM_BUS_DRIVER
949 retval
= ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
954 #ifdef PLATFORM_DRIVER
955 retval
= platform_driver_register(&PLATFORM_DRIVER
);
960 #ifdef OF_PLATFORM_DRIVER
961 retval
= of_register_platform_driver(&OF_PLATFORM_DRIVER
);
963 goto error_of_platform
;
967 retval
= sa1111_driver_register(&SA1111_DRIVER
);
973 retval
= pci_register_driver(&PCI_DRIVER
);
985 sa1111_driver_unregister(&SA1111_DRIVER
);
988 #ifdef OF_PLATFORM_DRIVER
989 of_unregister_platform_driver(&OF_PLATFORM_DRIVER
);
992 #ifdef PLATFORM_DRIVER
993 platform_driver_unregister(&PLATFORM_DRIVER
);
996 #ifdef PS3_SYSTEM_BUS_DRIVER
997 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1002 module_init(ohci_hcd_mod_init
);
1004 static void __exit
ohci_hcd_mod_exit(void)
1007 pci_unregister_driver(&PCI_DRIVER
);
1009 #ifdef SA1111_DRIVER
1010 sa1111_driver_unregister(&SA1111_DRIVER
);
1012 #ifdef OF_PLATFORM_DRIVER
1013 of_unregister_platform_driver(&OF_PLATFORM_DRIVER
);
1015 #ifdef PLATFORM_DRIVER
1016 platform_driver_unregister(&PLATFORM_DRIVER
);
1018 #ifdef PS3_SYSTEM_BUS_DRIVER
1019 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1022 module_exit(ohci_hcd_mod_exit
);