2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
16 #include <asm/processor.h>
17 #include <asm/tlbflush.h>
18 #include <asm/sections.h>
19 #include <asm/uaccess.h>
20 #include <asm/pgalloc.h>
21 #include <asm/proto.h>
25 * The current flushing context - we pass it instead of 5 arguments:
34 unsigned force_split
: 1;
39 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
40 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
41 * entries change the page attribute in parallel to some other cpu
42 * splitting a large page entry along with changing the attribute.
44 static DEFINE_SPINLOCK(cpa_lock
);
46 #define CPA_FLUSHTLB 1
50 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
52 void update_page_count(int level
, unsigned long pages
)
56 /* Protect against CPA */
57 spin_lock_irqsave(&pgd_lock
, flags
);
58 direct_pages_count
[level
] += pages
;
59 spin_unlock_irqrestore(&pgd_lock
, flags
);
62 static void split_page_count(int level
)
64 direct_pages_count
[level
]--;
65 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
68 void arch_report_meminfo(struct seq_file
*m
)
70 seq_printf(m
, "DirectMap4k: %8lu kB\n",
71 direct_pages_count
[PG_LEVEL_4K
] << 2);
72 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
73 seq_printf(m
, "DirectMap2M: %8lu kB\n",
74 direct_pages_count
[PG_LEVEL_2M
] << 11);
76 seq_printf(m
, "DirectMap4M: %8lu kB\n",
77 direct_pages_count
[PG_LEVEL_2M
] << 12);
81 seq_printf(m
, "DirectMap1G: %8lu kB\n",
82 direct_pages_count
[PG_LEVEL_1G
] << 20);
86 static inline void split_page_count(int level
) { }
91 static inline unsigned long highmap_start_pfn(void)
93 return __pa(_text
) >> PAGE_SHIFT
;
96 static inline unsigned long highmap_end_pfn(void)
98 return __pa(roundup((unsigned long)_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
103 #ifdef CONFIG_DEBUG_PAGEALLOC
104 # define debug_pagealloc 1
106 # define debug_pagealloc 0
110 within(unsigned long addr
, unsigned long start
, unsigned long end
)
112 return addr
>= start
&& addr
< end
;
120 * clflush_cache_range - flush a cache range with clflush
121 * @addr: virtual start address
122 * @size: number of bytes to flush
124 * clflush is an unordered instruction which needs fencing with mfence
125 * to avoid ordering issues.
127 void clflush_cache_range(void *vaddr
, unsigned int size
)
129 void *vend
= vaddr
+ size
- 1;
133 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
136 * Flush any possible final partial cacheline:
143 static void __cpa_flush_all(void *arg
)
145 unsigned long cache
= (unsigned long)arg
;
148 * Flush all to work around Errata in early athlons regarding
149 * large page flushing.
153 if (cache
&& boot_cpu_data
.x86_model
>= 4)
157 static void cpa_flush_all(unsigned long cache
)
159 BUG_ON(irqs_disabled());
161 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
164 static void __cpa_flush_range(void *arg
)
167 * We could optimize that further and do individual per page
168 * tlb invalidates for a low number of pages. Caveat: we must
169 * flush the high aliases on 64bit as well.
174 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
176 unsigned int i
, level
;
179 BUG_ON(irqs_disabled());
180 WARN_ON(PAGE_ALIGN(start
) != start
);
182 on_each_cpu(__cpa_flush_range
, NULL
, 1);
188 * We only need to flush on one CPU,
189 * clflush is a MESI-coherent instruction that
190 * will cause all other CPUs to flush the same
193 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
194 pte_t
*pte
= lookup_address(addr
, &level
);
197 * Only flush present addresses:
199 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
200 clflush_cache_range((void *) addr
, PAGE_SIZE
);
204 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
)
206 unsigned int i
, level
;
209 BUG_ON(irqs_disabled());
211 on_each_cpu(__cpa_flush_range
, NULL
, 1);
217 if (numpages
>= 1024) {
218 if (boot_cpu_data
.x86_model
>= 4)
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
228 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
++) {
229 pte_t
*pte
= lookup_address(*addr
, &level
);
232 * Only flush present addresses:
234 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
235 clflush_cache_range((void *) *addr
, PAGE_SIZE
);
240 * Certain areas of memory on x86 require very specific protection flags,
241 * for example the BIOS area or kernel text. Callers don't always get this
242 * right (again, ioremap() on BIOS memory is not uncommon) so this function
243 * checks and fixes these known static required protection bits.
245 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
248 pgprot_t forbidden
= __pgprot(0);
251 * The BIOS area between 640k and 1Mb needs to be executable for
252 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
254 if (within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
255 pgprot_val(forbidden
) |= _PAGE_NX
;
258 * The kernel text needs to be executable for obvious reasons
259 * Does not cover __inittext since that is gone later on. On
260 * 64bit we do not enforce !NX on the low mapping
262 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
263 pgprot_val(forbidden
) |= _PAGE_NX
;
266 * The .rodata section needs to be read-only. Using the pfn
267 * catches all aliases.
269 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
270 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
271 pgprot_val(forbidden
) |= _PAGE_RW
;
273 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
279 * Lookup the page table entry for a virtual address. Return a pointer
280 * to the entry and the level of the mapping.
282 * Note: We return pud and pmd either when the entry is marked large
283 * or when the present bit is not set. Otherwise we would return a
284 * pointer to a nonexisting mapping.
286 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
288 pgd_t
*pgd
= pgd_offset_k(address
);
292 *level
= PG_LEVEL_NONE
;
297 pud
= pud_offset(pgd
, address
);
301 *level
= PG_LEVEL_1G
;
302 if (pud_large(*pud
) || !pud_present(*pud
))
305 pmd
= pmd_offset(pud
, address
);
309 *level
= PG_LEVEL_2M
;
310 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
313 *level
= PG_LEVEL_4K
;
315 return pte_offset_kernel(pmd
, address
);
317 EXPORT_SYMBOL_GPL(lookup_address
);
320 * Set the new pmd in all the pgds we know about:
322 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
325 set_pte_atomic(kpte
, pte
);
327 if (!SHARED_KERNEL_PMD
) {
330 list_for_each_entry(page
, &pgd_list
, lru
) {
335 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
336 pud
= pud_offset(pgd
, address
);
337 pmd
= pmd_offset(pud
, address
);
338 set_pte_atomic((pte_t
*)pmd
, pte
);
345 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
346 struct cpa_data
*cpa
)
348 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
, addr
, pfn
;
349 pte_t new_pte
, old_pte
, *tmp
;
350 pgprot_t old_prot
, new_prot
;
354 if (cpa
->force_split
)
357 spin_lock_irqsave(&pgd_lock
, flags
);
359 * Check for races, another CPU might have split this page
362 tmp
= lookup_address(address
, &level
);
368 psize
= PMD_PAGE_SIZE
;
369 pmask
= PMD_PAGE_MASK
;
373 psize
= PUD_PAGE_SIZE
;
374 pmask
= PUD_PAGE_MASK
;
383 * Calculate the number of pages, which fit into this large
384 * page starting at address:
386 nextpage_addr
= (address
+ psize
) & pmask
;
387 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
388 if (numpages
< cpa
->numpages
)
389 cpa
->numpages
= numpages
;
392 * We are safe now. Check whether the new pgprot is the same:
395 old_prot
= new_prot
= pte_pgprot(old_pte
);
397 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
398 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
401 * old_pte points to the large page base address. So we need
402 * to add the offset of the virtual address:
404 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
407 new_prot
= static_protections(new_prot
, address
, pfn
);
410 * We need to check the full range, whether
411 * static_protection() requires a different pgprot for one of
412 * the pages in the range we try to preserve:
414 addr
= address
+ PAGE_SIZE
;
416 for (i
= 1; i
< cpa
->numpages
; i
++, addr
+= PAGE_SIZE
, pfn
++) {
417 pgprot_t chk_prot
= static_protections(new_prot
, addr
, pfn
);
419 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
424 * If there are no changes, return. maxpages has been updated
427 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
433 * We need to change the attributes. Check, whether we can
434 * change the large page in one go. We request a split, when
435 * the address is not aligned and the number of pages is
436 * smaller than the number of pages in the large page. Note
437 * that we limited the number of possible pages already to
438 * the number of pages in the large page.
440 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
442 * The address is aligned and the number of pages
443 * covers the full page.
445 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
446 __set_pmd_pte(kpte
, address
, new_pte
);
447 cpa
->flags
|= CPA_FLUSHTLB
;
452 spin_unlock_irqrestore(&pgd_lock
, flags
);
457 static int split_large_page(pte_t
*kpte
, unsigned long address
)
459 unsigned long flags
, pfn
, pfninc
= 1;
460 unsigned int i
, level
;
465 if (!debug_pagealloc
)
466 spin_unlock(&cpa_lock
);
467 base
= alloc_pages(GFP_KERNEL
, 0);
468 if (!debug_pagealloc
)
469 spin_lock(&cpa_lock
);
473 spin_lock_irqsave(&pgd_lock
, flags
);
475 * Check for races, another CPU might have split this page
478 tmp
= lookup_address(address
, &level
);
482 pbase
= (pte_t
*)page_address(base
);
483 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
484 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
487 if (level
== PG_LEVEL_1G
) {
488 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
489 pgprot_val(ref_prot
) |= _PAGE_PSE
;
494 * Get the target pfn from the original entry:
496 pfn
= pte_pfn(*kpte
);
497 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
498 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
500 if (address
>= (unsigned long)__va(0) &&
501 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
502 split_page_count(level
);
505 if (address
>= (unsigned long)__va(1UL<<32) &&
506 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
507 split_page_count(level
);
511 * Install the new, split up pagetable. Important details here:
513 * On Intel the NX bit of all levels must be cleared to make a
514 * page executable. See section 4.13.2 of Intel 64 and IA-32
515 * Architectures Software Developer's Manual).
517 * Mark the entry present. The current mapping might be
518 * set to not present, which we preserved above.
520 ref_prot
= pte_pgprot(pte_mkexec(pte_clrhuge(*kpte
)));
521 pgprot_val(ref_prot
) |= _PAGE_PRESENT
;
522 __set_pmd_pte(kpte
, address
, mk_pte(base
, ref_prot
));
527 * If we dropped out via the lookup_address check under
528 * pgd_lock then stick the page back into the pool:
532 spin_unlock_irqrestore(&pgd_lock
, flags
);
537 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
539 unsigned long address
;
542 pte_t
*kpte
, old_pte
;
544 if (cpa
->flags
& CPA_ARRAY
)
545 address
= cpa
->vaddr
[cpa
->curpage
];
547 address
= *cpa
->vaddr
;
550 kpte
= lookup_address(address
, &level
);
555 if (!pte_val(old_pte
)) {
558 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
559 "vaddr = %lx cpa->vaddr = %lx\n", address
,
564 if (level
== PG_LEVEL_4K
) {
566 pgprot_t new_prot
= pte_pgprot(old_pte
);
567 unsigned long pfn
= pte_pfn(old_pte
);
569 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
570 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
572 new_prot
= static_protections(new_prot
, address
, pfn
);
575 * We need to keep the pfn from the existing PTE,
576 * after all we're only going to change it's attributes
577 * not the memory it points to
579 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
582 * Do we really change anything ?
584 if (pte_val(old_pte
) != pte_val(new_pte
)) {
585 set_pte_atomic(kpte
, new_pte
);
586 cpa
->flags
|= CPA_FLUSHTLB
;
593 * Check, whether we can keep the large page intact
594 * and just change the pte:
596 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
598 * When the range fits into the existing large page,
599 * return. cp->numpages and cpa->tlbflush have been updated in
606 * We have to split the large page:
608 err
= split_large_page(kpte
, address
);
611 * Do a global flush tlb after splitting the large page
612 * and before we do the actual change page attribute in the PTE.
614 * With out this, we violate the TLB application note, that says
615 * "The TLBs may contain both ordinary and large-page
616 * translations for a 4-KByte range of linear addresses. This
617 * may occur if software modifies the paging structures so that
618 * the page size used for the address range changes. If the two
619 * translations differ with respect to page frame or attributes
620 * (e.g., permissions), processor behavior is undefined and may
621 * be implementation-specific."
623 * We do this global tlb flush inside the cpa_lock, so that we
624 * don't allow any other cpu, with stale tlb entries change the
625 * page attribute in parallel, that also falls into the
626 * just split large page entry.
635 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
637 static int cpa_process_alias(struct cpa_data
*cpa
)
639 struct cpa_data alias_cpa
;
641 unsigned long temp_cpa_vaddr
, vaddr
;
643 if (cpa
->pfn
>= max_pfn_mapped
)
647 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
651 * No need to redo, when the primary call touched the direct
654 if (cpa
->flags
& CPA_ARRAY
)
655 vaddr
= cpa
->vaddr
[cpa
->curpage
];
659 if (!(within(vaddr
, PAGE_OFFSET
,
660 PAGE_OFFSET
+ (max_low_pfn_mapped
<< PAGE_SHIFT
))
662 || within(vaddr
, PAGE_OFFSET
+ (1UL<<32),
663 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))
668 temp_cpa_vaddr
= (unsigned long) __va(cpa
->pfn
<< PAGE_SHIFT
);
669 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
670 alias_cpa
.flags
&= ~CPA_ARRAY
;
673 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
680 * No need to redo, when the primary call touched the high
683 if (within(vaddr
, (unsigned long) _text
, (unsigned long) _end
))
687 * If the physical address is inside the kernel map, we need
688 * to touch the high mapped kernel as well:
690 if (!within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn()))
694 temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) + __START_KERNEL_map
- phys_base
;
695 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
696 alias_cpa
.flags
&= ~CPA_ARRAY
;
699 * The high mapping range is imprecise, so ignore the return value.
701 __change_page_attr_set_clr(&alias_cpa
, 0);
706 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
708 int ret
, numpages
= cpa
->numpages
;
712 * Store the remaining nr of pages for the large page
713 * preservation check.
715 cpa
->numpages
= numpages
;
716 /* for array changes, we can't use large page */
717 if (cpa
->flags
& CPA_ARRAY
)
720 if (!debug_pagealloc
)
721 spin_lock(&cpa_lock
);
722 ret
= __change_page_attr(cpa
, checkalias
);
723 if (!debug_pagealloc
)
724 spin_unlock(&cpa_lock
);
729 ret
= cpa_process_alias(cpa
);
735 * Adjust the number of pages with the result of the
736 * CPA operation. Either a large page has been
737 * preserved or a single page update happened.
739 BUG_ON(cpa
->numpages
> numpages
);
740 numpages
-= cpa
->numpages
;
741 if (cpa
->flags
& CPA_ARRAY
)
744 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
750 static inline int cache_attr(pgprot_t attr
)
752 return pgprot_val(attr
) &
753 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
756 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
757 pgprot_t mask_set
, pgprot_t mask_clr
,
758 int force_split
, int array
)
761 int ret
, cache
, checkalias
;
764 * Check, if we are requested to change a not supported
767 mask_set
= canon_pgprot(mask_set
);
768 mask_clr
= canon_pgprot(mask_clr
);
769 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
772 /* Ensure we are PAGE_SIZE aligned */
774 if (*addr
& ~PAGE_MASK
) {
777 * People should not be passing in unaligned addresses:
783 for (i
= 0; i
< numpages
; i
++) {
784 if (addr
[i
] & ~PAGE_MASK
) {
785 addr
[i
] &= PAGE_MASK
;
791 /* Must avoid aliasing mappings in the highmem code */
797 cpa
.numpages
= numpages
;
798 cpa
.mask_set
= mask_set
;
799 cpa
.mask_clr
= mask_clr
;
802 cpa
.force_split
= force_split
;
805 cpa
.flags
|= CPA_ARRAY
;
807 /* No alias checking for _NX bit modifications */
808 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
810 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
813 * Check whether we really changed something:
815 if (!(cpa
.flags
& CPA_FLUSHTLB
))
819 * No need to flush, when we did not set any of the caching
822 cache
= cache_attr(mask_set
);
825 * On success we use clflush, when the CPU supports it to
826 * avoid the wbindv. If the CPU does not support it and in the
827 * error case we fall back to cpa_flush_all (which uses
830 if (!ret
&& cpu_has_clflush
) {
831 if (cpa
.flags
& CPA_ARRAY
)
832 cpa_flush_array(addr
, numpages
, cache
);
834 cpa_flush_range(*addr
, numpages
, cache
);
836 cpa_flush_all(cache
);
842 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
843 pgprot_t mask
, int array
)
845 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
849 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
850 pgprot_t mask
, int array
)
852 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
856 int _set_memory_uc(unsigned long addr
, int numpages
)
859 * for now UC MINUS. see comments in ioremap_nocache()
861 return change_page_attr_set(&addr
, numpages
,
862 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
865 int set_memory_uc(unsigned long addr
, int numpages
)
868 * for now UC MINUS. see comments in ioremap_nocache()
870 if (reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
871 _PAGE_CACHE_UC_MINUS
, NULL
))
874 return _set_memory_uc(addr
, numpages
);
876 EXPORT_SYMBOL(set_memory_uc
);
878 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
884 * for now UC MINUS. see comments in ioremap_nocache()
886 for (i
= 0; i
< addrinarray
; i
++) {
887 start
= __pa(addr
[i
]);
888 for (end
= start
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
889 if (end
!= __pa(addr
[i
+ 1]))
893 if (reserve_memtype(start
, end
, _PAGE_CACHE_UC_MINUS
, NULL
))
897 return change_page_attr_set(addr
, addrinarray
,
898 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
900 for (i
= 0; i
< addrinarray
; i
++) {
901 unsigned long tmp
= __pa(addr
[i
]);
905 for (end
= tmp
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
906 if (end
!= __pa(addr
[i
+ 1]))
910 free_memtype(tmp
, end
);
914 EXPORT_SYMBOL(set_memory_array_uc
);
916 int _set_memory_wc(unsigned long addr
, int numpages
)
918 return change_page_attr_set(&addr
, numpages
,
919 __pgprot(_PAGE_CACHE_WC
), 0);
922 int set_memory_wc(unsigned long addr
, int numpages
)
925 return set_memory_uc(addr
, numpages
);
927 if (reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
928 _PAGE_CACHE_WC
, NULL
))
931 return _set_memory_wc(addr
, numpages
);
933 EXPORT_SYMBOL(set_memory_wc
);
935 int _set_memory_wb(unsigned long addr
, int numpages
)
937 return change_page_attr_clear(&addr
, numpages
,
938 __pgprot(_PAGE_CACHE_MASK
), 0);
941 int set_memory_wb(unsigned long addr
, int numpages
)
943 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
945 return _set_memory_wb(addr
, numpages
);
947 EXPORT_SYMBOL(set_memory_wb
);
949 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
953 for (i
= 0; i
< addrinarray
; i
++) {
954 unsigned long start
= __pa(addr
[i
]);
957 for (end
= start
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
958 if (end
!= __pa(addr
[i
+ 1]))
962 free_memtype(start
, end
);
964 return change_page_attr_clear(addr
, addrinarray
,
965 __pgprot(_PAGE_CACHE_MASK
), 1);
967 EXPORT_SYMBOL(set_memory_array_wb
);
969 int set_memory_x(unsigned long addr
, int numpages
)
971 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
973 EXPORT_SYMBOL(set_memory_x
);
975 int set_memory_nx(unsigned long addr
, int numpages
)
977 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
979 EXPORT_SYMBOL(set_memory_nx
);
981 int set_memory_ro(unsigned long addr
, int numpages
)
983 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
985 EXPORT_SYMBOL_GPL(set_memory_ro
);
987 int set_memory_rw(unsigned long addr
, int numpages
)
989 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
991 EXPORT_SYMBOL_GPL(set_memory_rw
);
993 int set_memory_np(unsigned long addr
, int numpages
)
995 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
998 int set_memory_4k(unsigned long addr
, int numpages
)
1000 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1004 int set_pages_uc(struct page
*page
, int numpages
)
1006 unsigned long addr
= (unsigned long)page_address(page
);
1008 return set_memory_uc(addr
, numpages
);
1010 EXPORT_SYMBOL(set_pages_uc
);
1012 int set_pages_wb(struct page
*page
, int numpages
)
1014 unsigned long addr
= (unsigned long)page_address(page
);
1016 return set_memory_wb(addr
, numpages
);
1018 EXPORT_SYMBOL(set_pages_wb
);
1020 int set_pages_x(struct page
*page
, int numpages
)
1022 unsigned long addr
= (unsigned long)page_address(page
);
1024 return set_memory_x(addr
, numpages
);
1026 EXPORT_SYMBOL(set_pages_x
);
1028 int set_pages_nx(struct page
*page
, int numpages
)
1030 unsigned long addr
= (unsigned long)page_address(page
);
1032 return set_memory_nx(addr
, numpages
);
1034 EXPORT_SYMBOL(set_pages_nx
);
1036 int set_pages_ro(struct page
*page
, int numpages
)
1038 unsigned long addr
= (unsigned long)page_address(page
);
1040 return set_memory_ro(addr
, numpages
);
1043 int set_pages_rw(struct page
*page
, int numpages
)
1045 unsigned long addr
= (unsigned long)page_address(page
);
1047 return set_memory_rw(addr
, numpages
);
1050 #ifdef CONFIG_DEBUG_PAGEALLOC
1052 static int __set_pages_p(struct page
*page
, int numpages
)
1054 unsigned long tempaddr
= (unsigned long) page_address(page
);
1055 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1056 .numpages
= numpages
,
1057 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1058 .mask_clr
= __pgprot(0),
1062 * No alias checking needed for setting present flag. otherwise,
1063 * we may need to break large pages for 64-bit kernel text
1064 * mappings (this adds to complexity if we want to do this from
1065 * atomic context especially). Let's keep it simple!
1067 return __change_page_attr_set_clr(&cpa
, 0);
1070 static int __set_pages_np(struct page
*page
, int numpages
)
1072 unsigned long tempaddr
= (unsigned long) page_address(page
);
1073 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1074 .numpages
= numpages
,
1075 .mask_set
= __pgprot(0),
1076 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1080 * No alias checking needed for setting not present flag. otherwise,
1081 * we may need to break large pages for 64-bit kernel text
1082 * mappings (this adds to complexity if we want to do this from
1083 * atomic context especially). Let's keep it simple!
1085 return __change_page_attr_set_clr(&cpa
, 0);
1088 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1090 if (PageHighMem(page
))
1093 debug_check_no_locks_freed(page_address(page
),
1094 numpages
* PAGE_SIZE
);
1098 * If page allocator is not up yet then do not call c_p_a():
1100 if (!debug_pagealloc_enabled
)
1104 * The return value is ignored as the calls cannot fail.
1105 * Large pages for identity mappings are not used at boot time
1106 * and hence no memory allocations during large page split.
1109 __set_pages_p(page
, numpages
);
1111 __set_pages_np(page
, numpages
);
1114 * We should perform an IPI and flush all tlbs,
1115 * but that can deadlock->flush only current cpu:
1120 #ifdef CONFIG_HIBERNATION
1122 bool kernel_page_present(struct page
*page
)
1127 if (PageHighMem(page
))
1130 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1131 return (pte_val(*pte
) & _PAGE_PRESENT
);
1134 #endif /* CONFIG_HIBERNATION */
1136 #endif /* CONFIG_DEBUG_PAGEALLOC */
1139 * The testcases use internal knowledge of the implementation that shouldn't
1140 * be exposed to the rest of the kernel. Include these directly here.
1142 #ifdef CONFIG_CPA_DEBUG
1143 #include "pageattr-test.c"