2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2008 MontaVista Software, Inc.
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
20 * Note that final HPT370 support was done by force extraction of GPL.
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
55 * Alan Cox <alan@lxorguk.ukuu.org.uk>
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
122 #include <linux/types.h>
123 #include <linux/module.h>
124 #include <linux/kernel.h>
125 #include <linux/delay.h>
126 #include <linux/blkdev.h>
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
132 #include <asm/uaccess.h>
135 #define DRV_NAME "hpt366"
137 /* various tuning parameters */
138 #undef HPT_RESET_STATE_ENGINE
139 #undef HPT_DELAY_INTERRUPT
140 #define HPT_SERIALIZE_IO 0
142 static const char *quirk_drives
[] = {
143 "QUANTUM FIREBALLlct08 08",
144 "QUANTUM FIREBALLP KA6.4",
145 "QUANTUM FIREBALLP LM20.4",
146 "QUANTUM FIREBALLP LM20.5",
150 static const char *bad_ata100_5
[] = {
169 static const char *bad_ata66_4
[] = {
185 "MAXTOR STM3320620A",
189 static const char *bad_ata66_3
[] = {
194 static const char *bad_ata33
[] = {
195 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
196 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
197 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
199 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
200 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
201 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
205 static u8 xfer_speeds
[] = {
225 /* Key for bus clock timings
228 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
230 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
232 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
234 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
236 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
237 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
238 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
240 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
241 * task file register access.
244 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
249 static u32 forty_base_hpt36x
[] = {
250 /* XFER_UDMA_6 */ 0x900fd943,
251 /* XFER_UDMA_5 */ 0x900fd943,
252 /* XFER_UDMA_4 */ 0x900fd943,
253 /* XFER_UDMA_3 */ 0x900ad943,
254 /* XFER_UDMA_2 */ 0x900bd943,
255 /* XFER_UDMA_1 */ 0x9008d943,
256 /* XFER_UDMA_0 */ 0x9008d943,
258 /* XFER_MW_DMA_2 */ 0xa008d943,
259 /* XFER_MW_DMA_1 */ 0xa010d955,
260 /* XFER_MW_DMA_0 */ 0xa010d9fc,
262 /* XFER_PIO_4 */ 0xc008d963,
263 /* XFER_PIO_3 */ 0xc010d974,
264 /* XFER_PIO_2 */ 0xc010d997,
265 /* XFER_PIO_1 */ 0xc010d9c7,
266 /* XFER_PIO_0 */ 0xc018d9d9
269 static u32 thirty_three_base_hpt36x
[] = {
270 /* XFER_UDMA_6 */ 0x90c9a731,
271 /* XFER_UDMA_5 */ 0x90c9a731,
272 /* XFER_UDMA_4 */ 0x90c9a731,
273 /* XFER_UDMA_3 */ 0x90cfa731,
274 /* XFER_UDMA_2 */ 0x90caa731,
275 /* XFER_UDMA_1 */ 0x90cba731,
276 /* XFER_UDMA_0 */ 0x90c8a731,
278 /* XFER_MW_DMA_2 */ 0xa0c8a731,
279 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
280 /* XFER_MW_DMA_0 */ 0xa0c8a797,
282 /* XFER_PIO_4 */ 0xc0c8a731,
283 /* XFER_PIO_3 */ 0xc0c8a742,
284 /* XFER_PIO_2 */ 0xc0d0a753,
285 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
286 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
289 static u32 twenty_five_base_hpt36x
[] = {
290 /* XFER_UDMA_6 */ 0x90c98521,
291 /* XFER_UDMA_5 */ 0x90c98521,
292 /* XFER_UDMA_4 */ 0x90c98521,
293 /* XFER_UDMA_3 */ 0x90cf8521,
294 /* XFER_UDMA_2 */ 0x90cf8521,
295 /* XFER_UDMA_1 */ 0x90cb8521,
296 /* XFER_UDMA_0 */ 0x90cb8521,
298 /* XFER_MW_DMA_2 */ 0xa0ca8521,
299 /* XFER_MW_DMA_1 */ 0xa0ca8532,
300 /* XFER_MW_DMA_0 */ 0xa0ca8575,
302 /* XFER_PIO_4 */ 0xc0ca8521,
303 /* XFER_PIO_3 */ 0xc0ca8532,
304 /* XFER_PIO_2 */ 0xc0ca8542,
305 /* XFER_PIO_1 */ 0xc0d08572,
306 /* XFER_PIO_0 */ 0xc0d08585
310 /* These are the timing tables from the HighPoint open source drivers... */
311 static u32 thirty_three_base_hpt37x
[] = {
312 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
313 /* XFER_UDMA_5 */ 0x12446231,
314 /* XFER_UDMA_4 */ 0x12446231,
315 /* XFER_UDMA_3 */ 0x126c6231,
316 /* XFER_UDMA_2 */ 0x12486231,
317 /* XFER_UDMA_1 */ 0x124c6233,
318 /* XFER_UDMA_0 */ 0x12506297,
320 /* XFER_MW_DMA_2 */ 0x22406c31,
321 /* XFER_MW_DMA_1 */ 0x22406c33,
322 /* XFER_MW_DMA_0 */ 0x22406c97,
324 /* XFER_PIO_4 */ 0x06414e31,
325 /* XFER_PIO_3 */ 0x06414e42,
326 /* XFER_PIO_2 */ 0x06414e53,
327 /* XFER_PIO_1 */ 0x06814e93,
328 /* XFER_PIO_0 */ 0x06814ea7
331 static u32 fifty_base_hpt37x
[] = {
332 /* XFER_UDMA_6 */ 0x12848242,
333 /* XFER_UDMA_5 */ 0x12848242,
334 /* XFER_UDMA_4 */ 0x12ac8242,
335 /* XFER_UDMA_3 */ 0x128c8242,
336 /* XFER_UDMA_2 */ 0x120c8242,
337 /* XFER_UDMA_1 */ 0x12148254,
338 /* XFER_UDMA_0 */ 0x121882ea,
340 /* XFER_MW_DMA_2 */ 0x22808242,
341 /* XFER_MW_DMA_1 */ 0x22808254,
342 /* XFER_MW_DMA_0 */ 0x228082ea,
344 /* XFER_PIO_4 */ 0x0a81f442,
345 /* XFER_PIO_3 */ 0x0a81f443,
346 /* XFER_PIO_2 */ 0x0a81f454,
347 /* XFER_PIO_1 */ 0x0ac1f465,
348 /* XFER_PIO_0 */ 0x0ac1f48a
351 static u32 sixty_six_base_hpt37x
[] = {
352 /* XFER_UDMA_6 */ 0x1c869c62,
353 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
354 /* XFER_UDMA_4 */ 0x1c8a9c62,
355 /* XFER_UDMA_3 */ 0x1c8e9c62,
356 /* XFER_UDMA_2 */ 0x1c929c62,
357 /* XFER_UDMA_1 */ 0x1c9a9c62,
358 /* XFER_UDMA_0 */ 0x1c829c62,
360 /* XFER_MW_DMA_2 */ 0x2c829c62,
361 /* XFER_MW_DMA_1 */ 0x2c829c66,
362 /* XFER_MW_DMA_0 */ 0x2c829d2e,
364 /* XFER_PIO_4 */ 0x0c829c62,
365 /* XFER_PIO_3 */ 0x0c829c84,
366 /* XFER_PIO_2 */ 0x0c829ca6,
367 /* XFER_PIO_1 */ 0x0d029d26,
368 /* XFER_PIO_0 */ 0x0d029d5e
372 * The following are the new timing tables with PIO mode data/taskfile transfer
373 * overclocking fixed...
376 /* This table is taken from the HPT370 data manual rev. 1.02 */
377 static u32 thirty_three_base_hpt37x
[] = {
378 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
379 /* XFER_UDMA_5 */ 0x16455031,
380 /* XFER_UDMA_4 */ 0x16455031,
381 /* XFER_UDMA_3 */ 0x166d5031,
382 /* XFER_UDMA_2 */ 0x16495031,
383 /* XFER_UDMA_1 */ 0x164d5033,
384 /* XFER_UDMA_0 */ 0x16515097,
386 /* XFER_MW_DMA_2 */ 0x26515031,
387 /* XFER_MW_DMA_1 */ 0x26515033,
388 /* XFER_MW_DMA_0 */ 0x26515097,
390 /* XFER_PIO_4 */ 0x06515021,
391 /* XFER_PIO_3 */ 0x06515022,
392 /* XFER_PIO_2 */ 0x06515033,
393 /* XFER_PIO_1 */ 0x06915065,
394 /* XFER_PIO_0 */ 0x06d1508a
397 static u32 fifty_base_hpt37x
[] = {
398 /* XFER_UDMA_6 */ 0x1a861842,
399 /* XFER_UDMA_5 */ 0x1a861842,
400 /* XFER_UDMA_4 */ 0x1aae1842,
401 /* XFER_UDMA_3 */ 0x1a8e1842,
402 /* XFER_UDMA_2 */ 0x1a0e1842,
403 /* XFER_UDMA_1 */ 0x1a161854,
404 /* XFER_UDMA_0 */ 0x1a1a18ea,
406 /* XFER_MW_DMA_2 */ 0x2a821842,
407 /* XFER_MW_DMA_1 */ 0x2a821854,
408 /* XFER_MW_DMA_0 */ 0x2a8218ea,
410 /* XFER_PIO_4 */ 0x0a821842,
411 /* XFER_PIO_3 */ 0x0a821843,
412 /* XFER_PIO_2 */ 0x0a821855,
413 /* XFER_PIO_1 */ 0x0ac218a8,
414 /* XFER_PIO_0 */ 0x0b02190c
417 static u32 sixty_six_base_hpt37x
[] = {
418 /* XFER_UDMA_6 */ 0x1c86fe62,
419 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
420 /* XFER_UDMA_4 */ 0x1c8afe62,
421 /* XFER_UDMA_3 */ 0x1c8efe62,
422 /* XFER_UDMA_2 */ 0x1c92fe62,
423 /* XFER_UDMA_1 */ 0x1c9afe62,
424 /* XFER_UDMA_0 */ 0x1c82fe62,
426 /* XFER_MW_DMA_2 */ 0x2c82fe62,
427 /* XFER_MW_DMA_1 */ 0x2c82fe66,
428 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
430 /* XFER_PIO_4 */ 0x0c82fe62,
431 /* XFER_PIO_3 */ 0x0c82fe84,
432 /* XFER_PIO_2 */ 0x0c82fea6,
433 /* XFER_PIO_1 */ 0x0d02ff26,
434 /* XFER_PIO_0 */ 0x0d42ff7f
438 #define HPT366_DEBUG_DRIVE_INFO 0
439 #define HPT371_ALLOW_ATA133_6 1
440 #define HPT302_ALLOW_ATA133_6 1
441 #define HPT372_ALLOW_ATA133_6 1
442 #define HPT370_ALLOW_ATA100_5 0
443 #define HPT366_ALLOW_ATA66_4 1
444 #define HPT366_ALLOW_ATA66_3 1
445 #define HPT366_MAX_DEVS 8
447 /* Supported ATA clock frequencies */
461 u32
*clock_table
[NUM_ATA_CLOCKS
];
465 * Hold all the HighPoint chip information in one place.
469 char *chip_name
; /* Chip name */
470 u8 chip_type
; /* Chip type */
471 u8 udma_mask
; /* Allowed UltraDMA modes mask. */
472 u8 dpll_clk
; /* DPLL clock in MHz */
473 u8 pci_clk
; /* PCI clock in MHz */
474 struct hpt_timings
*timings
; /* Chipset timing data */
475 u8 clock
; /* ATA clock selected */
478 /* Supported HighPoint chips */
493 static struct hpt_timings hpt36x_timings
= {
494 .pio_mask
= 0xc1f8ffff,
495 .dma_mask
= 0x303800ff,
496 .ultra_mask
= 0x30070000,
498 [ATA_CLOCK_25MHZ
] = twenty_five_base_hpt36x
,
499 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt36x
,
500 [ATA_CLOCK_40MHZ
] = forty_base_hpt36x
,
501 [ATA_CLOCK_50MHZ
] = NULL
,
502 [ATA_CLOCK_66MHZ
] = NULL
506 static struct hpt_timings hpt37x_timings
= {
507 .pio_mask
= 0xcfc3ffff,
508 .dma_mask
= 0x31c001ff,
509 .ultra_mask
= 0x303c0000,
511 [ATA_CLOCK_25MHZ
] = NULL
,
512 [ATA_CLOCK_33MHZ
] = thirty_three_base_hpt37x
,
513 [ATA_CLOCK_40MHZ
] = NULL
,
514 [ATA_CLOCK_50MHZ
] = fifty_base_hpt37x
,
515 [ATA_CLOCK_66MHZ
] = sixty_six_base_hpt37x
519 static const struct hpt_info hpt36x __devinitdata
= {
520 .chip_name
= "HPT36x",
522 .udma_mask
= HPT366_ALLOW_ATA66_3
? (HPT366_ALLOW_ATA66_4
? ATA_UDMA4
: ATA_UDMA3
) : ATA_UDMA2
,
523 .dpll_clk
= 0, /* no DPLL */
524 .timings
= &hpt36x_timings
527 static const struct hpt_info hpt370 __devinitdata
= {
528 .chip_name
= "HPT370",
530 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
532 .timings
= &hpt37x_timings
535 static const struct hpt_info hpt370a __devinitdata
= {
536 .chip_name
= "HPT370A",
537 .chip_type
= HPT370A
,
538 .udma_mask
= HPT370_ALLOW_ATA100_5
? ATA_UDMA5
: ATA_UDMA4
,
540 .timings
= &hpt37x_timings
543 static const struct hpt_info hpt374 __devinitdata
= {
544 .chip_name
= "HPT374",
546 .udma_mask
= ATA_UDMA5
,
548 .timings
= &hpt37x_timings
551 static const struct hpt_info hpt372 __devinitdata
= {
552 .chip_name
= "HPT372",
554 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
556 .timings
= &hpt37x_timings
559 static const struct hpt_info hpt372a __devinitdata
= {
560 .chip_name
= "HPT372A",
561 .chip_type
= HPT372A
,
562 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
564 .timings
= &hpt37x_timings
567 static const struct hpt_info hpt302 __devinitdata
= {
568 .chip_name
= "HPT302",
570 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
572 .timings
= &hpt37x_timings
575 static const struct hpt_info hpt371 __devinitdata
= {
576 .chip_name
= "HPT371",
578 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
580 .timings
= &hpt37x_timings
583 static const struct hpt_info hpt372n __devinitdata
= {
584 .chip_name
= "HPT372N",
585 .chip_type
= HPT372N
,
586 .udma_mask
= HPT372_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
588 .timings
= &hpt37x_timings
591 static const struct hpt_info hpt302n __devinitdata
= {
592 .chip_name
= "HPT302N",
593 .chip_type
= HPT302N
,
594 .udma_mask
= HPT302_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
596 .timings
= &hpt37x_timings
599 static const struct hpt_info hpt371n __devinitdata
= {
600 .chip_name
= "HPT371N",
601 .chip_type
= HPT371N
,
602 .udma_mask
= HPT371_ALLOW_ATA133_6
? ATA_UDMA6
: ATA_UDMA5
,
604 .timings
= &hpt37x_timings
607 static int check_in_drive_list(ide_drive_t
*drive
, const char **list
)
609 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
612 if (!strcmp(*list
++, m
))
617 static struct hpt_info
*hpt3xx_get_info(struct device
*dev
)
619 struct ide_host
*host
= dev_get_drvdata(dev
);
620 struct hpt_info
*info
= (struct hpt_info
*)host
->host_priv
;
622 return dev
== host
->dev
[1] ? info
+ 1 : info
;
626 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
627 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
630 static u8
hpt3xx_udma_filter(ide_drive_t
*drive
)
632 ide_hwif_t
*hwif
= HWIF(drive
);
633 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
634 u8 mask
= hwif
->ultra_mask
;
636 switch (info
->chip_type
) {
638 if (!HPT366_ALLOW_ATA66_4
||
639 check_in_drive_list(drive
, bad_ata66_4
))
642 if (!HPT366_ALLOW_ATA66_3
||
643 check_in_drive_list(drive
, bad_ata66_3
))
647 if (!HPT370_ALLOW_ATA100_5
||
648 check_in_drive_list(drive
, bad_ata100_5
))
652 if (!HPT370_ALLOW_ATA100_5
||
653 check_in_drive_list(drive
, bad_ata100_5
))
659 if (ata_id_is_sata(drive
->id
))
666 return check_in_drive_list(drive
, bad_ata33
) ? 0x00 : mask
;
669 static u8
hpt3xx_mdma_filter(ide_drive_t
*drive
)
671 ide_hwif_t
*hwif
= HWIF(drive
);
672 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
674 switch (info
->chip_type
) {
679 if (ata_id_is_sata(drive
->id
))
687 static u32
get_speed_setting(u8 speed
, struct hpt_info
*info
)
692 * Lookup the transfer mode table to get the index into
695 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
697 for (i
= 0; i
< ARRAY_SIZE(xfer_speeds
) - 1; i
++)
698 if (xfer_speeds
[i
] == speed
)
701 return info
->timings
->clock_table
[info
->clock
][i
];
704 static void hpt3xx_set_mode(ide_drive_t
*drive
, const u8 speed
)
706 ide_hwif_t
*hwif
= drive
->hwif
;
707 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
708 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
709 struct hpt_timings
*t
= info
->timings
;
710 u8 itr_addr
= 0x40 + (drive
->dn
* 4);
712 u32 new_itr
= get_speed_setting(speed
, info
);
713 u32 itr_mask
= speed
< XFER_MW_DMA_0
? t
->pio_mask
:
714 (speed
< XFER_UDMA_0
? t
->dma_mask
:
717 pci_read_config_dword(dev
, itr_addr
, &old_itr
);
718 new_itr
= (old_itr
& ~itr_mask
) | (new_itr
& itr_mask
);
720 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
721 * to avoid problems handling I/O errors later
723 new_itr
&= ~0xc0000000;
725 pci_write_config_dword(dev
, itr_addr
, new_itr
);
728 static void hpt3xx_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
730 hpt3xx_set_mode(drive
, XFER_PIO_0
+ pio
);
733 static void hpt3xx_quirkproc(ide_drive_t
*drive
)
735 char *m
= (char *)&drive
->id
[ATA_ID_PROD
];
736 const char **list
= quirk_drives
;
739 if (strstr(m
, *list
++)) {
740 drive
->quirk_list
= 1;
744 drive
->quirk_list
= 0;
747 static void hpt3xx_maskproc(ide_drive_t
*drive
, int mask
)
749 ide_hwif_t
*hwif
= HWIF(drive
);
750 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
751 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
753 if (drive
->quirk_list
== 0)
756 if (info
->chip_type
>= HPT370
) {
759 pci_read_config_byte(dev
, 0x5a, &scr1
);
760 if (((scr1
& 0x10) >> 4) != mask
) {
765 pci_write_config_byte(dev
, 0x5a, scr1
);
768 disable_irq(hwif
->irq
);
770 enable_irq(hwif
->irq
);
774 * This is specific to the HPT366 UDMA chipset
775 * by HighPoint|Triones Technologies, Inc.
777 static void hpt366_dma_lost_irq(ide_drive_t
*drive
)
779 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
780 u8 mcr1
= 0, mcr3
= 0, scr1
= 0;
782 pci_read_config_byte(dev
, 0x50, &mcr1
);
783 pci_read_config_byte(dev
, 0x52, &mcr3
);
784 pci_read_config_byte(dev
, 0x5a, &scr1
);
785 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
786 drive
->name
, __func__
, mcr1
, mcr3
, scr1
);
788 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
789 ide_dma_lost_irq(drive
);
792 static void hpt370_clear_engine(ide_drive_t
*drive
)
794 ide_hwif_t
*hwif
= HWIF(drive
);
795 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
797 pci_write_config_byte(dev
, hwif
->select_data
, 0x37);
801 static void hpt370_irq_timeout(ide_drive_t
*drive
)
803 ide_hwif_t
*hwif
= HWIF(drive
);
804 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
808 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
809 printk(KERN_DEBUG
"%s: %d bytes in FIFO\n", drive
->name
, bfifo
& 0x1ff);
811 /* get DMA command mode */
812 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
814 outb(dma_cmd
& ~0x1, hwif
->dma_base
+ ATA_DMA_CMD
);
815 hpt370_clear_engine(drive
);
818 static void hpt370_dma_start(ide_drive_t
*drive
)
820 #ifdef HPT_RESET_STATE_ENGINE
821 hpt370_clear_engine(drive
);
823 ide_dma_start(drive
);
826 static int hpt370_dma_end(ide_drive_t
*drive
)
828 ide_hwif_t
*hwif
= HWIF(drive
);
829 u8 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
831 if (dma_stat
& 0x01) {
834 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
836 hpt370_irq_timeout(drive
);
838 return ide_dma_end(drive
);
841 static void hpt370_dma_timeout(ide_drive_t
*drive
)
843 hpt370_irq_timeout(drive
);
844 ide_dma_timeout(drive
);
847 /* returns 1 if DMA IRQ issued, 0 otherwise */
848 static int hpt374_dma_test_irq(ide_drive_t
*drive
)
850 ide_hwif_t
*hwif
= HWIF(drive
);
851 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
855 pci_read_config_word(dev
, hwif
->select_data
+ 2, &bfifo
);
857 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
861 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
862 /* return 1 if INTR asserted */
869 static int hpt374_dma_end(ide_drive_t
*drive
)
871 ide_hwif_t
*hwif
= HWIF(drive
);
872 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
873 u8 mcr
= 0, mcr_addr
= hwif
->select_data
;
874 u8 bwsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
876 pci_read_config_byte(dev
, 0x6a, &bwsr
);
877 pci_read_config_byte(dev
, mcr_addr
, &mcr
);
879 pci_write_config_byte(dev
, mcr_addr
, mcr
| 0x30);
880 return ide_dma_end(drive
);
884 * hpt3xxn_set_clock - perform clock switching dance
885 * @hwif: hwif to switch
886 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
888 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
891 static void hpt3xxn_set_clock(ide_hwif_t
*hwif
, u8 mode
)
893 unsigned long base
= hwif
->extra_base
;
894 u8 scr2
= inb(base
+ 0x6b);
896 if ((scr2
& 0x7f) == mode
)
899 /* Tristate the bus */
900 outb(0x80, base
+ 0x63);
901 outb(0x80, base
+ 0x67);
903 /* Switch clock and reset channels */
904 outb(mode
, base
+ 0x6b);
905 outb(0xc0, base
+ 0x69);
908 * Reset the state machines.
909 * NOTE: avoid accidentally enabling the disabled channels.
911 outb(inb(base
+ 0x60) | 0x32, base
+ 0x60);
912 outb(inb(base
+ 0x64) | 0x32, base
+ 0x64);
915 outb(0x00, base
+ 0x69);
917 /* Reconnect channels to bus */
918 outb(0x00, base
+ 0x63);
919 outb(0x00, base
+ 0x67);
923 * hpt3xxn_rw_disk - prepare for I/O
924 * @drive: drive for command
925 * @rq: block request structure
927 * This is called when a disk I/O is issued to HPT3xxN.
928 * We need it because of the clock switching.
931 static void hpt3xxn_rw_disk(ide_drive_t
*drive
, struct request
*rq
)
933 hpt3xxn_set_clock(HWIF(drive
), rq_data_dir(rq
) ? 0x23 : 0x21);
937 * hpt37x_calibrate_dpll - calibrate the DPLL
940 * Perform a calibration cycle on the DPLL.
941 * Returns 1 if this succeeds
943 static int hpt37x_calibrate_dpll(struct pci_dev
*dev
, u16 f_low
, u16 f_high
)
945 u32 dpll
= (f_high
<< 16) | f_low
| 0x100;
949 pci_write_config_dword(dev
, 0x5c, dpll
);
951 /* Wait for oscillator ready */
952 for(i
= 0; i
< 0x5000; ++i
) {
954 pci_read_config_byte(dev
, 0x5b, &scr2
);
958 /* See if it stays ready (we'll just bail out if it's not yet) */
959 for(i
= 0; i
< 0x1000; ++i
) {
960 pci_read_config_byte(dev
, 0x5b, &scr2
);
961 /* DPLL destabilized? */
965 /* Turn off tuning, we have the DPLL set */
966 pci_read_config_dword (dev
, 0x5c, &dpll
);
967 pci_write_config_dword(dev
, 0x5c, (dpll
& ~0x100));
971 static void hpt3xx_disable_fast_irq(struct pci_dev
*dev
, u8 mcr_addr
)
973 struct ide_host
*host
= pci_get_drvdata(dev
);
974 struct hpt_info
*info
= host
->host_priv
+ (&dev
->dev
== host
->dev
[1]);
975 u8 chip_type
= info
->chip_type
;
976 u8 new_mcr
, old_mcr
= 0;
979 * Disable the "fast interrupt" prediction. Don't hold off
980 * on interrupts. (== 0x01 despite what the docs say)
982 pci_read_config_byte(dev
, mcr_addr
+ 1, &old_mcr
);
984 if (chip_type
>= HPT374
)
985 new_mcr
= old_mcr
& ~0x07;
986 else if (chip_type
>= HPT370
) {
989 #ifdef HPT_DELAY_INTERRUPT
994 } else /* HPT366 and HPT368 */
995 new_mcr
= old_mcr
& ~0x80;
997 if (new_mcr
!= old_mcr
)
998 pci_write_config_byte(dev
, mcr_addr
+ 1, new_mcr
);
1001 static unsigned int init_chipset_hpt366(struct pci_dev
*dev
)
1003 unsigned long io_base
= pci_resource_start(dev
, 4);
1004 struct hpt_info
*info
= hpt3xx_get_info(&dev
->dev
);
1005 const char *name
= DRV_NAME
;
1006 u8 pci_clk
, dpll_clk
= 0; /* PCI and DPLL clock in MHz */
1008 enum ata_clock clock
;
1010 chip_type
= info
->chip_type
;
1012 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, (L1_CACHE_BYTES
/ 4));
1013 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 0x78);
1014 pci_write_config_byte(dev
, PCI_MIN_GNT
, 0x08);
1015 pci_write_config_byte(dev
, PCI_MAX_LAT
, 0x08);
1018 * First, try to estimate the PCI clock frequency...
1020 if (chip_type
>= HPT370
) {
1025 /* Interrupt force enable. */
1026 pci_read_config_byte(dev
, 0x5a, &scr1
);
1028 pci_write_config_byte(dev
, 0x5a, scr1
& ~0x10);
1031 * HighPoint does this for HPT372A.
1032 * NOTE: This register is only writeable via I/O space.
1034 if (chip_type
== HPT372A
)
1035 outb(0x0e, io_base
+ 0x9c);
1038 * Default to PCI clock. Make sure MA15/16 are set to output
1039 * to prevent drives having problems with 40-pin cables.
1041 pci_write_config_byte(dev
, 0x5b, 0x23);
1044 * We'll have to read f_CNT value in order to determine
1045 * the PCI clock frequency according to the following ratio:
1047 * f_CNT = Fpci * 192 / Fdpll
1049 * First try reading the register in which the HighPoint BIOS
1050 * saves f_CNT value before reprogramming the DPLL from its
1051 * default setting (which differs for the various chips).
1053 * NOTE: This register is only accessible via I/O space;
1054 * HPT374 BIOS only saves it for the function 0, so we have to
1055 * always read it from there -- no need to check the result of
1056 * pci_get_slot() for the function 0 as the whole device has
1057 * been already "pinned" (via function 1) in init_setup_hpt374()
1059 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1060 struct pci_dev
*dev1
= pci_get_slot(dev
->bus
,
1062 unsigned long io_base
= pci_resource_start(dev1
, 4);
1064 temp
= inl(io_base
+ 0x90);
1067 temp
= inl(io_base
+ 0x90);
1070 * In case the signature check fails, we'll have to
1071 * resort to reading the f_CNT register itself in hopes
1072 * that nobody has touched the DPLL yet...
1074 if ((temp
& 0xFFFFF000) != 0xABCDE000) {
1077 printk(KERN_WARNING
"%s %s: no clock data saved by "
1078 "BIOS\n", name
, pci_name(dev
));
1080 /* Calculate the average value of f_CNT. */
1081 for (temp
= i
= 0; i
< 128; i
++) {
1082 pci_read_config_word(dev
, 0x78, &f_cnt
);
1083 temp
+= f_cnt
& 0x1ff;
1088 f_cnt
= temp
& 0x1ff;
1090 dpll_clk
= info
->dpll_clk
;
1091 pci_clk
= (f_cnt
* dpll_clk
) / 192;
1093 /* Clamp PCI clock to bands. */
1096 else if(pci_clk
< 45)
1098 else if(pci_clk
< 55)
1103 printk(KERN_INFO
"%s %s: DPLL base: %d MHz, f_CNT: %d, "
1104 "assuming %d MHz PCI\n", name
, pci_name(dev
),
1105 dpll_clk
, f_cnt
, pci_clk
);
1109 pci_read_config_dword(dev
, 0x40, &itr1
);
1111 /* Detect PCI clock by looking at cmd_high_time. */
1112 switch((itr1
>> 8) & 0x07) {
1126 /* Let's assume we'll use PCI clock for the ATA clock... */
1129 clock
= ATA_CLOCK_25MHZ
;
1133 clock
= ATA_CLOCK_33MHZ
;
1136 clock
= ATA_CLOCK_40MHZ
;
1139 clock
= ATA_CLOCK_50MHZ
;
1142 clock
= ATA_CLOCK_66MHZ
;
1147 * Only try the DPLL if we don't have a table for the PCI clock that
1148 * we are running at for HPT370/A, always use it for anything newer...
1150 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1151 * We also don't like using the DPLL because this causes glitches
1152 * on PRST-/SRST- when the state engine gets reset...
1154 if (chip_type
>= HPT374
|| info
->timings
->clock_table
[clock
] == NULL
) {
1155 u16 f_low
, delta
= pci_clk
< 50 ? 2 : 4;
1159 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1160 * supported/enabled, use 50 MHz DPLL clock otherwise...
1162 if (info
->udma_mask
== ATA_UDMA6
) {
1164 clock
= ATA_CLOCK_66MHZ
;
1165 } else if (dpll_clk
) { /* HPT36x chips don't have DPLL */
1167 clock
= ATA_CLOCK_50MHZ
;
1170 if (info
->timings
->clock_table
[clock
] == NULL
) {
1171 printk(KERN_ERR
"%s %s: unknown bus timing!\n",
1172 name
, pci_name(dev
));
1176 /* Select the DPLL clock. */
1177 pci_write_config_byte(dev
, 0x5b, 0x21);
1180 * Adjust the DPLL based upon PCI clock, enable it,
1181 * and wait for stabilization...
1183 f_low
= (pci_clk
* 48) / dpll_clk
;
1185 for (adjust
= 0; adjust
< 8; adjust
++) {
1186 if(hpt37x_calibrate_dpll(dev
, f_low
, f_low
+ delta
))
1190 * See if it'll settle at a fractionally different clock
1193 f_low
-= adjust
>> 1;
1195 f_low
+= adjust
>> 1;
1198 printk(KERN_ERR
"%s %s: DPLL did not stabilize!\n",
1199 name
, pci_name(dev
));
1203 printk(KERN_INFO
"%s %s: using %d MHz DPLL clock\n",
1204 name
, pci_name(dev
), dpll_clk
);
1206 /* Mark the fact that we're not using the DPLL. */
1209 printk(KERN_INFO
"%s %s: using %d MHz PCI clock\n",
1210 name
, pci_name(dev
), pci_clk
);
1213 /* Store the clock frequencies. */
1214 info
->dpll_clk
= dpll_clk
;
1215 info
->pci_clk
= pci_clk
;
1216 info
->clock
= clock
;
1218 if (chip_type
>= HPT370
) {
1222 * Reset the state engines.
1223 * NOTE: Avoid accidentally enabling the disabled channels.
1225 pci_read_config_byte (dev
, 0x50, &mcr1
);
1226 pci_read_config_byte (dev
, 0x54, &mcr4
);
1227 pci_write_config_byte(dev
, 0x50, (mcr1
| 0x32));
1228 pci_write_config_byte(dev
, 0x54, (mcr4
| 0x32));
1233 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1234 * the MISC. register to stretch the UltraDMA Tss timing.
1235 * NOTE: This register is only writeable via I/O space.
1237 if (chip_type
== HPT371N
&& clock
== ATA_CLOCK_66MHZ
)
1238 outb(inb(io_base
+ 0x9c) | 0x04, io_base
+ 0x9c);
1240 hpt3xx_disable_fast_irq(dev
, 0x50);
1241 hpt3xx_disable_fast_irq(dev
, 0x54);
1246 static u8
hpt3xx_cable_detect(ide_hwif_t
*hwif
)
1248 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1249 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
1250 u8 chip_type
= info
->chip_type
;
1251 u8 scr1
= 0, ata66
= hwif
->channel
? 0x01 : 0x02;
1254 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1255 * address lines to access an external EEPROM. To read valid
1256 * cable detect state the pins must be enabled as inputs.
1258 if (chip_type
== HPT374
&& (PCI_FUNC(dev
->devfn
) & 1)) {
1260 * HPT374 PCI function 1
1261 * - set bit 15 of reg 0x52 to enable TCBLID as input
1262 * - set bit 15 of reg 0x56 to enable FCBLID as input
1264 u8 mcr_addr
= hwif
->select_data
+ 2;
1267 pci_read_config_word(dev
, mcr_addr
, &mcr
);
1268 pci_write_config_word(dev
, mcr_addr
, (mcr
| 0x8000));
1269 /* now read cable id register */
1270 pci_read_config_byte(dev
, 0x5a, &scr1
);
1271 pci_write_config_word(dev
, mcr_addr
, mcr
);
1272 } else if (chip_type
>= HPT370
) {
1274 * HPT370/372 and 374 pcifn 0
1275 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1279 pci_read_config_byte(dev
, 0x5b, &scr2
);
1280 pci_write_config_byte(dev
, 0x5b, (scr2
& ~1));
1281 /* now read cable id register */
1282 pci_read_config_byte(dev
, 0x5a, &scr1
);
1283 pci_write_config_byte(dev
, 0x5b, scr2
);
1285 pci_read_config_byte(dev
, 0x5a, &scr1
);
1287 return (scr1
& ata66
) ? ATA_CBL_PATA40
: ATA_CBL_PATA80
;
1290 static void __devinit
init_hwif_hpt366(ide_hwif_t
*hwif
)
1292 struct hpt_info
*info
= hpt3xx_get_info(hwif
->dev
);
1293 int serialize
= HPT_SERIALIZE_IO
;
1294 u8 chip_type
= info
->chip_type
;
1296 /* Cache the channel's MISC. control registers' offset */
1297 hwif
->select_data
= hwif
->channel
? 0x54 : 0x50;
1300 * HPT3xxN chips have some complications:
1302 * - on 33 MHz PCI we must clock switch
1303 * - on 66 MHz PCI we must NOT use the PCI clock
1305 if (chip_type
>= HPT372N
&& info
->dpll_clk
&& info
->pci_clk
< 66) {
1307 * Clock is shared between the channels,
1308 * so we'll have to serialize them... :-(
1311 hwif
->rw_disk
= &hpt3xxn_rw_disk
;
1314 /* Serialize access to this device if needed */
1315 if (serialize
&& hwif
->mate
)
1316 hwif
->serialized
= hwif
->mate
->serialized
= 1;
1319 static int __devinit
init_dma_hpt366(ide_hwif_t
*hwif
,
1320 const struct ide_port_info
*d
)
1322 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1323 unsigned long flags
, base
= ide_pci_dma_base(hwif
, d
);
1324 u8 dma_old
, dma_new
, masterdma
= 0, slavedma
= 0;
1329 hwif
->dma_base
= base
;
1331 if (ide_pci_check_simplex(hwif
, d
) < 0)
1334 if (ide_pci_set_master(dev
, d
->name
) < 0)
1337 dma_old
= inb(base
+ 2);
1339 local_irq_save(flags
);
1342 pci_read_config_byte(dev
, hwif
->channel
? 0x4b : 0x43, &masterdma
);
1343 pci_read_config_byte(dev
, hwif
->channel
? 0x4f : 0x47, &slavedma
);
1345 if (masterdma
& 0x30) dma_new
|= 0x20;
1346 if ( slavedma
& 0x30) dma_new
|= 0x40;
1347 if (dma_new
!= dma_old
)
1348 outb(dma_new
, base
+ 2);
1350 local_irq_restore(flags
);
1352 printk(KERN_INFO
" %s: BM-DMA at 0x%04lx-0x%04lx\n",
1353 hwif
->name
, base
, base
+ 7);
1355 hwif
->extra_base
= base
+ (hwif
->channel
? 8 : 16);
1357 if (ide_allocate_dma_engine(hwif
))
1360 hwif
->dma_ops
= &sff_dma_ops
;
1365 static void __devinit
hpt374_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1367 if (dev2
->irq
!= dev
->irq
) {
1368 /* FIXME: we need a core pci_set_interrupt() */
1369 dev2
->irq
= dev
->irq
;
1370 printk(KERN_INFO DRV_NAME
" %s: PCI config space interrupt "
1371 "fixed\n", pci_name(dev2
));
1375 static void __devinit
hpt371_init(struct pci_dev
*dev
)
1380 * HPT371 chips physically have only one channel, the secondary one,
1381 * but the primary channel registers do exist! Go figure...
1382 * So, we manually disable the non-existing channel here
1383 * (if the BIOS hasn't done this already).
1385 pci_read_config_byte(dev
, 0x50, &mcr1
);
1387 pci_write_config_byte(dev
, 0x50, mcr1
& ~0x04);
1390 static int __devinit
hpt36x_init(struct pci_dev
*dev
, struct pci_dev
*dev2
)
1392 u8 mcr1
= 0, pin1
= 0, pin2
= 0;
1395 * Now we'll have to force both channels enabled if
1396 * at least one of them has been enabled by BIOS...
1398 pci_read_config_byte(dev
, 0x50, &mcr1
);
1400 pci_write_config_byte(dev
, 0x50, mcr1
| 0x30);
1402 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin1
);
1403 pci_read_config_byte(dev2
, PCI_INTERRUPT_PIN
, &pin2
);
1405 if (pin1
!= pin2
&& dev
->irq
== dev2
->irq
) {
1406 printk(KERN_INFO DRV_NAME
" %s: onboard version of chipset, "
1407 "pin1=%d pin2=%d\n", pci_name(dev
), pin1
, pin2
);
1414 #define IDE_HFLAGS_HPT3XX \
1415 (IDE_HFLAG_NO_ATAPI_DMA | \
1416 IDE_HFLAG_OFF_BOARD)
1418 static const struct ide_port_ops hpt3xx_port_ops
= {
1419 .set_pio_mode
= hpt3xx_set_pio_mode
,
1420 .set_dma_mode
= hpt3xx_set_mode
,
1421 .quirkproc
= hpt3xx_quirkproc
,
1422 .maskproc
= hpt3xx_maskproc
,
1423 .mdma_filter
= hpt3xx_mdma_filter
,
1424 .udma_filter
= hpt3xx_udma_filter
,
1425 .cable_detect
= hpt3xx_cable_detect
,
1428 static const struct ide_dma_ops hpt37x_dma_ops
= {
1429 .dma_host_set
= ide_dma_host_set
,
1430 .dma_setup
= ide_dma_setup
,
1431 .dma_exec_cmd
= ide_dma_exec_cmd
,
1432 .dma_start
= ide_dma_start
,
1433 .dma_end
= hpt374_dma_end
,
1434 .dma_test_irq
= hpt374_dma_test_irq
,
1435 .dma_lost_irq
= ide_dma_lost_irq
,
1436 .dma_timeout
= ide_dma_timeout
,
1439 static const struct ide_dma_ops hpt370_dma_ops
= {
1440 .dma_host_set
= ide_dma_host_set
,
1441 .dma_setup
= ide_dma_setup
,
1442 .dma_exec_cmd
= ide_dma_exec_cmd
,
1443 .dma_start
= hpt370_dma_start
,
1444 .dma_end
= hpt370_dma_end
,
1445 .dma_test_irq
= ide_dma_test_irq
,
1446 .dma_lost_irq
= ide_dma_lost_irq
,
1447 .dma_timeout
= hpt370_dma_timeout
,
1450 static const struct ide_dma_ops hpt36x_dma_ops
= {
1451 .dma_host_set
= ide_dma_host_set
,
1452 .dma_setup
= ide_dma_setup
,
1453 .dma_exec_cmd
= ide_dma_exec_cmd
,
1454 .dma_start
= ide_dma_start
,
1455 .dma_end
= ide_dma_end
,
1456 .dma_test_irq
= ide_dma_test_irq
,
1457 .dma_lost_irq
= hpt366_dma_lost_irq
,
1458 .dma_timeout
= ide_dma_timeout
,
1461 static const struct ide_port_info hpt366_chipsets
[] __devinitdata
= {
1464 .init_chipset
= init_chipset_hpt366
,
1465 .init_hwif
= init_hwif_hpt366
,
1466 .init_dma
= init_dma_hpt366
,
1468 * HPT36x chips have one channel per function and have
1469 * both channel enable bits located differently and visible
1470 * to both functions -- really stupid design decision... :-(
1471 * Bit 4 is for the primary channel, bit 5 for the secondary.
1473 .enablebits
= {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1474 .port_ops
= &hpt3xx_port_ops
,
1475 .dma_ops
= &hpt36x_dma_ops
,
1476 .host_flags
= IDE_HFLAGS_HPT3XX
| IDE_HFLAG_SINGLE
,
1477 .pio_mask
= ATA_PIO4
,
1478 .mwdma_mask
= ATA_MWDMA2
,
1482 .init_chipset
= init_chipset_hpt366
,
1483 .init_hwif
= init_hwif_hpt366
,
1484 .init_dma
= init_dma_hpt366
,
1485 .enablebits
= {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1486 .port_ops
= &hpt3xx_port_ops
,
1487 .dma_ops
= &hpt37x_dma_ops
,
1488 .host_flags
= IDE_HFLAGS_HPT3XX
,
1489 .pio_mask
= ATA_PIO4
,
1490 .mwdma_mask
= ATA_MWDMA2
,
1495 * hpt366_init_one - called when an HPT366 is found
1496 * @dev: the hpt366 device
1497 * @id: the matching pci id
1499 * Called when the PCI registration layer (or the IDE initialization)
1500 * finds a device matching our IDE device tables.
1502 static int __devinit
hpt366_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1504 const struct hpt_info
*info
= NULL
;
1505 struct hpt_info
*dyn_info
;
1506 struct pci_dev
*dev2
= NULL
;
1507 struct ide_port_info d
;
1508 u8 idx
= id
->driver_data
;
1509 u8 rev
= dev
->revision
;
1512 if ((idx
== 0 || idx
== 4) && (PCI_FUNC(dev
->devfn
) & 1))
1520 switch (min_t(u8
, rev
, 6)) {
1521 case 3: info
= &hpt370
; break;
1522 case 4: info
= &hpt370a
; break;
1523 case 5: info
= &hpt372
; break;
1524 case 6: info
= &hpt372n
; break;
1530 info
= (rev
> 1) ? &hpt372n
: &hpt372a
;
1533 info
= (rev
> 1) ? &hpt302n
: &hpt302
;
1537 info
= (rev
> 1) ? &hpt371n
: &hpt371
;
1547 printk(KERN_INFO DRV_NAME
": %s chipset detected\n", info
->chip_name
);
1549 d
= hpt366_chipsets
[min_t(u8
, idx
, 1)];
1551 d
.udma_mask
= info
->udma_mask
;
1553 /* fixup ->dma_ops for HPT370/HPT370A */
1554 if (info
== &hpt370
|| info
== &hpt370a
)
1555 d
.dma_ops
= &hpt370_dma_ops
;
1557 if (info
== &hpt36x
|| info
== &hpt374
)
1558 dev2
= pci_get_slot(dev
->bus
, dev
->devfn
+ 1);
1560 dyn_info
= kzalloc(sizeof(*dyn_info
) * (dev2
? 2 : 1), GFP_KERNEL
);
1561 if (dyn_info
== NULL
) {
1562 printk(KERN_ERR
"%s %s: out of memory!\n",
1563 d
.name
, pci_name(dev
));
1569 * Copy everything from a static "template" structure
1570 * to just allocated per-chip hpt_info structure.
1572 memcpy(dyn_info
, info
, sizeof(*dyn_info
));
1575 memcpy(dyn_info
+ 1, info
, sizeof(*dyn_info
));
1577 if (info
== &hpt374
)
1578 hpt374_init(dev
, dev2
);
1580 if (hpt36x_init(dev
, dev2
))
1581 d
.host_flags
&= ~IDE_HFLAG_NON_BOOTABLE
;
1584 ret
= ide_pci_init_two(dev
, dev2
, &d
, dyn_info
);
1592 ret
= ide_pci_init_one(dev
, &d
, dyn_info
);
1599 static void __devexit
hpt366_remove(struct pci_dev
*dev
)
1601 struct ide_host
*host
= pci_get_drvdata(dev
);
1602 struct ide_info
*info
= host
->host_priv
;
1603 struct pci_dev
*dev2
= host
->dev
[1] ? to_pci_dev(host
->dev
[1]) : NULL
;
1605 ide_pci_remove(dev
);
1610 static const struct pci_device_id hpt366_pci_tbl
[] __devinitconst
= {
1611 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT366
), 0 },
1612 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372
), 1 },
1613 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT302
), 2 },
1614 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT371
), 3 },
1615 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT374
), 4 },
1616 { PCI_VDEVICE(TTI
, PCI_DEVICE_ID_TTI_HPT372N
), 5 },
1619 MODULE_DEVICE_TABLE(pci
, hpt366_pci_tbl
);
1621 static struct pci_driver hpt366_pci_driver
= {
1622 .name
= "HPT366_IDE",
1623 .id_table
= hpt366_pci_tbl
,
1624 .probe
= hpt366_init_one
,
1625 .remove
= __devexit_p(hpt366_remove
),
1626 .suspend
= ide_pci_suspend
,
1627 .resume
= ide_pci_resume
,
1630 static int __init
hpt366_ide_init(void)
1632 return ide_pci_register_driver(&hpt366_pci_driver
);
1635 static void __exit
hpt366_ide_exit(void)
1637 pci_unregister_driver(&hpt366_pci_driver
);
1640 module_init(hpt366_ide_init
);
1641 module_exit(hpt366_ide_exit
);
1643 MODULE_AUTHOR("Andre Hedrick");
1644 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1645 MODULE_LICENSE("GPL");