2 * Copyright (c) 2009-2010 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
21 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 * Some Intel Ibex Peak based platforms support so-called "intelligent
26 * power sharing", which allows the CPU and GPU to cooperate to maximize
27 * performance within a given TDP (thermal design point). This driver
28 * performs the coordination between the CPU and GPU, monitors thermal and
29 * power statistics in the platform, and initializes power monitoring
30 * hardware. It also provides a few tunables to control behavior. Its
31 * primary purpose is to safely allow CPU and GPU turbo modes to be enabled
32 * by tracking power and thermal budget; secondarily it can boost turbo
33 * performance by allocating more power or thermal budget to the CPU or GPU
34 * based on available headroom and activity.
36 * The basic algorithm is driven by a 5s moving average of tempurature. If
37 * thermal headroom is available, the CPU and/or GPU power clamps may be
38 * adjusted upwards. If we hit the thermal ceiling or a thermal trigger,
39 * we scale back the clamp. Aside from trigger events (when we're critically
40 * close or over our TDP) we don't adjust the clamps more than once every
43 * The thermal device (device 31, function 6) has a set of registers that
44 * are updated by the ME firmware. The ME should also take the clamp values
45 * written to those registers and write them to the CPU, but we currently
46 * bypass that functionality and write the CPU MSR directly.
52 * - handle CPU hotplug
53 * - provide turbo enable/disable api
56 * - CDI 403777, 403778 - Auburndale EDS vol 1 & 2
57 * - CDI 401376 - Ibex Peak EDS
58 * - ref 26037, 26641 - IPS BIOS spec
59 * - ref 26489 - Nehalem BIOS writer's guide
60 * - ref 26921 - Ibex Peak BIOS Specification
63 #include <linux/debugfs.h>
64 #include <linux/delay.h>
65 #include <linux/interrupt.h>
66 #include <linux/kernel.h>
67 #include <linux/kthread.h>
68 #include <linux/module.h>
69 #include <linux/pci.h>
70 #include <linux/sched.h>
71 #include <linux/seq_file.h>
72 #include <linux/string.h>
73 #include <linux/tick.h>
74 #include <linux/timer.h>
75 #include <drm/i915_drm.h>
77 #include <asm/processor.h>
78 #include "intel_ips.h"
80 #define PCI_DEVICE_ID_INTEL_THERMAL_SENSOR 0x3b32
83 * Package level MSRs for monitor/control
85 #define PLATFORM_INFO 0xce
86 #define PLATFORM_TDP (1<<29)
87 #define PLATFORM_RATIO (1<<28)
89 #define IA32_MISC_ENABLE 0x1a0
90 #define IA32_MISC_TURBO_EN (1ULL<<38)
92 #define TURBO_POWER_CURRENT_LIMIT 0x1ac
93 #define TURBO_TDC_OVR_EN (1UL<<31)
94 #define TURBO_TDC_MASK (0x000000007fff0000UL)
95 #define TURBO_TDC_SHIFT (16)
96 #define TURBO_TDP_OVR_EN (1UL<<15)
97 #define TURBO_TDP_MASK (0x0000000000003fffUL)
100 * Core/thread MSRs for monitoring
102 #define IA32_PERF_CTL 0x199
103 #define IA32_PERF_TURBO_DIS (1ULL<<32)
106 * Thermal PCI device regs
108 #define THM_CFG_TBAR 0x10
109 #define THM_CFG_TBAR_HI 0x14
111 #define THM_TSIU 0x00
115 #define THM_TSTR 0x03
116 #define THM_TSTTP 0x04
117 #define THM_TSCO 0x08
118 #define THM_TSES 0x0c
119 #define THM_TSGPEN 0x0d
120 #define TSGPEN_HOT_LOHI (1<<1)
121 #define TSGPEN_CRIT_LOHI (1<<2)
122 #define THM_TSPC 0x0e
123 #define THM_PPEC 0x10
126 #define PTA_SLOPE_MASK (0xff00)
127 #define PTA_SLOPE_SHIFT 8
128 #define PTA_OFFSET_MASK (0x00ff)
129 #define THM_MGTA 0x16
130 #define MGTA_SLOPE_MASK (0xff00)
131 #define MGTA_SLOPE_SHIFT 8
132 #define MGTA_OFFSET_MASK (0x00ff)
134 #define TRC_CORE2_EN (1<<15)
135 #define TRC_THM_EN (1<<12)
136 #define TRC_C6_WAR (1<<8)
137 #define TRC_CORE1_EN (1<<7)
138 #define TRC_CORE_PWR (1<<6)
139 #define TRC_PCH_EN (1<<5)
140 #define TRC_MCH_EN (1<<4)
141 #define TRC_DIMM4 (1<<3)
142 #define TRC_DIMM3 (1<<2)
143 #define TRC_DIMM2 (1<<1)
144 #define TRC_DIMM1 (1<<0)
147 #define TEN_UPDATE_EN 1
149 #define PSC_NTG (1<<0) /* No GFX turbo support */
150 #define PSC_NTPC (1<<1) /* No CPU turbo support */
151 #define PSC_PP_DEF (0<<2) /* Perf policy up to driver */
152 #define PSP_PP_PC (1<<2) /* BIOS prefers CPU perf */
153 #define PSP_PP_BAL (2<<2) /* BIOS wants balanced perf */
154 #define PSP_PP_GFX (3<<2) /* BIOS prefers GFX perf */
155 #define PSP_PBRT (1<<4) /* BIOS run time support */
156 #define THM_CTV1 0x30
157 #define CTV_TEMP_ERROR (1<<15)
158 #define CTV_TEMP_MASK 0x3f
160 #define THM_CTV2 0x32
161 #define THM_CEC 0x34 /* undocumented power accumulator in joules */
163 #define THM_HTS 0x50 /* 32 bits */
164 #define HTS_PCPL_MASK (0x7fe00000)
165 #define HTS_PCPL_SHIFT 21
166 #define HTS_GPL_MASK (0x001ff000)
167 #define HTS_GPL_SHIFT 12
168 #define HTS_PP_MASK (0x00000c00)
169 #define HTS_PP_SHIFT 10
171 #define HTS_PP_PROC 1
174 #define HTS_PCTD_DIS (1<<9)
175 #define HTS_GTD_DIS (1<<8)
176 #define HTS_PTL_MASK (0x000000fe)
177 #define HTS_PTL_SHIFT 1
178 #define HTS_NVV (1<<0)
179 #define THM_HTSHI 0x54 /* 16 bits */
180 #define HTS2_PPL_MASK (0x03ff)
181 #define HTS2_PRST_MASK (0x3c00)
182 #define HTS2_PRST_SHIFT 10
183 #define HTS2_PRST_UNLOADED 0
184 #define HTS2_PRST_RUNNING 1
185 #define HTS2_PRST_TDISOP 2 /* turbo disabled due to power */
186 #define HTS2_PRST_TDISHT 3 /* turbo disabled due to high temp */
187 #define HTS2_PRST_TDISUSR 4 /* user disabled turbo */
188 #define HTS2_PRST_TDISPLAT 5 /* platform disabled turbo */
189 #define HTS2_PRST_TDISPM 6 /* power management disabled turbo */
190 #define HTS2_PRST_TDISERR 7 /* some kind of error disabled turbo */
192 #define THM_MGTV 0x58
193 #define TV_MASK 0x000000000000ff00
196 #define PTV_MASK 0x00ff
197 #define THM_MMGPC 0x64
198 #define THM_MPPC 0x66
199 #define THM_MPCPC 0x68
200 #define THM_TSPIEN 0x82
201 #define TSPIEN_AUX_LOHI (1<<0)
202 #define TSPIEN_HOT_LOHI (1<<1)
203 #define TSPIEN_CRIT_LOHI (1<<2)
204 #define TSPIEN_AUX2_LOHI (1<<3)
205 #define THM_TSLOCK 0x83
209 #define STS_PCPL_MASK (0x7fe00000)
210 #define STS_PCPL_SHIFT 21
211 #define STS_GPL_MASK (0x001ff000)
212 #define STS_GPL_SHIFT 12
213 #define STS_PP_MASK (0x00000c00)
214 #define STS_PP_SHIFT 10
216 #define STS_PP_PROC 1
219 #define STS_PCTD_DIS (1<<9)
220 #define STS_GTD_DIS (1<<8)
221 #define STS_PTL_MASK (0x000000fe)
222 #define STS_PTL_SHIFT 1
223 #define STS_NVV (1<<0)
225 #define SEC_ACK (1<<0)
228 #define STS_PPL_MASK (0x0003ff00)
229 #define STS_PPL_SHIFT 16
233 #define ITV_ME_SEQNO_MASK 0x00ff0000 /* ME should update every ~200ms */
234 #define ITV_ME_SEQNO_SHIFT (16)
235 #define ITV_MCH_TEMP_MASK 0x0000ff00
236 #define ITV_MCH_TEMP_SHIFT (8)
237 #define ITV_PCH_TEMP_MASK 0x000000ff
239 #define thm_readb(off) readb(ips->regmap + (off))
240 #define thm_readw(off) readw(ips->regmap + (off))
241 #define thm_readl(off) readl(ips->regmap + (off))
242 #define thm_readq(off) readq(ips->regmap + (off))
244 #define thm_writeb(off, val) writeb((val), ips->regmap + (off))
245 #define thm_writew(off, val) writew((val), ips->regmap + (off))
246 #define thm_writel(off, val) writel((val), ips->regmap + (off))
248 static const int IPS_ADJUST_PERIOD
= 5000; /* ms */
249 static bool late_i915_load
= false;
251 /* For initial average collection */
252 static const int IPS_SAMPLE_PERIOD
= 200; /* ms */
253 static const int IPS_SAMPLE_WINDOW
= 5000; /* 5s moving window of samples */
254 #define IPS_SAMPLE_COUNT (IPS_SAMPLE_WINDOW / IPS_SAMPLE_PERIOD)
257 struct ips_mcp_limits
{
259 int cpu_model
; /* includes extended model... */
260 int mcp_power_limit
; /* mW units */
261 int core_power_limit
;
263 int core_temp_limit
; /* degrees C */
267 /* Max temps are -10 degrees C to avoid PROCHOT# */
269 struct ips_mcp_limits ips_sv_limits
= {
270 .mcp_power_limit
= 35000,
271 .core_power_limit
= 29000,
272 .mch_power_limit
= 20000,
273 .core_temp_limit
= 95,
277 struct ips_mcp_limits ips_lv_limits
= {
278 .mcp_power_limit
= 25000,
279 .core_power_limit
= 21000,
280 .mch_power_limit
= 13000,
281 .core_temp_limit
= 95,
285 struct ips_mcp_limits ips_ulv_limits
= {
286 .mcp_power_limit
= 18000,
287 .core_power_limit
= 14000,
288 .mch_power_limit
= 11000,
289 .core_temp_limit
= 95,
296 struct task_struct
*monitor
;
297 struct task_struct
*adjust
;
298 struct dentry
*debug_root
;
300 /* Average CPU core temps (all averages in .01 degrees C for precision) */
305 /* Average for the CPU (both cores?) */
307 /* Average power consumption (in mW) */
316 /* Maximums & prefs, protected by turbo status lock */
317 spinlock_t turbo_status_lock
;
320 u16 core_power_limit
;
322 bool cpu_turbo_enabled
;
324 bool gpu_turbo_enabled
;
327 bool poll_turbo_status
;
329 bool turbo_toggle_allowed
;
330 struct ips_mcp_limits
*limits
;
332 /* Optional MCH interfaces for if i915 is in use */
333 unsigned long (*read_mch_val
)(void);
334 bool (*gpu_raise
)(void);
335 bool (*gpu_lower
)(void);
336 bool (*gpu_busy
)(void);
337 bool (*gpu_turbo_disable
)(void);
339 /* For restoration at unload */
340 u64 orig_turbo_limit
;
341 u64 orig_turbo_ratios
;
345 ips_gpu_turbo_enabled(struct ips_driver
*ips
);
348 * ips_cpu_busy - is CPU busy?
349 * @ips: IPS driver struct
351 * Check CPU for load to see whether we should increase its thermal budget.
354 * True if the CPU could use more power, false otherwise.
356 static bool ips_cpu_busy(struct ips_driver
*ips
)
358 if ((avenrun
[0] >> FSHIFT
) > 1)
365 * ips_cpu_raise - raise CPU power clamp
366 * @ips: IPS driver struct
368 * Raise the CPU power clamp by %IPS_CPU_STEP, in accordance with TDP for
371 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR upwards (as
372 * long as we haven't hit the TDP limit for the SKU).
374 static void ips_cpu_raise(struct ips_driver
*ips
)
377 u16 cur_tdp_limit
, new_tdp_limit
;
379 if (!ips
->cpu_turbo_enabled
)
382 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
384 cur_tdp_limit
= turbo_override
& TURBO_TDP_MASK
;
385 new_tdp_limit
= cur_tdp_limit
+ 8; /* 1W increase */
387 /* Clamp to SKU TDP limit */
388 if (((new_tdp_limit
* 10) / 8) > ips
->core_power_limit
)
389 new_tdp_limit
= cur_tdp_limit
;
391 thm_writew(THM_MPCPC
, (new_tdp_limit
* 10) / 8);
393 turbo_override
|= TURBO_TDC_OVR_EN
| TURBO_TDC_OVR_EN
;
394 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
396 turbo_override
&= ~TURBO_TDP_MASK
;
397 turbo_override
|= new_tdp_limit
;
399 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
403 * ips_cpu_lower - lower CPU power clamp
404 * @ips: IPS driver struct
406 * Lower CPU power clamp b %IPS_CPU_STEP if possible.
408 * We do this by adjusting the TURBO_POWER_CURRENT_LIMIT MSR down, going
409 * as low as the platform limits will allow (though we could go lower there
410 * wouldn't be much point).
412 static void ips_cpu_lower(struct ips_driver
*ips
)
415 u16 cur_limit
, new_limit
;
417 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
419 cur_limit
= turbo_override
& TURBO_TDP_MASK
;
420 new_limit
= cur_limit
- 8; /* 1W decrease */
422 /* Clamp to SKU TDP limit */
423 if (new_limit
< (ips
->orig_turbo_limit
& TURBO_TDP_MASK
))
424 new_limit
= ips
->orig_turbo_limit
& TURBO_TDP_MASK
;
426 thm_writew(THM_MPCPC
, (new_limit
* 10) / 8);
428 turbo_override
|= TURBO_TDC_OVR_EN
| TURBO_TDC_OVR_EN
;
429 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
431 turbo_override
&= ~TURBO_TDP_MASK
;
432 turbo_override
|= new_limit
;
434 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
438 * do_enable_cpu_turbo - internal turbo enable function
441 * Internal function for actually updating MSRs. When we enable/disable
442 * turbo, we need to do it on each CPU; this function is the one called
443 * by on_each_cpu() when needed.
445 static void do_enable_cpu_turbo(void *data
)
449 rdmsrl(IA32_PERF_CTL
, perf_ctl
);
450 if (perf_ctl
& IA32_PERF_TURBO_DIS
) {
451 perf_ctl
&= ~IA32_PERF_TURBO_DIS
;
452 wrmsrl(IA32_PERF_CTL
, perf_ctl
);
457 * ips_enable_cpu_turbo - enable turbo mode on all CPUs
458 * @ips: IPS driver struct
460 * Enable turbo mode by clearing the disable bit in IA32_PERF_CTL on
461 * all logical threads.
463 static void ips_enable_cpu_turbo(struct ips_driver
*ips
)
465 /* Already on, no need to mess with MSRs */
466 if (ips
->__cpu_turbo_on
)
469 if (ips
->turbo_toggle_allowed
)
470 on_each_cpu(do_enable_cpu_turbo
, ips
, 1);
472 ips
->__cpu_turbo_on
= true;
476 * do_disable_cpu_turbo - internal turbo disable function
479 * Internal function for actually updating MSRs. When we enable/disable
480 * turbo, we need to do it on each CPU; this function is the one called
481 * by on_each_cpu() when needed.
483 static void do_disable_cpu_turbo(void *data
)
487 rdmsrl(IA32_PERF_CTL
, perf_ctl
);
488 if (!(perf_ctl
& IA32_PERF_TURBO_DIS
)) {
489 perf_ctl
|= IA32_PERF_TURBO_DIS
;
490 wrmsrl(IA32_PERF_CTL
, perf_ctl
);
495 * ips_disable_cpu_turbo - disable turbo mode on all CPUs
496 * @ips: IPS driver struct
498 * Disable turbo mode by setting the disable bit in IA32_PERF_CTL on
499 * all logical threads.
501 static void ips_disable_cpu_turbo(struct ips_driver
*ips
)
503 /* Already off, leave it */
504 if (!ips
->__cpu_turbo_on
)
507 if (ips
->turbo_toggle_allowed
)
508 on_each_cpu(do_disable_cpu_turbo
, ips
, 1);
510 ips
->__cpu_turbo_on
= false;
514 * ips_gpu_busy - is GPU busy?
515 * @ips: IPS driver struct
517 * Check GPU for load to see whether we should increase its thermal budget.
518 * We need to call into the i915 driver in this case.
521 * True if the GPU could use more power, false otherwise.
523 static bool ips_gpu_busy(struct ips_driver
*ips
)
525 if (!ips_gpu_turbo_enabled(ips
))
528 return ips
->gpu_busy();
532 * ips_gpu_raise - raise GPU power clamp
533 * @ips: IPS driver struct
535 * Raise the GPU frequency/power if possible. We need to call into the
536 * i915 driver in this case.
538 static void ips_gpu_raise(struct ips_driver
*ips
)
540 if (!ips_gpu_turbo_enabled(ips
))
543 if (!ips
->gpu_raise())
544 ips
->gpu_turbo_enabled
= false;
550 * ips_gpu_lower - lower GPU power clamp
551 * @ips: IPS driver struct
553 * Lower GPU frequency/power if possible. Need to call i915.
555 static void ips_gpu_lower(struct ips_driver
*ips
)
557 if (!ips_gpu_turbo_enabled(ips
))
560 if (!ips
->gpu_lower())
561 ips
->gpu_turbo_enabled
= false;
567 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
568 * @ips: IPS driver struct
570 * Call into the graphics driver indicating that it can safely use
573 static void ips_enable_gpu_turbo(struct ips_driver
*ips
)
575 if (ips
->__gpu_turbo_on
)
577 ips
->__gpu_turbo_on
= true;
581 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
582 * @ips: IPS driver struct
584 * Request that the graphics driver disable turbo mode.
586 static void ips_disable_gpu_turbo(struct ips_driver
*ips
)
588 /* Avoid calling i915 if turbo is already disabled */
589 if (!ips
->__gpu_turbo_on
)
592 if (!ips
->gpu_turbo_disable())
593 dev_err(&ips
->dev
->dev
, "failed to disable graphis turbo\n");
595 ips
->__gpu_turbo_on
= false;
599 * mcp_exceeded - check whether we're outside our thermal & power limits
600 * @ips: IPS driver struct
602 * Check whether the MCP is over its thermal or power budget.
604 static bool mcp_exceeded(struct ips_driver
*ips
)
610 const char *msg
= "MCP limit exceeded: ";
612 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
614 temp_limit
= ips
->mcp_temp_limit
* 100;
615 if (ips
->mcp_avg_temp
> temp_limit
) {
616 dev_info(&ips
->dev
->dev
,
617 "%sAvg temp %u, limit %u\n", msg
, ips
->mcp_avg_temp
,
622 avg_power
= ips
->cpu_avg_power
+ ips
->mch_avg_power
;
623 if (avg_power
> ips
->mcp_power_limit
) {
624 dev_info(&ips
->dev
->dev
,
625 "%sAvg power %u, limit %u\n", msg
, avg_power
,
626 ips
->mcp_power_limit
);
630 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
636 * cpu_exceeded - check whether a CPU core is outside its limits
637 * @ips: IPS driver struct
638 * @cpu: CPU number to check
640 * Check a given CPU's average temp or power is over its limit.
642 static bool cpu_exceeded(struct ips_driver
*ips
, int cpu
)
648 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
649 avg
= cpu
? ips
->ctv2_avg_temp
: ips
->ctv1_avg_temp
;
650 if (avg
> (ips
->limits
->core_temp_limit
* 100))
652 if (ips
->cpu_avg_power
> ips
->core_power_limit
* 100)
654 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
657 dev_info(&ips
->dev
->dev
,
658 "CPU power or thermal limit exceeded\n");
664 * mch_exceeded - check whether the GPU is over budget
665 * @ips: IPS driver struct
667 * Check the MCH temp & power against their maximums.
669 static bool mch_exceeded(struct ips_driver
*ips
)
674 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
675 if (ips
->mch_avg_temp
> (ips
->limits
->mch_temp_limit
* 100))
677 if (ips
->mch_avg_power
> ips
->mch_power_limit
)
679 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
685 * verify_limits - verify BIOS provided limits
686 * @ips: IPS structure
688 * BIOS can optionally provide non-default limits for power and temp. Check
689 * them here and use the defaults if the BIOS values are not provided or
690 * are otherwise unusable.
692 static void verify_limits(struct ips_driver
*ips
)
694 if (ips
->mcp_power_limit
< ips
->limits
->mcp_power_limit
||
695 ips
->mcp_power_limit
> 35000)
696 ips
->mcp_power_limit
= ips
->limits
->mcp_power_limit
;
698 if (ips
->mcp_temp_limit
< ips
->limits
->core_temp_limit
||
699 ips
->mcp_temp_limit
< ips
->limits
->mch_temp_limit
||
700 ips
->mcp_temp_limit
> 150)
701 ips
->mcp_temp_limit
= min(ips
->limits
->core_temp_limit
,
702 ips
->limits
->mch_temp_limit
);
706 * update_turbo_limits - get various limits & settings from regs
707 * @ips: IPS driver struct
709 * Update the IPS power & temp limits, along with turbo enable flags,
710 * based on latest register contents.
712 * Used at init time and for runtime BIOS support, which requires polling
713 * the regs for updates (as a result of AC->DC transition for example).
716 * Caller must hold turbo_status_lock (outside of init)
718 static void update_turbo_limits(struct ips_driver
*ips
)
720 u32 hts
= thm_readl(THM_HTS
);
722 ips
->cpu_turbo_enabled
= !(hts
& HTS_PCTD_DIS
);
724 * Disable turbo for now, until we can figure out why the power figures
727 ips
->cpu_turbo_enabled
= false;
730 ips
->gpu_turbo_enabled
= !(hts
& HTS_GTD_DIS
);
732 ips
->core_power_limit
= thm_readw(THM_MPCPC
);
733 ips
->mch_power_limit
= thm_readw(THM_MMGPC
);
734 ips
->mcp_temp_limit
= thm_readw(THM_PTL
);
735 ips
->mcp_power_limit
= thm_readw(THM_MPPC
);
738 /* Ignore BIOS CPU vs GPU pref */
742 * ips_adjust - adjust power clamp based on thermal state
743 * @data: ips driver structure
745 * Wake up every 5s or so and check whether we should adjust the power clamp.
746 * Check CPU and GPU load to determine which needs adjustment. There are
747 * several things to consider here:
748 * - do we need to adjust up or down?
753 * - is CPU or GPU preferred? (CPU is default)
755 * So, given the above, we do the following:
756 * - up (TDP available)
757 * - CPU not busy, GPU not busy - nothing
758 * - CPU busy, GPU not busy - adjust CPU up
759 * - CPU not busy, GPU busy - adjust GPU up
760 * - CPU busy, GPU busy - adjust preferred unit up, taking headroom from
761 * non-preferred unit if necessary
762 * - down (at TDP limit)
763 * - adjust both CPU and GPU down if possible
765 cpu+ gpu+ cpu+gpu- cpu-gpu+ cpu-gpu-
766 cpu < gpu < cpu+gpu+ cpu+ gpu+ nothing
767 cpu < gpu >= cpu+gpu-(mcp<) cpu+gpu-(mcp<) gpu- gpu-
768 cpu >= gpu < cpu-gpu+(mcp<) cpu- cpu-gpu+(mcp<) cpu-
769 cpu >= gpu >= cpu-gpu- cpu-gpu- cpu-gpu- cpu-gpu-
772 static int ips_adjust(void *data
)
774 struct ips_driver
*ips
= data
;
777 dev_dbg(&ips
->dev
->dev
, "starting ips-adjust thread\n");
780 * Adjust CPU and GPU clamps every 5s if needed. Doing it more
781 * often isn't recommended due to ME interaction.
784 bool cpu_busy
= ips_cpu_busy(ips
);
785 bool gpu_busy
= ips_gpu_busy(ips
);
787 spin_lock_irqsave(&ips
->turbo_status_lock
, flags
);
788 if (ips
->poll_turbo_status
)
789 update_turbo_limits(ips
);
790 spin_unlock_irqrestore(&ips
->turbo_status_lock
, flags
);
792 /* Update turbo status if necessary */
793 if (ips
->cpu_turbo_enabled
)
794 ips_enable_cpu_turbo(ips
);
796 ips_disable_cpu_turbo(ips
);
798 if (ips
->gpu_turbo_enabled
)
799 ips_enable_gpu_turbo(ips
);
801 ips_disable_gpu_turbo(ips
);
803 /* We're outside our comfort zone, crank them down */
804 if (mcp_exceeded(ips
)) {
810 if (!cpu_exceeded(ips
, 0) && cpu_busy
)
815 if (!mch_exceeded(ips
) && gpu_busy
)
821 schedule_timeout_interruptible(msecs_to_jiffies(IPS_ADJUST_PERIOD
));
822 } while (!kthread_should_stop());
824 dev_dbg(&ips
->dev
->dev
, "ips-adjust thread stopped\n");
830 * Helpers for reading out temp/power values and calculating their
831 * averages for the decision making and monitoring functions.
834 static u16
calc_avg_temp(struct ips_driver
*ips
, u16
*array
)
840 for (i
= 0; i
< IPS_SAMPLE_COUNT
; i
++)
841 total
+= (u64
)(array
[i
] * 100);
843 do_div(total
, IPS_SAMPLE_COUNT
);
850 static u16
read_mgtv(struct ips_driver
*ips
)
856 val
= thm_readq(THM_MGTV
);
857 val
= (val
& TV_MASK
) >> TV_SHIFT
;
859 slope
= offset
= thm_readw(THM_MGTA
);
860 slope
= (slope
& MGTA_SLOPE_MASK
) >> MGTA_SLOPE_SHIFT
;
861 offset
= offset
& MGTA_OFFSET_MASK
;
863 ret
= ((val
* slope
+ 0x40) >> 7) + offset
;
865 return 0; /* MCH temp reporting buggy */
868 static u16
read_ptv(struct ips_driver
*ips
)
870 u16 val
, slope
, offset
;
872 slope
= (ips
->pta_val
& PTA_SLOPE_MASK
) >> PTA_SLOPE_SHIFT
;
873 offset
= ips
->pta_val
& PTA_OFFSET_MASK
;
875 val
= thm_readw(THM_PTV
) & PTV_MASK
;
880 static u16
read_ctv(struct ips_driver
*ips
, int cpu
)
882 int reg
= cpu
? THM_CTV2
: THM_CTV1
;
885 val
= thm_readw(reg
);
886 if (!(val
& CTV_TEMP_ERROR
))
887 val
= (val
) >> 6; /* discard fractional component */
894 static u32
get_cpu_power(struct ips_driver
*ips
, u32
*last
, int period
)
900 * CEC is in joules/65535. Take difference over time to
903 val
= thm_readl(THM_CEC
);
905 /* period is in ms and we want mW */
906 ret
= (((val
- *last
) * 1000) / period
);
907 ret
= (ret
* 1000) / 65535;
913 static const u16 temp_decay_factor
= 2;
914 static u16
update_average_temp(u16 avg
, u16 val
)
918 /* Multiply by 100 for extra precision */
919 ret
= (val
* 100 / temp_decay_factor
) +
920 (((temp_decay_factor
- 1) * avg
) / temp_decay_factor
);
924 static const u16 power_decay_factor
= 2;
925 static u16
update_average_power(u32 avg
, u32 val
)
929 ret
= (val
/ power_decay_factor
) +
930 (((power_decay_factor
- 1) * avg
) / power_decay_factor
);
935 static u32
calc_avg_power(struct ips_driver
*ips
, u32
*array
)
941 for (i
= 0; i
< IPS_SAMPLE_COUNT
; i
++)
944 do_div(total
, IPS_SAMPLE_COUNT
);
950 static void monitor_timeout(unsigned long arg
)
952 wake_up_process((struct task_struct
*)arg
);
956 * ips_monitor - temp/power monitoring thread
957 * @data: ips driver structure
959 * This is the main function for the IPS driver. It monitors power and
960 * tempurature in the MCP and adjusts CPU and GPU power clams accordingly.
962 * We keep a 5s moving average of power consumption and tempurature. Using
963 * that data, along with CPU vs GPU preference, we adjust the power clamps
966 static int ips_monitor(void *data
)
968 struct ips_driver
*ips
= data
;
969 struct timer_list timer
;
970 unsigned long seqno_timestamp
, expire
, last_msecs
, last_sample_period
;
972 u32
*cpu_samples
, *mchp_samples
, old_cpu_power
;
973 u16
*mcp_samples
, *ctv1_samples
, *ctv2_samples
, *mch_samples
;
974 u8 cur_seqno
, last_seqno
;
976 mcp_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
977 ctv1_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
978 ctv2_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
979 mch_samples
= kzalloc(sizeof(u16
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
980 cpu_samples
= kzalloc(sizeof(u32
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
981 mchp_samples
= kzalloc(sizeof(u32
) * IPS_SAMPLE_COUNT
, GFP_KERNEL
);
982 if (!mcp_samples
|| !ctv1_samples
|| !ctv2_samples
|| !mch_samples
||
983 !cpu_samples
|| !mchp_samples
) {
984 dev_err(&ips
->dev
->dev
,
985 "failed to allocate sample array, ips disabled\n");
995 last_seqno
= (thm_readl(THM_ITV
) & ITV_ME_SEQNO_MASK
) >>
997 seqno_timestamp
= get_jiffies_64();
999 old_cpu_power
= thm_readl(THM_CEC
);
1000 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD
));
1002 /* Collect an initial average */
1003 for (i
= 0; i
< IPS_SAMPLE_COUNT
; i
++) {
1004 u32 mchp
, cpu_power
;
1007 mcp_samples
[i
] = read_ptv(ips
);
1009 val
= read_ctv(ips
, 0);
1010 ctv1_samples
[i
] = val
;
1012 val
= read_ctv(ips
, 1);
1013 ctv2_samples
[i
] = val
;
1015 val
= read_mgtv(ips
);
1016 mch_samples
[i
] = val
;
1018 cpu_power
= get_cpu_power(ips
, &old_cpu_power
,
1020 cpu_samples
[i
] = cpu_power
;
1022 if (ips
->read_mch_val
) {
1023 mchp
= ips
->read_mch_val();
1024 mchp_samples
[i
] = mchp
;
1027 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD
));
1028 if (kthread_should_stop())
1032 ips
->mcp_avg_temp
= calc_avg_temp(ips
, mcp_samples
);
1033 ips
->ctv1_avg_temp
= calc_avg_temp(ips
, ctv1_samples
);
1034 ips
->ctv2_avg_temp
= calc_avg_temp(ips
, ctv2_samples
);
1035 ips
->mch_avg_temp
= calc_avg_temp(ips
, mch_samples
);
1036 ips
->cpu_avg_power
= calc_avg_power(ips
, cpu_samples
);
1037 ips
->mch_avg_power
= calc_avg_power(ips
, mchp_samples
);
1039 kfree(ctv1_samples
);
1040 kfree(ctv2_samples
);
1043 kfree(mchp_samples
);
1045 /* Start the adjustment thread now that we have data */
1046 wake_up_process(ips
->adjust
);
1049 * Ok, now we have an initial avg. From here on out, we track the
1050 * running avg using a decaying average calculation. This allows
1051 * us to reduce the sample frequency if the CPU and GPU are idle.
1053 old_cpu_power
= thm_readl(THM_CEC
);
1054 schedule_timeout_interruptible(msecs_to_jiffies(IPS_SAMPLE_PERIOD
));
1055 last_sample_period
= IPS_SAMPLE_PERIOD
;
1057 setup_deferrable_timer_on_stack(&timer
, monitor_timeout
,
1058 (unsigned long)current
);
1060 u32 cpu_val
, mch_val
;
1064 val
= read_ptv(ips
);
1065 ips
->mcp_avg_temp
= update_average_temp(ips
->mcp_avg_temp
, val
);
1068 val
= read_ctv(ips
, 0);
1069 ips
->ctv1_avg_temp
=
1070 update_average_temp(ips
->ctv1_avg_temp
, val
);
1072 cpu_val
= get_cpu_power(ips
, &old_cpu_power
,
1073 last_sample_period
);
1074 ips
->cpu_avg_power
=
1075 update_average_power(ips
->cpu_avg_power
, cpu_val
);
1077 if (ips
->second_cpu
) {
1079 val
= read_ctv(ips
, 1);
1080 ips
->ctv2_avg_temp
=
1081 update_average_temp(ips
->ctv2_avg_temp
, val
);
1085 val
= read_mgtv(ips
);
1086 ips
->mch_avg_temp
= update_average_temp(ips
->mch_avg_temp
, val
);
1088 if (ips
->read_mch_val
) {
1089 mch_val
= ips
->read_mch_val();
1090 ips
->mch_avg_power
=
1091 update_average_power(ips
->mch_avg_power
,
1096 * Make sure ME is updating thermal regs.
1098 * If it's been more than a second since the last update,
1099 * the ME is probably hung.
1101 cur_seqno
= (thm_readl(THM_ITV
) & ITV_ME_SEQNO_MASK
) >>
1103 if (cur_seqno
== last_seqno
&&
1104 time_after(jiffies
, seqno_timestamp
+ HZ
)) {
1105 dev_warn(&ips
->dev
->dev
, "ME failed to update for more than 1s, likely hung\n");
1107 seqno_timestamp
= get_jiffies_64();
1108 last_seqno
= cur_seqno
;
1111 last_msecs
= jiffies_to_msecs(jiffies
);
1112 expire
= jiffies
+ msecs_to_jiffies(IPS_SAMPLE_PERIOD
);
1114 __set_current_state(TASK_INTERRUPTIBLE
);
1115 mod_timer(&timer
, expire
);
1118 /* Calculate actual sample period for power averaging */
1119 last_sample_period
= jiffies_to_msecs(jiffies
) - last_msecs
;
1120 if (!last_sample_period
)
1121 last_sample_period
= 1;
1122 } while (!kthread_should_stop());
1124 del_timer_sync(&timer
);
1125 destroy_timer_on_stack(&timer
);
1127 dev_dbg(&ips
->dev
->dev
, "ips-monitor thread stopped\n");
1133 #define THM_DUMPW(reg) \
1135 u16 val = thm_readw(reg); \
1136 dev_dbg(&ips->dev->dev, #reg ": 0x%04x\n", val); \
1138 #define THM_DUMPL(reg) \
1140 u32 val = thm_readl(reg); \
1141 dev_dbg(&ips->dev->dev, #reg ": 0x%08x\n", val); \
1143 #define THM_DUMPQ(reg) \
1145 u64 val = thm_readq(reg); \
1146 dev_dbg(&ips->dev->dev, #reg ": 0x%016x\n", val); \
1149 static void dump_thermal_info(struct ips_driver
*ips
)
1153 ptl
= thm_readw(THM_PTL
);
1154 dev_dbg(&ips
->dev
->dev
, "Processor temp limit: %d\n", ptl
);
1158 THM_DUMPW(THM_CTV1
);
1161 THM_DUMPQ(THM_MGTV
);
1166 * ips_irq_handler - handle temperature triggers and other IPS events
1170 * Handle temperature limit trigger events, generally by lowering the clamps.
1171 * If we're at a critical limit, we clamp back to the lowest possible value
1172 * to prevent emergency shutdown.
1174 static irqreturn_t
ips_irq_handler(int irq
, void *arg
)
1176 struct ips_driver
*ips
= arg
;
1177 u8 tses
= thm_readb(THM_TSES
);
1178 u8 tes
= thm_readb(THM_TES
);
1183 dev_info(&ips
->dev
->dev
, "TSES: 0x%02x\n", tses
);
1184 dev_info(&ips
->dev
->dev
, "TES: 0x%02x\n", tes
);
1186 /* STS update from EC? */
1190 sts
= thm_readl(THM_STS
);
1191 tc1
= thm_readl(THM_TC1
);
1193 if (sts
& STS_NVV
) {
1194 spin_lock(&ips
->turbo_status_lock
);
1195 ips
->core_power_limit
= (sts
& STS_PCPL_MASK
) >>
1197 ips
->mch_power_limit
= (sts
& STS_GPL_MASK
) >>
1199 /* ignore EC CPU vs GPU pref */
1200 ips
->cpu_turbo_enabled
= !(sts
& STS_PCTD_DIS
);
1202 * Disable turbo for now, until we can figure
1203 * out why the power figures are wrong
1205 ips
->cpu_turbo_enabled
= false;
1207 ips
->gpu_turbo_enabled
= !(sts
& STS_GTD_DIS
);
1208 ips
->mcp_temp_limit
= (sts
& STS_PTL_MASK
) >>
1210 ips
->mcp_power_limit
= (tc1
& STS_PPL_MASK
) >>
1213 spin_unlock(&ips
->turbo_status_lock
);
1215 thm_writeb(THM_SEC
, SEC_ACK
);
1217 thm_writeb(THM_TES
, tes
);
1222 dev_warn(&ips
->dev
->dev
,
1223 "thermal trip occurred, tses: 0x%04x\n", tses
);
1224 thm_writeb(THM_TSES
, tses
);
1230 #ifndef CONFIG_DEBUG_FS
1231 static void ips_debugfs_init(struct ips_driver
*ips
) { return; }
1232 static void ips_debugfs_cleanup(struct ips_driver
*ips
) { return; }
1235 /* Expose current state and limits in debugfs if possible */
1237 struct ips_debugfs_node
{
1238 struct ips_driver
*ips
;
1240 int (*show
)(struct seq_file
*m
, void *data
);
1243 static int show_cpu_temp(struct seq_file
*m
, void *data
)
1245 struct ips_driver
*ips
= m
->private;
1247 seq_printf(m
, "%d.%02d\n", ips
->ctv1_avg_temp
/ 100,
1248 ips
->ctv1_avg_temp
% 100);
1253 static int show_cpu_power(struct seq_file
*m
, void *data
)
1255 struct ips_driver
*ips
= m
->private;
1257 seq_printf(m
, "%dmW\n", ips
->cpu_avg_power
);
1262 static int show_cpu_clamp(struct seq_file
*m
, void *data
)
1267 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
1269 tdp
= (int)(turbo_override
& TURBO_TDP_MASK
);
1270 tdc
= (int)((turbo_override
& TURBO_TDC_MASK
) >> TURBO_TDC_SHIFT
);
1272 /* Convert to .1W/A units */
1277 seq_printf(m
, "%d.%dW %d.%dA\n", tdp
/ 10, tdp
% 10,
1278 tdc
/ 10, tdc
% 10);
1283 static int show_mch_temp(struct seq_file
*m
, void *data
)
1285 struct ips_driver
*ips
= m
->private;
1287 seq_printf(m
, "%d.%02d\n", ips
->mch_avg_temp
/ 100,
1288 ips
->mch_avg_temp
% 100);
1293 static int show_mch_power(struct seq_file
*m
, void *data
)
1295 struct ips_driver
*ips
= m
->private;
1297 seq_printf(m
, "%dmW\n", ips
->mch_avg_power
);
1302 static struct ips_debugfs_node ips_debug_files
[] = {
1303 { NULL
, "cpu_temp", show_cpu_temp
},
1304 { NULL
, "cpu_power", show_cpu_power
},
1305 { NULL
, "cpu_clamp", show_cpu_clamp
},
1306 { NULL
, "mch_temp", show_mch_temp
},
1307 { NULL
, "mch_power", show_mch_power
},
1310 static int ips_debugfs_open(struct inode
*inode
, struct file
*file
)
1312 struct ips_debugfs_node
*node
= inode
->i_private
;
1314 return single_open(file
, node
->show
, node
->ips
);
1317 static const struct file_operations ips_debugfs_ops
= {
1318 .owner
= THIS_MODULE
,
1319 .open
= ips_debugfs_open
,
1321 .llseek
= seq_lseek
,
1322 .release
= single_release
,
1325 static void ips_debugfs_cleanup(struct ips_driver
*ips
)
1327 if (ips
->debug_root
)
1328 debugfs_remove_recursive(ips
->debug_root
);
1332 static void ips_debugfs_init(struct ips_driver
*ips
)
1336 ips
->debug_root
= debugfs_create_dir("ips", NULL
);
1337 if (!ips
->debug_root
) {
1338 dev_err(&ips
->dev
->dev
,
1339 "failed to create debugfs entries: %ld\n",
1340 PTR_ERR(ips
->debug_root
));
1344 for (i
= 0; i
< ARRAY_SIZE(ips_debug_files
); i
++) {
1346 struct ips_debugfs_node
*node
= &ips_debug_files
[i
];
1349 ent
= debugfs_create_file(node
->name
, S_IFREG
| S_IRUGO
,
1350 ips
->debug_root
, node
,
1353 dev_err(&ips
->dev
->dev
,
1354 "failed to create debug file: %ld\n",
1363 ips_debugfs_cleanup(ips
);
1366 #endif /* CONFIG_DEBUG_FS */
1369 * ips_detect_cpu - detect whether CPU supports IPS
1371 * Walk our list and see if we're on a supported CPU. If we find one,
1372 * return the limits for it.
1374 static struct ips_mcp_limits
*ips_detect_cpu(struct ips_driver
*ips
)
1376 u64 turbo_power
, misc_en
;
1377 struct ips_mcp_limits
*limits
= NULL
;
1380 if (!(boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
== 37)) {
1381 dev_info(&ips
->dev
->dev
, "Non-IPS CPU detected.\n");
1385 rdmsrl(IA32_MISC_ENABLE
, misc_en
);
1387 * If the turbo enable bit isn't set, we shouldn't try to enable/disable
1388 * turbo manually or we'll get an illegal MSR access, even though
1389 * turbo will still be available.
1391 if (misc_en
& IA32_MISC_TURBO_EN
)
1392 ips
->turbo_toggle_allowed
= true;
1394 ips
->turbo_toggle_allowed
= false;
1396 if (strstr(boot_cpu_data
.x86_model_id
, "CPU M"))
1397 limits
= &ips_sv_limits
;
1398 else if (strstr(boot_cpu_data
.x86_model_id
, "CPU L"))
1399 limits
= &ips_lv_limits
;
1400 else if (strstr(boot_cpu_data
.x86_model_id
, "CPU U"))
1401 limits
= &ips_ulv_limits
;
1403 dev_info(&ips
->dev
->dev
, "No CPUID match found.\n");
1407 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_power
);
1408 tdp
= turbo_power
& TURBO_TDP_MASK
;
1410 /* Sanity check TDP against CPU */
1411 if (limits
->core_power_limit
!= (tdp
/ 8) * 1000) {
1412 dev_info(&ips
->dev
->dev
, "CPU TDP doesn't match expected value (found %d, expected %d)\n",
1413 tdp
/ 8, limits
->core_power_limit
/ 1000);
1414 limits
->core_power_limit
= (tdp
/ 8) * 1000;
1422 * ips_get_i915_syms - try to get GPU control methods from i915 driver
1425 * The i915 driver exports several interfaces to allow the IPS driver to
1426 * monitor and control graphics turbo mode. If we can find them, we can
1427 * enable graphics turbo, otherwise we must disable it to avoid exceeding
1428 * thermal and power limits in the MCP.
1430 static bool ips_get_i915_syms(struct ips_driver
*ips
)
1432 ips
->read_mch_val
= symbol_get(i915_read_mch_val
);
1433 if (!ips
->read_mch_val
)
1435 ips
->gpu_raise
= symbol_get(i915_gpu_raise
);
1436 if (!ips
->gpu_raise
)
1438 ips
->gpu_lower
= symbol_get(i915_gpu_lower
);
1439 if (!ips
->gpu_lower
)
1441 ips
->gpu_busy
= symbol_get(i915_gpu_busy
);
1444 ips
->gpu_turbo_disable
= symbol_get(i915_gpu_turbo_disable
);
1445 if (!ips
->gpu_turbo_disable
)
1451 symbol_put(i915_gpu_busy
);
1453 symbol_put(i915_gpu_lower
);
1455 symbol_put(i915_gpu_raise
);
1457 symbol_put(i915_read_mch_val
);
1463 ips_gpu_turbo_enabled(struct ips_driver
*ips
)
1465 if (!ips
->gpu_busy
&& late_i915_load
) {
1466 if (ips_get_i915_syms(ips
)) {
1467 dev_info(&ips
->dev
->dev
,
1468 "i915 driver attached, reenabling gpu turbo\n");
1469 ips
->gpu_turbo_enabled
= !(thm_readl(THM_HTS
) & HTS_GTD_DIS
);
1473 return ips
->gpu_turbo_enabled
;
1477 ips_link_to_i915_driver(void)
1479 /* We can't cleanly get at the various ips_driver structs from
1480 * this caller (the i915 driver), so just set a flag saying
1481 * that it's time to try getting the symbols again.
1483 late_i915_load
= true;
1485 EXPORT_SYMBOL_GPL(ips_link_to_i915_driver
);
1487 static DEFINE_PCI_DEVICE_TABLE(ips_id_table
) = {
1488 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
,
1489 PCI_DEVICE_ID_INTEL_THERMAL_SENSOR
), },
1493 MODULE_DEVICE_TABLE(pci
, ips_id_table
);
1495 static int ips_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1498 struct ips_driver
*ips
;
1501 u16 htshi
, trc
, trc_required_mask
;
1504 ips
= kzalloc(sizeof(struct ips_driver
), GFP_KERNEL
);
1508 pci_set_drvdata(dev
, ips
);
1511 ips
->limits
= ips_detect_cpu(ips
);
1513 dev_info(&dev
->dev
, "IPS not supported on this CPU\n");
1518 spin_lock_init(&ips
->turbo_status_lock
);
1520 ret
= pci_enable_device(dev
);
1522 dev_err(&dev
->dev
, "can't enable PCI device, aborting\n");
1526 if (!pci_resource_start(dev
, 0)) {
1527 dev_err(&dev
->dev
, "TBAR not assigned, aborting\n");
1532 ret
= pci_request_regions(dev
, "ips thermal sensor");
1534 dev_err(&dev
->dev
, "thermal resource busy, aborting\n");
1539 ips
->regmap
= ioremap(pci_resource_start(dev
, 0),
1540 pci_resource_len(dev
, 0));
1542 dev_err(&dev
->dev
, "failed to map thermal regs, aborting\n");
1547 tse
= thm_readb(THM_TSE
);
1548 if (tse
!= TSE_EN
) {
1549 dev_err(&dev
->dev
, "thermal device not enabled (0x%02x), aborting\n", tse
);
1554 trc
= thm_readw(THM_TRC
);
1555 trc_required_mask
= TRC_CORE1_EN
| TRC_CORE_PWR
| TRC_MCH_EN
;
1556 if ((trc
& trc_required_mask
) != trc_required_mask
) {
1557 dev_err(&dev
->dev
, "thermal reporting for required devices not enabled, aborting\n");
1562 if (trc
& TRC_CORE2_EN
)
1563 ips
->second_cpu
= true;
1565 update_turbo_limits(ips
);
1566 dev_dbg(&dev
->dev
, "max cpu power clamp: %dW\n",
1567 ips
->mcp_power_limit
/ 10);
1568 dev_dbg(&dev
->dev
, "max core power clamp: %dW\n",
1569 ips
->core_power_limit
/ 10);
1570 /* BIOS may update limits at runtime */
1571 if (thm_readl(THM_PSC
) & PSP_PBRT
)
1572 ips
->poll_turbo_status
= true;
1574 if (!ips_get_i915_syms(ips
)) {
1575 dev_err(&dev
->dev
, "failed to get i915 symbols, graphics turbo disabled\n");
1576 ips
->gpu_turbo_enabled
= false;
1578 dev_dbg(&dev
->dev
, "graphics turbo enabled\n");
1579 ips
->gpu_turbo_enabled
= true;
1583 * Check PLATFORM_INFO MSR to make sure this chip is
1586 rdmsrl(PLATFORM_INFO
, platform_info
);
1587 if (!(platform_info
& PLATFORM_TDP
)) {
1588 dev_err(&dev
->dev
, "platform indicates TDP override unavailable, aborting\n");
1594 * IRQ handler for ME interaction
1595 * Note: don't use MSI here as the PCH has bugs.
1597 pci_disable_msi(dev
);
1598 ret
= request_irq(dev
->irq
, ips_irq_handler
, IRQF_SHARED
, "ips",
1601 dev_err(&dev
->dev
, "request irq failed, aborting\n");
1605 /* Enable aux, hot & critical interrupts */
1606 thm_writeb(THM_TSPIEN
, TSPIEN_AUX2_LOHI
| TSPIEN_CRIT_LOHI
|
1607 TSPIEN_HOT_LOHI
| TSPIEN_AUX_LOHI
);
1608 thm_writeb(THM_TEN
, TEN_UPDATE_EN
);
1610 /* Collect adjustment values */
1611 ips
->cta_val
= thm_readw(THM_CTA
);
1612 ips
->pta_val
= thm_readw(THM_PTA
);
1613 ips
->mgta_val
= thm_readw(THM_MGTA
);
1615 /* Save turbo limits & ratios */
1616 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, ips
->orig_turbo_limit
);
1618 ips_disable_cpu_turbo(ips
);
1619 ips
->cpu_turbo_enabled
= false;
1621 /* Create thermal adjust thread */
1622 ips
->adjust
= kthread_create(ips_adjust
, ips
, "ips-adjust");
1623 if (IS_ERR(ips
->adjust
)) {
1625 "failed to create thermal adjust thread, aborting\n");
1627 goto error_free_irq
;
1632 * Set up the work queue and monitor thread. The monitor thread
1633 * will wake up ips_adjust thread.
1635 ips
->monitor
= kthread_run(ips_monitor
, ips
, "ips-monitor");
1636 if (IS_ERR(ips
->monitor
)) {
1638 "failed to create thermal monitor thread, aborting\n");
1640 goto error_thread_cleanup
;
1643 hts
= (ips
->core_power_limit
<< HTS_PCPL_SHIFT
) |
1644 (ips
->mcp_temp_limit
<< HTS_PTL_SHIFT
) | HTS_NVV
;
1645 htshi
= HTS2_PRST_RUNNING
<< HTS2_PRST_SHIFT
;
1647 thm_writew(THM_HTSHI
, htshi
);
1648 thm_writel(THM_HTS
, hts
);
1650 ips_debugfs_init(ips
);
1652 dev_info(&dev
->dev
, "IPS driver initialized, MCP temp limit %d\n",
1653 ips
->mcp_temp_limit
);
1656 error_thread_cleanup
:
1657 kthread_stop(ips
->adjust
);
1659 free_irq(ips
->dev
->irq
, ips
);
1661 iounmap(ips
->regmap
);
1663 pci_release_regions(dev
);
1669 static void ips_remove(struct pci_dev
*dev
)
1671 struct ips_driver
*ips
= pci_get_drvdata(dev
);
1677 ips_debugfs_cleanup(ips
);
1679 /* Release i915 driver */
1680 if (ips
->read_mch_val
)
1681 symbol_put(i915_read_mch_val
);
1683 symbol_put(i915_gpu_raise
);
1685 symbol_put(i915_gpu_lower
);
1687 symbol_put(i915_gpu_busy
);
1688 if (ips
->gpu_turbo_disable
)
1689 symbol_put(i915_gpu_turbo_disable
);
1691 rdmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
1692 turbo_override
&= ~(TURBO_TDC_OVR_EN
| TURBO_TDP_OVR_EN
);
1693 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, turbo_override
);
1694 wrmsrl(TURBO_POWER_CURRENT_LIMIT
, ips
->orig_turbo_limit
);
1696 free_irq(ips
->dev
->irq
, ips
);
1698 kthread_stop(ips
->adjust
);
1700 kthread_stop(ips
->monitor
);
1701 iounmap(ips
->regmap
);
1702 pci_release_regions(dev
);
1704 dev_dbg(&dev
->dev
, "IPS driver removed\n");
1708 static int ips_suspend(struct pci_dev
*dev
, pm_message_t state
)
1713 static int ips_resume(struct pci_dev
*dev
)
1718 #define ips_suspend NULL
1719 #define ips_resume NULL
1720 #endif /* CONFIG_PM */
1722 static void ips_shutdown(struct pci_dev
*dev
)
1726 static struct pci_driver ips_pci_driver
= {
1727 .name
= "intel ips",
1728 .id_table
= ips_id_table
,
1730 .remove
= ips_remove
,
1731 .suspend
= ips_suspend
,
1732 .resume
= ips_resume
,
1733 .shutdown
= ips_shutdown
,
1736 static int __init
ips_init(void)
1738 return pci_register_driver(&ips_pci_driver
);
1740 module_init(ips_init
);
1742 static void ips_exit(void)
1744 pci_unregister_driver(&ips_pci_driver
);
1747 module_exit(ips_exit
);
1749 MODULE_LICENSE("GPL");
1750 MODULE_AUTHOR("Jesse Barnes <jbarnes@virtuousgeek.org>");
1751 MODULE_DESCRIPTION("Intelligent Power Sharing Driver");