arch/arm/mach-tegra/timer.c

   1 /*
   2  * arch/arch/mach-tegra/timer.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  *
   6  * Author:
   7  *      Colin Cross <ccross@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/err.h>
  22 #include <linux/sched.h>
  23 #include <linux/time.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/clockchips.h>
  27 #include <linux/clocksource.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30
  31 #include <asm/mach/time.h>
  32 #include <asm/localtimer.h>
  33 #include <asm/sched_clock.h>
  34
  35 #include <mach/iomap.h>
  36 #include <mach/irqs.h>
  37 #include <mach/suspend.h>
  38
  39 #include "board.h"
  40 #include "clock.h"
  41
  42 #define RTC_SECONDS            0x08
  43 #define RTC_SHADOW_SECONDS     0x0c
  44 #define RTC_MILLISECONDS       0x10
  45
  46 #define TIMERUS_CNTR_1US 0x10
  47 #define TIMERUS_USEC_CFG 0x14
  48 #define TIMERUS_CNTR_FREEZE 0x4c
  49
  50 #define TIMER1_BASE 0x0
  51 #define TIMER2_BASE 0x8
  52 #define TIMER3_BASE 0x50
  53 #define TIMER4_BASE 0x58
  54
  55 #define TIMER_PTV 0x0
  56 #define TIMER_PCR 0x4
  57
  58 static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
  59 static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE);
  60
  61 static struct timespec persistent_ts;
  62 static u64 persistent_ms, last_persistent_ms;
  63
  64 #define timer_writel(value, reg) \
  65         __raw_writel(value, (u32)timer_reg_base + (reg))
  66 #define timer_readl(reg) \
  67         __raw_readl((u32)timer_reg_base + (reg))
  68
  69 static int tegra_timer_set_next_event(unsigned long cycles,
  70                                          struct clock_event_device *evt)
  71 {
  72         u32 reg;
  73
  74         reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
  75         timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  76
  77         return 0;
  78 }
  79
  80 static void tegra_timer_set_mode(enum clock_event_mode mode,
  81                                     struct clock_event_device *evt)
  82 {
  83         u32 reg;
  84
  85         timer_writel(0, TIMER3_BASE + TIMER_PTV);
  86
  87         switch (mode) {
  88         case CLOCK_EVT_MODE_PERIODIC:
  89                 reg = 0xC0000000 | ((1000000/HZ)-1);
  90                 timer_writel(reg, TIMER3_BASE + TIMER_PTV);
  91                 break;
  92         case CLOCK_EVT_MODE_ONESHOT:
  93                 break;
  94         case CLOCK_EVT_MODE_UNUSED:
  95         case CLOCK_EVT_MODE_SHUTDOWN:
  96         case CLOCK_EVT_MODE_RESUME:
  97                 break;
  98         }
  99 }
 100
 101 static cycle_t tegra_clocksource_read(struct clocksource *cs)
 102 {
 103         return timer_readl(TIMERUS_CNTR_1US);
 104 }
 105
 106 static struct clock_event_device tegra_clockevent = {
 107         .name           = "timer0",
 108         .rating         = 300,
 109         .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
 110         .set_next_event = tegra_timer_set_next_event,
 111         .set_mode       = tegra_timer_set_mode,
 112 };
 113
 114 static struct clocksource tegra_clocksource = {
 115         .name   = "timer_us",
 116         .rating = 300,
 117         .read   = tegra_clocksource_read,
 118         .mask   = CLOCKSOURCE_MASK(32),
 119         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 120 };
 121
 122 static DEFINE_CLOCK_DATA(cd);
 123
 124 /*
 125  * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60).
 126  * This gives a resolution of about 1us and a wrap period of about 1h11min.
 127  */
 128 #define SC_MULT         4194304000u
 129 #define SC_SHIFT        22
 130
 131 unsigned long long notrace sched_clock(void)
 132 {
 133         u32 cyc = timer_readl(TIMERUS_CNTR_1US);
 134         return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
 135 }
 136
 137 static void notrace tegra_update_sched_clock(void)
 138 {
 139         u32 cyc = timer_readl(TIMERUS_CNTR_1US);
 140         update_sched_clock(&cd, cyc, (u32)~0);
 141 }
 142
 143 /*
 144  * tegra_rtc_read - Reads the Tegra RTC registers
 145  * Care must be taken that this funciton is not called while the
 146  * tegra_rtc driver could be executing to avoid race conditions
 147  * on the RTC shadow register
 148  */
 149 u64 tegra_rtc_read_ms(void)
 150 {
 151         u32 ms = readl(rtc_base + RTC_MILLISECONDS);
 152         u32 s = readl(rtc_base + RTC_SHADOW_SECONDS);
 153         return (u64)s * MSEC_PER_SEC + ms;
 154 }
 155
 156 /*
 157  * read_persistent_clock -  Return time from a persistent clock.
 158  *
 159  * Reads the time from a source which isn't disabled during PM, the
 160  * 32k sync timer.  Convert the cycles elapsed since last read into
 161  * nsecs and adds to a monotonically increasing timespec.
 162  * Care must be taken that this funciton is not called while the
 163  * tegra_rtc driver could be executing to avoid race conditions
 164  * on the RTC shadow register
 165  */
 166 void read_persistent_clock(struct timespec *ts)
 167 {
 168         u64 delta;
 169         struct timespec *tsp = &persistent_ts;
 170
 171         last_persistent_ms = persistent_ms;
 172         persistent_ms = tegra_rtc_read_ms();
 173         delta = persistent_ms - last_persistent_ms;
 174
 175         timespec_add_ns(tsp, delta * NSEC_PER_MSEC);
 176         *ts = *tsp;
 177 }
 178
 179 static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
 180 {
 181         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 182         timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
 183         evt->event_handler(evt);
 184         return IRQ_HANDLED;
 185 }
 186
 187 static struct irqaction tegra_timer_irq = {
 188         .name           = "timer0",
 189         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
 190         .handler        = tegra_timer_interrupt,
 191         .dev_id         = &tegra_clockevent,
 192         .irq            = INT_TMR3,
 193 };
 194
 195 static void __init tegra_init_timer(void)
 196 {
 197         struct clk *clk;
 198         unsigned long rate = clk_measure_input_freq();
 199         int ret;
 200
 201         clk = clk_get_sys("timer", NULL);
 202         BUG_ON(IS_ERR(clk));
 203         clk_enable(clk);
 204
 205         /*
 206          * rtc registers are used by read_persistent_clock, keep the rtc clock
 207          * enabled
 208          */
 209         clk = clk_get_sys("rtc-tegra", NULL);
 210         BUG_ON(IS_ERR(clk));
 211         clk_enable(clk);
 212
 213 #ifdef CONFIG_HAVE_ARM_TWD
 214         twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
 215 #endif
 216
 217         switch (rate) {
 218         case 12000000:
 219                 timer_writel(0x000b, TIMERUS_USEC_CFG);
 220                 break;
 221         case 13000000:
 222                 timer_writel(0x000c, TIMERUS_USEC_CFG);
 223                 break;
 224         case 19200000:
 225                 timer_writel(0x045f, TIMERUS_USEC_CFG);
 226                 break;
 227         case 26000000:
 228                 timer_writel(0x0019, TIMERUS_USEC_CFG);
 229                 break;
 230         default:
 231                 WARN(1, "Unknown clock rate");
 232         }
 233
 234         init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
 235                                1000000, SC_MULT, SC_SHIFT);
 236
 237         if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
 238                 printk(KERN_ERR "Failed to register clocksource\n");
 239                 BUG();
 240         }
 241
 242         ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
 243         if (ret) {
 244                 printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
 245                 BUG();
 246         }
 247
 248         clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
 249         tegra_clockevent.max_delta_ns =
 250                 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
 251         tegra_clockevent.min_delta_ns =
 252                 clockevent_delta2ns(0x1, &tegra_clockevent);
 253         tegra_clockevent.cpumask = cpu_all_mask;
 254         tegra_clockevent.irq = tegra_timer_irq.irq;
 255         clockevents_register_device(&tegra_clockevent);
 256 }
 257
 258 struct sys_timer tegra_timer = {
 259         .init = tegra_init_timer,
 260 };
 261
 262 #ifdef CONFIG_PM
 263 static u32 usec_config;
 264
 265 void tegra_timer_suspend(void)
 266 {
 267         usec_config = timer_readl(TIMERUS_USEC_CFG);
 268 }
 269
 270 void tegra_timer_resume(void)
 271 {
 272         timer_writel(usec_config, TIMERUS_USEC_CFG);
 273 }
 274 #endif