drivers/staging/rtl8192e/r8192E_phy.h

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * This program is distributed in the hope that it will be useful, but WITHOUT
   5  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   6  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   7  * more details.
   8  *
   9  * You should have received a copy of the GNU General Public License along with
  10  * this program; if not, write to the Free Software Foundation, Inc.,
  11  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  12  *
  13  * The full GNU General Public License is included in this distribution in the
  14  * file called LICENSE.
  15  *
  16  * Contact Information:
  17  * wlanfae <wlanfae@realtek.com>
  18 ******************************************************************************/
  19 #ifndef _R819XU_PHY_H
  20 #define _R819XU_PHY_H
  21
  22 #define MAX_DOZE_WAITING_TIMES_9x 64
  23
  24 #define MAX_PRECMD_CNT 16
  25 #define MAX_RFDEPENDCMD_CNT 16
  26 #define MAX_POSTCMD_CNT 16
  27
  28 #ifdef RTL8190P
  29 #define AGCTAB_ArrayLength                              AGCTAB_ArrayLengthPci
  30 #define MACPHY_ArrayLength                              MACPHY_ArrayLengthPci
  31 #define RadioA_ArrayLength                              RadioA_ArrayLengthPci
  32 #define RadioB_ArrayLength                              RadioB_ArrayLengthPci
  33 #define MACPHY_Array_PGLength                   MACPHY_Array_PGLengthPci
  34 #define RadioC_ArrayLength                              RadioC_ArrayLengthPci
  35 #define RadioD_ArrayLength                              RadioD_ArrayLengthPci
  36 #define PHY_REGArrayLength                              PHY_REGArrayLengthPci
  37 #define PHY_REG_1T2RArrayLength                         PHY_REG_1T2RArrayLengthPci
  38
  39 #define Rtl819XMACPHY_Array_PG                  Rtl8190PciMACPHY_Array_PG
  40 #define Rtl819XMACPHY_Array                             Rtl8190PciMACPHY_Array
  41 #define Rtl819XRadioA_Array                                     Rtl8190PciRadioA_Array
  42 #define Rtl819XRadioB_Array                                     Rtl8190PciRadioB_Array
  43 #define Rtl819XRadioC_Array                                     Rtl8190PciRadioC_Array
  44 #define Rtl819XRadioD_Array                                     Rtl8190PciRadioD_Array
  45 #define Rtl819XAGCTAB_Array                             Rtl8190PciAGCTAB_Array
  46 #define Rtl819XPHY_REGArray                             Rtl8190PciPHY_REGArray
  47 #define Rtl819XPHY_REG_1T2RArray                Rtl8190PciPHY_REG_1T2RArray
  48 #endif
  49
  50 #ifdef RTL8192E
  51 #define AGCTAB_ArrayLength                              AGCTAB_ArrayLengthPciE
  52 #define MACPHY_ArrayLength                              MACPHY_ArrayLengthPciE
  53 #define RadioA_ArrayLength                              RadioA_ArrayLengthPciE
  54 #define RadioB_ArrayLength                              RadioB_ArrayLengthPciE
  55 #define MACPHY_Array_PGLength                   MACPHY_Array_PGLengthPciE
  56 #define RadioC_ArrayLength                              RadioC_ArrayLengthPciE
  57 #define RadioD_ArrayLength                              RadioD_ArrayLengthPciE
  58 #define PHY_REGArrayLength                              PHY_REGArrayLengthPciE
  59 #define PHY_REG_1T2RArrayLength                         PHY_REG_1T2RArrayLengthPciE
  60
  61 #define Rtl819XMACPHY_Array_PG                  Rtl8192PciEMACPHY_Array_PG
  62 #define Rtl819XMACPHY_Array                             Rtl8192PciEMACPHY_Array
  63 #define Rtl819XRadioA_Array                             Rtl8192PciERadioA_Array
  64 #define Rtl819XRadioB_Array                             Rtl8192PciERadioB_Array
  65 #define Rtl819XRadioC_Array                             Rtl8192PciERadioC_Array
  66 #define Rtl819XRadioD_Array                             Rtl8192PciERadioD_Array
  67 #define Rtl819XAGCTAB_Array                             Rtl8192PciEAGCTAB_Array
  68 #define Rtl819XPHY_REGArray                             Rtl8192PciEPHY_REGArray
  69 #define Rtl819XPHY_REG_1T2RArray                        Rtl8192PciEPHY_REG_1T2RArray
  70 #endif
  71
  72
  73
  74 typedef enum _SwChnlCmdID{
  75         CmdID_End,
  76         CmdID_SetTxPowerLevel,
  77         CmdID_BBRegWrite10,
  78         CmdID_WritePortUlong,
  79         CmdID_WritePortUshort,
  80         CmdID_WritePortUchar,
  81         CmdID_RF_WriteReg,
  82 }SwChnlCmdID;
  83
  84 /*--------------------------------Define structure--------------------------------*/
  85 typedef struct _SwChnlCmd{
  86         SwChnlCmdID     CmdID;
  87         u32                     Para1;
  88         u32                     Para2;
  89         u32                     msDelay;
  90 }__attribute__ ((packed)) SwChnlCmd;
  91
  92 extern u32 rtl819XMACPHY_Array_PG[];
  93 extern u32 rtl819XPHY_REG_1T2RArray[];
  94 extern u32 rtl819XAGCTAB_Array[];
  95 extern u32 rtl819XRadioA_Array[];
  96 extern u32 rtl819XRadioB_Array[];
  97 extern u32 rtl819XRadioC_Array[];
  98 extern u32 rtl819XRadioD_Array[];
  99
 100 typedef enum _HW90_BLOCK{
 101         HW90_BLOCK_MAC = 0,
 102         HW90_BLOCK_PHY0 = 1,
 103         HW90_BLOCK_PHY1 = 2,
 104         HW90_BLOCK_RF = 3,
 105         HW90_BLOCK_MAXIMUM = 4,
 106 }HW90_BLOCK_E, *PHW90_BLOCK_E;
 107
 108 typedef enum _RF90_RADIO_PATH{
 109         RF90_PATH_A = 0,
 110         RF90_PATH_B = 1,
 111         RF90_PATH_C = 2,
 112         RF90_PATH_D = 3,
 113         RF90_PATH_MAX
 114 }RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
 115
 116 #define bMaskByte0                0xff
 117 #define bMaskByte1                0xff00
 118 #define bMaskByte2                0xff0000
 119 #define bMaskByte3                0xff000000
 120 #define bMaskHWord                0xffff0000
 121 #define bMaskLWord                0x0000ffff
 122 #define bMaskDWord                0xffffffff
 123
 124 extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath);
 125 extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData);
 126 extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask);
 127 extern void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data);
 128 extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
 129 extern void rtl8192_phy_configmac(struct net_device* dev);
 130 extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType);
 131 extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
 132 extern bool rtl8192_BBConfig(struct net_device* dev);
 133 extern void rtl8192_phy_getTxPower(struct net_device* dev);
 134 extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel);
 135 extern bool rtl8192_phy_RFConfig(struct net_device* dev);
 136 extern void rtl8192_phy_updateInitGain(struct net_device* dev);
 137 extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E  eRFPath);
 138
 139 extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel);
 140 extern void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH  Bandwidth, HT_EXTCHNL_OFFSET Offset);
 141 extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
 142 extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
 143 extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
 144
 145 #if defined RTL8190P
 146 extern  void
 147 PHY_SetRtl8190pRfOff(struct net_device* dev     );
 148 #endif
 149
 150 #if defined RTL8192E
 151 extern  void
 152 PHY_SetRtl8192eRfOff(struct net_device* dev     );
 153 #endif
 154
 155 bool
 156 SetRFPowerState(
 157         struct net_device* dev,
 158         RT_RF_POWER_STATE       eRFPowerState
 159         );
 160 #define PHY_SetRFPowerState SetRFPowerState
 161
 162 extern void PHY_ScanOperationBackup8192(struct net_device* dev,u8 Operation);
 163
 164 #endif