2 * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #define MMCIPOWER 0x000
11 #define MCI_PWR_OFF 0x00
12 #define MCI_PWR_UP 0x02
13 #define MCI_PWR_ON 0x03
14 #define MCI_DATA2DIREN (1 << 2)
15 #define MCI_CMDDIREN (1 << 3)
16 #define MCI_DATA0DIREN (1 << 4)
17 #define MCI_DATA31DIREN (1 << 5)
18 #define MCI_OD (1 << 6)
19 #define MCI_ROD (1 << 7)
20 /* The ST Micro version does not have ROD */
21 #define MCI_FBCLKEN (1 << 7)
22 #define MCI_DATA74DIREN (1 << 8)
24 #define MMCICLOCK 0x004
25 #define MCI_CLK_ENABLE (1 << 8)
26 #define MCI_CLK_PWRSAVE (1 << 9)
27 #define MCI_CLK_BYPASS (1 << 10)
28 #define MCI_4BIT_BUS (1 << 11)
29 /* 8bit wide buses supported in ST Micro versions */
30 #define MCI_ST_8BIT_BUS (1 << 12)
32 #define MMCIARGUMENT 0x008
33 #define MMCICOMMAND 0x00c
34 #define MCI_CPSM_RESPONSE (1 << 6)
35 #define MCI_CPSM_LONGRSP (1 << 7)
36 #define MCI_CPSM_INTERRUPT (1 << 8)
37 #define MCI_CPSM_PENDING (1 << 9)
38 #define MCI_CPSM_ENABLE (1 << 10)
39 #define MCI_SDIO_SUSP (1 << 11)
40 #define MCI_ENCMD_COMPL (1 << 12)
41 #define MCI_NIEN (1 << 13)
42 #define MCI_CE_ATACMD (1 << 14)
44 #define MMCIRESPCMD 0x010
45 #define MMCIRESPONSE0 0x014
46 #define MMCIRESPONSE1 0x018
47 #define MMCIRESPONSE2 0x01c
48 #define MMCIRESPONSE3 0x020
49 #define MMCIDATATIMER 0x024
50 #define MMCIDATALENGTH 0x028
51 #define MMCIDATACTRL 0x02c
52 #define MCI_DPSM_ENABLE (1 << 0)
53 #define MCI_DPSM_DIRECTION (1 << 1)
54 #define MCI_DPSM_MODE (1 << 2)
55 #define MCI_DPSM_DMAENABLE (1 << 3)
56 #define MCI_DPSM_BLOCKSIZE (1 << 4)
57 /* Control register extensions in the ST Micro U300 and Ux500 versions */
58 #define MCI_ST_DPSM_RWSTART (1 << 8)
59 #define MCI_ST_DPSM_RWSTOP (1 << 9)
60 #define MCI_ST_DPSM_RWMOD (1 << 10)
61 #define MCI_ST_DPSM_SDIOEN (1 << 11)
62 /* Control register extensions in the ST Micro Ux500 versions */
63 #define MCI_ST_DPSM_DMAREQCTL (1 << 12)
64 #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
65 #define MCI_ST_DPSM_BUSYMODE (1 << 14)
66 #define MCI_ST_DPSM_DDRMODE (1 << 15)
68 #define MMCIDATACNT 0x030
69 #define MMCISTATUS 0x034
70 #define MCI_CMDCRCFAIL (1 << 0)
71 #define MCI_DATACRCFAIL (1 << 1)
72 #define MCI_CMDTIMEOUT (1 << 2)
73 #define MCI_DATATIMEOUT (1 << 3)
74 #define MCI_TXUNDERRUN (1 << 4)
75 #define MCI_RXOVERRUN (1 << 5)
76 #define MCI_CMDRESPEND (1 << 6)
77 #define MCI_CMDSENT (1 << 7)
78 #define MCI_DATAEND (1 << 8)
79 #define MCI_DATABLOCKEND (1 << 10)
80 #define MCI_CMDACTIVE (1 << 11)
81 #define MCI_TXACTIVE (1 << 12)
82 #define MCI_RXACTIVE (1 << 13)
83 #define MCI_TXFIFOHALFEMPTY (1 << 14)
84 #define MCI_RXFIFOHALFFULL (1 << 15)
85 #define MCI_TXFIFOFULL (1 << 16)
86 #define MCI_RXFIFOFULL (1 << 17)
87 #define MCI_TXFIFOEMPTY (1 << 18)
88 #define MCI_RXFIFOEMPTY (1 << 19)
89 #define MCI_TXDATAAVLBL (1 << 20)
90 #define MCI_RXDATAAVLBL (1 << 21)
91 #define MCI_SDIOIT (1 << 22)
92 #define MCI_CEATAEND (1 << 23)
94 #define MMCICLEAR 0x038
95 #define MCI_CMDCRCFAILCLR (1 << 0)
96 #define MCI_DATACRCFAILCLR (1 << 1)
97 #define MCI_CMDTIMEOUTCLR (1 << 2)
98 #define MCI_DATATIMEOUTCLR (1 << 3)
99 #define MCI_TXUNDERRUNCLR (1 << 4)
100 #define MCI_RXOVERRUNCLR (1 << 5)
101 #define MCI_CMDRESPENDCLR (1 << 6)
102 #define MCI_CMDSENTCLR (1 << 7)
103 #define MCI_DATAENDCLR (1 << 8)
104 #define MCI_DATABLOCKENDCLR (1 << 10)
105 #define MCI_SDIOITC (1 << 22)
106 #define MCI_CEATAENDC (1 << 23)
108 #define MMCIMASK0 0x03c
109 #define MCI_CMDCRCFAILMASK (1 << 0)
110 #define MCI_DATACRCFAILMASK (1 << 1)
111 #define MCI_CMDTIMEOUTMASK (1 << 2)
112 #define MCI_DATATIMEOUTMASK (1 << 3)
113 #define MCI_TXUNDERRUNMASK (1 << 4)
114 #define MCI_RXOVERRUNMASK (1 << 5)
115 #define MCI_CMDRESPENDMASK (1 << 6)
116 #define MCI_CMDSENTMASK (1 << 7)
117 #define MCI_DATAENDMASK (1 << 8)
118 #define MCI_DATABLOCKENDMASK (1 << 10)
119 #define MCI_CMDACTIVEMASK (1 << 11)
120 #define MCI_TXACTIVEMASK (1 << 12)
121 #define MCI_RXACTIVEMASK (1 << 13)
122 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
123 #define MCI_RXFIFOHALFFULLMASK (1 << 15)
124 #define MCI_TXFIFOFULLMASK (1 << 16)
125 #define MCI_RXFIFOFULLMASK (1 << 17)
126 #define MCI_TXFIFOEMPTYMASK (1 << 18)
127 #define MCI_RXFIFOEMPTYMASK (1 << 19)
128 #define MCI_TXDATAAVLBLMASK (1 << 20)
129 #define MCI_RXDATAAVLBLMASK (1 << 21)
130 #define MCI_SDIOITMASK (1 << 22)
131 #define MCI_CEATAENDMASK (1 << 23)
133 #define MMCIMASK1 0x040
134 #define MMCIFIFOCNT 0x048
135 #define MMCIFIFO 0x080 /* to 0x0bc */
137 #define MCI_IRQENABLE \
138 (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
139 MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
140 MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
149 struct mmc_request
*mrq
;
150 struct mmc_command
*cmd
;
151 struct mmc_data
*data
;
152 struct mmc_host
*mmc
;
158 unsigned int data_xfered
;
165 struct mmci_platform_data
*plat
;
166 struct variant_data
*variant
;
171 struct timer_list timer
;
172 unsigned int oldstat
;
175 struct sg_mapping_iter sg_miter
;
177 struct regulator
*vcc
;