?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
dt/net: Eliminate users of of_platform_{,un}register_driver
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / gianfar.c
blobccb231c4d9334bbe49336eeee5f8491e0c8e321b
1 /*
2 * drivers/net/gianfar.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 *
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * Copyright 2007 MontaVista Software, Inc.
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the
18 * Free Software Foundation; either version 2 of the License, or (at your
19 * option) any later version.
20 *
21 * Gianfar: AKA Lambda Draconis, "Dragon"
22 * RA 11 31 24.2
23 * Dec +69 19 52
24 * V 3.84
25 * B-V +1.62
26 *
27 * Theory of operation
28 *
29 * The driver is initialized through of_device. Configuration information
30 * is therefore conveyed through an OF-style device tree.
31 *
32 * The Gianfar Ethernet Controller uses a ring of buffer
33 * descriptors. The beginning is indicated by a register
34 * pointing to the physical address of the start of the ring.
35 * The end is determined by a "wrap" bit being set in the
36 * last descriptor of the ring.
37 *
38 * When a packet is received, the RXF bit in the
39 * IEVENT register is set, triggering an interrupt when the
40 * corresponding bit in the IMASK register is also set (if
41 * interrupt coalescing is active, then the interrupt may not
42 * happen immediately, but will wait until either a set number
43 * of frames or amount of time have passed). In NAPI, the
44 * interrupt handler will signal there is work to be done, and
45 * exit. This method will start at the last known empty
46 * descriptor, and process every subsequent descriptor until there
47 * are none left with data (NAPI will stop after a set number of
48 * packets to give time to other tasks, but will eventually
49 * process all the packets). The data arrives inside a
50 * pre-allocated skb, and so after the skb is passed up to the
51 * stack, a new skb must be allocated, and the address field in
52 * the buffer descriptor must be updated to indicate this new
53 * skb.
54 *
55 * When the kernel requests that a packet be transmitted, the
56 * driver starts where it left off last time, and points the
57 * descriptor at the buffer which was passed in. The driver
58 * then informs the DMA engine that there are packets ready to
59 * be transmitted. Once the controller is finished transmitting
60 * the packet, an interrupt may be triggered (under the same
61 * conditions as for reception, but depending on the TXF bit).
62 * The driver then cleans up the buffer.
63 */
64
65 #include <linux/kernel.h>
66 #include <linux/string.h>
67 #include <linux/errno.h>
68 #include <linux/unistd.h>
69 #include <linux/slab.h>
70 #include <linux/interrupt.h>
71 #include <linux/init.h>
72 #include <linux/delay.h>
73 #include <linux/netdevice.h>
74 #include <linux/etherdevice.h>
75 #include <linux/skbuff.h>
76 #include <linux/if_vlan.h>
77 #include <linux/spinlock.h>
78 #include <linux/mm.h>
79 #include <linux/of_mdio.h>
80 #include <linux/of_platform.h>
81 #include <linux/ip.h>
82 #include <linux/tcp.h>
83 #include <linux/udp.h>
84 #include <linux/in.h>
85 #include <linux/net_tstamp.h>
86
87 #include <asm/io.h>
88 #include <asm/reg.h>
89 #include <asm/irq.h>
90 #include <asm/uaccess.h>
91 #include <linux/module.h>
92 #include <linux/dma-mapping.h>
93 #include <linux/crc32.h>
94 #include <linux/mii.h>
95 #include <linux/phy.h>
96 #include <linux/phy_fixed.h>
97 #include <linux/of.h>
98 #include <linux/of_net.h>
99
100 #include "gianfar.h"
101 #include "fsl_pq_mdio.h"
102
103 #define TX_TIMEOUT (1*HZ)
104 #undef BRIEF_GFAR_ERRORS
105 #undef VERBOSE_GFAR_ERRORS
106
107 const char gfar_driver_name[] = "Gianfar Ethernet";
108 const char gfar_driver_version[] = "1.3";
109
110 static int gfar_enet_open(struct net_device *dev);
111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
112 static void gfar_reset_task(struct work_struct *work);
113 static void gfar_timeout(struct net_device *dev);
114 static int gfar_close(struct net_device *dev);
115 struct sk_buff *gfar_new_skb(struct net_device *dev);
116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
117 struct sk_buff *skb);
118 static int gfar_set_mac_address(struct net_device *dev);
119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
120 static irqreturn_t gfar_error(int irq, void *dev_id);
121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
123 static void adjust_link(struct net_device *dev);
124 static void init_registers(struct net_device *dev);
125 static int init_phy(struct net_device *dev);
126 static int gfar_probe(struct platform_device *ofdev);
127 static int gfar_remove(struct platform_device *ofdev);
128 static void free_skb_resources(struct gfar_private *priv);
129 static void gfar_set_multi(struct net_device *dev);
130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
131 static void gfar_configure_serdes(struct net_device *dev);
132 static int gfar_poll(struct napi_struct *napi, int budget);
133 #ifdef CONFIG_NET_POLL_CONTROLLER
134 static void gfar_netpoll(struct net_device *dev);
135 #endif
136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
139 int amount_pull);
140 static void gfar_vlan_rx_register(struct net_device *netdev,
141 struct vlan_group *grp);
142 void gfar_halt(struct net_device *dev);
143 static void gfar_halt_nodisable(struct net_device *dev);
144 void gfar_start(struct net_device *dev);
145 static void gfar_clear_exact_match(struct net_device *dev);
146 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
147 const u8 *addr);
148 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
149
150 MODULE_AUTHOR("Freescale Semiconductor, Inc");
151 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
152 MODULE_LICENSE("GPL");
153
154 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
155 dma_addr_t buf)
156 {
157 u32 lstatus;
158
159 bdp->bufPtr = buf;
160
161 lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
162 if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
163 lstatus |= BD_LFLAG(RXBD_WRAP);
164
165 eieio();
166
167 bdp->lstatus = lstatus;
168 }
169
170 static int gfar_init_bds(struct net_device *ndev)
171 {
172 struct gfar_private *priv = netdev_priv(ndev);
173 struct gfar_priv_tx_q *tx_queue = NULL;
174 struct gfar_priv_rx_q *rx_queue = NULL;
175 struct txbd8 *txbdp;
176 struct rxbd8 *rxbdp;
177 int i, j;
178
179 for (i = 0; i < priv->num_tx_queues; i++) {
180 tx_queue = priv->tx_queue[i];
181 /* Initialize some variables in our dev structure */
182 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
183 tx_queue->dirty_tx = tx_queue->tx_bd_base;
184 tx_queue->cur_tx = tx_queue->tx_bd_base;
185 tx_queue->skb_curtx = 0;
186 tx_queue->skb_dirtytx = 0;
187
188 /* Initialize Transmit Descriptor Ring */
189 txbdp = tx_queue->tx_bd_base;
190 for (j = 0; j < tx_queue->tx_ring_size; j++) {
191 txbdp->lstatus = 0;
192 txbdp->bufPtr = 0;
193 txbdp++;
194 }
195
196 /* Set the last descriptor in the ring to indicate wrap */
197 txbdp--;
198 txbdp->status |= TXBD_WRAP;
199 }
200
201 for (i = 0; i < priv->num_rx_queues; i++) {
202 rx_queue = priv->rx_queue[i];
203 rx_queue->cur_rx = rx_queue->rx_bd_base;
204 rx_queue->skb_currx = 0;
205 rxbdp = rx_queue->rx_bd_base;
206
207 for (j = 0; j < rx_queue->rx_ring_size; j++) {
208 struct sk_buff *skb = rx_queue->rx_skbuff[j];
209
210 if (skb) {
211 gfar_init_rxbdp(rx_queue, rxbdp,
212 rxbdp->bufPtr);
213 } else {
214 skb = gfar_new_skb(ndev);
215 if (!skb) {
216 pr_err("%s: Can't allocate RX buffers\n",
217 ndev->name);
218 goto err_rxalloc_fail;
219 }
220 rx_queue->rx_skbuff[j] = skb;
221
222 gfar_new_rxbdp(rx_queue, rxbdp, skb);
223 }
224
225 rxbdp++;
226 }
227
228 }
229
230 return 0;
231
232 err_rxalloc_fail:
233 free_skb_resources(priv);
234 return -ENOMEM;
235 }
236
237 static int gfar_alloc_skb_resources(struct net_device *ndev)
238 {
239 void *vaddr;
240 dma_addr_t addr;
241 int i, j, k;
242 struct gfar_private *priv = netdev_priv(ndev);
243 struct device *dev = &priv->ofdev->dev;
244 struct gfar_priv_tx_q *tx_queue = NULL;
245 struct gfar_priv_rx_q *rx_queue = NULL;
246
247 priv->total_tx_ring_size = 0;
248 for (i = 0; i < priv->num_tx_queues; i++)
249 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
250
251 priv->total_rx_ring_size = 0;
252 for (i = 0; i < priv->num_rx_queues; i++)
253 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
254
255 /* Allocate memory for the buffer descriptors */
256 vaddr = dma_alloc_coherent(dev,
257 sizeof(struct txbd8) * priv->total_tx_ring_size +
258 sizeof(struct rxbd8) * priv->total_rx_ring_size,
259 &addr, GFP_KERNEL);
260 if (!vaddr) {
261 if (netif_msg_ifup(priv))
262 pr_err("%s: Could not allocate buffer descriptors!\n",
263 ndev->name);
264 return -ENOMEM;
265 }
266
267 for (i = 0; i < priv->num_tx_queues; i++) {
268 tx_queue = priv->tx_queue[i];
269 tx_queue->tx_bd_base = (struct txbd8 *) vaddr;
270 tx_queue->tx_bd_dma_base = addr;
271 tx_queue->dev = ndev;
272 /* enet DMA only understands physical addresses */
273 addr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
274 vaddr += sizeof(struct txbd8) *tx_queue->tx_ring_size;
275 }
276
277 /* Start the rx descriptor ring where the tx ring leaves off */
278 for (i = 0; i < priv->num_rx_queues; i++) {
279 rx_queue = priv->rx_queue[i];
280 rx_queue->rx_bd_base = (struct rxbd8 *) vaddr;
281 rx_queue->rx_bd_dma_base = addr;
282 rx_queue->dev = ndev;
283 addr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
284 vaddr += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
285 }
286
287 /* Setup the skbuff rings */
288 for (i = 0; i < priv->num_tx_queues; i++) {
289 tx_queue = priv->tx_queue[i];
290 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
291 tx_queue->tx_ring_size, GFP_KERNEL);
292 if (!tx_queue->tx_skbuff) {
293 if (netif_msg_ifup(priv))
294 pr_err("%s: Could not allocate tx_skbuff\n",
295 ndev->name);
296 goto cleanup;
297 }
298
299 for (k = 0; k < tx_queue->tx_ring_size; k++)
300 tx_queue->tx_skbuff[k] = NULL;
301 }
302
303 for (i = 0; i < priv->num_rx_queues; i++) {
304 rx_queue = priv->rx_queue[i];
305 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
306 rx_queue->rx_ring_size, GFP_KERNEL);
307
308 if (!rx_queue->rx_skbuff) {
309 if (netif_msg_ifup(priv))
310 pr_err("%s: Could not allocate rx_skbuff\n",
311 ndev->name);
312 goto cleanup;
313 }
314
315 for (j = 0; j < rx_queue->rx_ring_size; j++)
316 rx_queue->rx_skbuff[j] = NULL;
317 }
318
319 if (gfar_init_bds(ndev))
320 goto cleanup;
321
322 return 0;
323
324 cleanup:
325 free_skb_resources(priv);
326 return -ENOMEM;
327 }
328
329 static void gfar_init_tx_rx_base(struct gfar_private *priv)
330 {
331 struct gfar __iomem *regs = priv->gfargrp[0].regs;
332 u32 __iomem *baddr;
333 int i;
334
335 baddr = &regs->tbase0;
336 for(i = 0; i < priv->num_tx_queues; i++) {
337 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
338 baddr += 2;
339 }
340
341 baddr = &regs->rbase0;
342 for(i = 0; i < priv->num_rx_queues; i++) {
343 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
344 baddr += 2;
345 }
346 }
347
348 static void gfar_init_mac(struct net_device *ndev)
349 {
350 struct gfar_private *priv = netdev_priv(ndev);
351 struct gfar __iomem *regs = priv->gfargrp[0].regs;
352 u32 rctrl = 0;
353 u32 tctrl = 0;
354 u32 attrs = 0;
355
356 /* write the tx/rx base registers */
357 gfar_init_tx_rx_base(priv);
358
359 /* Configure the coalescing support */
360 gfar_configure_coalescing(priv, 0xFF, 0xFF);
361
362 if (priv->rx_filer_enable) {
363 rctrl |= RCTRL_FILREN;
364 /* Program the RIR0 reg with the required distribution */
365 gfar_write(&regs->rir0, DEFAULT_RIR0);
366 }
367
368 if (priv->rx_csum_enable)
369 rctrl |= RCTRL_CHECKSUMMING;
370
371 if (priv->extended_hash) {
372 rctrl |= RCTRL_EXTHASH;
373
374 gfar_clear_exact_match(ndev);
375 rctrl |= RCTRL_EMEN;
376 }
377
378 if (priv->padding) {
379 rctrl &= ~RCTRL_PAL_MASK;
380 rctrl |= RCTRL_PADDING(priv->padding);
381 }
382
383 /* Insert receive time stamps into padding alignment bytes */
384 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
385 rctrl &= ~RCTRL_PAL_MASK;
386 rctrl |= RCTRL_PADDING(8);
387 priv->padding = 8;
388 }
389
390 /* Enable HW time stamping if requested from user space */
391 if (priv->hwts_rx_en)
392 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
393
394 /* keep vlan related bits if it's enabled */
395 if (priv->vlgrp) {
396 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
397 tctrl |= TCTRL_VLINS;
398 }
399
400 /* Init rctrl based on our settings */
401 gfar_write(&regs->rctrl, rctrl);
402
403 if (ndev->features & NETIF_F_IP_CSUM)
404 tctrl |= TCTRL_INIT_CSUM;
405
406 tctrl |= TCTRL_TXSCHED_PRIO;
407
408 gfar_write(&regs->tctrl, tctrl);
409
410 /* Set the extraction length and index */
411 attrs = ATTRELI_EL(priv->rx_stash_size) |
412 ATTRELI_EI(priv->rx_stash_index);
413
414 gfar_write(&regs->attreli, attrs);
415
416 /* Start with defaults, and add stashing or locking
417 * depending on the approprate variables */
418 attrs = ATTR_INIT_SETTINGS;
419
420 if (priv->bd_stash_en)
421 attrs |= ATTR_BDSTASH;
422
423 if (priv->rx_stash_size != 0)
424 attrs |= ATTR_BUFSTASH;
425
426 gfar_write(&regs->attr, attrs);
427
428 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
429 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
430 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
431 }
432
433 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
434 {
435 struct gfar_private *priv = netdev_priv(dev);
436 unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
437 unsigned long tx_packets = 0, tx_bytes = 0;
438 int i = 0;
439
440 for (i = 0; i < priv->num_rx_queues; i++) {
441 rx_packets += priv->rx_queue[i]->stats.rx_packets;
442 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
443 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
444 }
445
446 dev->stats.rx_packets = rx_packets;
447 dev->stats.rx_bytes = rx_bytes;
448 dev->stats.rx_dropped = rx_dropped;
449
450 for (i = 0; i < priv->num_tx_queues; i++) {
451 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
452 tx_packets += priv->tx_queue[i]->stats.tx_packets;
453 }
454
455 dev->stats.tx_bytes = tx_bytes;
456 dev->stats.tx_packets = tx_packets;
457
458 return &dev->stats;
459 }
460
461 static const struct net_device_ops gfar_netdev_ops = {
462 .ndo_open = gfar_enet_open,
463 .ndo_start_xmit = gfar_start_xmit,
464 .ndo_stop = gfar_close,
465 .ndo_change_mtu = gfar_change_mtu,
466 .ndo_set_multicast_list = gfar_set_multi,
467 .ndo_tx_timeout = gfar_timeout,
468 .ndo_do_ioctl = gfar_ioctl,
469 .ndo_get_stats = gfar_get_stats,
470 .ndo_vlan_rx_register = gfar_vlan_rx_register,
471 .ndo_set_mac_address = eth_mac_addr,
472 .ndo_validate_addr = eth_validate_addr,
473 #ifdef CONFIG_NET_POLL_CONTROLLER
474 .ndo_poll_controller = gfar_netpoll,
475 #endif
476 };
477
478 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
479 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
480
481 void lock_rx_qs(struct gfar_private *priv)
482 {
483 int i = 0x0;
484
485 for (i = 0; i < priv->num_rx_queues; i++)
486 spin_lock(&priv->rx_queue[i]->rxlock);
487 }
488
489 void lock_tx_qs(struct gfar_private *priv)
490 {
491 int i = 0x0;
492
493 for (i = 0; i < priv->num_tx_queues; i++)
494 spin_lock(&priv->tx_queue[i]->txlock);
495 }
496
497 void unlock_rx_qs(struct gfar_private *priv)
498 {
499 int i = 0x0;
500
501 for (i = 0; i < priv->num_rx_queues; i++)
502 spin_unlock(&priv->rx_queue[i]->rxlock);
503 }
504
505 void unlock_tx_qs(struct gfar_private *priv)
506 {
507 int i = 0x0;
508
509 for (i = 0; i < priv->num_tx_queues; i++)
510 spin_unlock(&priv->tx_queue[i]->txlock);
511 }
512
513 /* Returns 1 if incoming frames use an FCB */
514 static inline int gfar_uses_fcb(struct gfar_private *priv)
515 {
516 return priv->vlgrp || priv->rx_csum_enable ||
517 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
518 }
519
520 static void free_tx_pointers(struct gfar_private *priv)
521 {
522 int i = 0;
523
524 for (i = 0; i < priv->num_tx_queues; i++)
525 kfree(priv->tx_queue[i]);
526 }
527
528 static void free_rx_pointers(struct gfar_private *priv)
529 {
530 int i = 0;
531
532 for (i = 0; i < priv->num_rx_queues; i++)
533 kfree(priv->rx_queue[i]);
534 }
535
536 static void unmap_group_regs(struct gfar_private *priv)
537 {
538 int i = 0;
539
540 for (i = 0; i < MAXGROUPS; i++)
541 if (priv->gfargrp[i].regs)
542 iounmap(priv->gfargrp[i].regs);
543 }
544
545 static void disable_napi(struct gfar_private *priv)
546 {
547 int i = 0;
548
549 for (i = 0; i < priv->num_grps; i++)
550 napi_disable(&priv->gfargrp[i].napi);
551 }
552
553 static void enable_napi(struct gfar_private *priv)
554 {
555 int i = 0;
556
557 for (i = 0; i < priv->num_grps; i++)
558 napi_enable(&priv->gfargrp[i].napi);
559 }
560
561 static int gfar_parse_group(struct device_node *np,
562 struct gfar_private *priv, const char *model)
563 {
564 u32 *queue_mask;
565
566 priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
567 if (!priv->gfargrp[priv->num_grps].regs)
568 return -ENOMEM;
569
570 priv->gfargrp[priv->num_grps].interruptTransmit =
571 irq_of_parse_and_map(np, 0);
572
573 /* If we aren't the FEC we have multiple interrupts */
574 if (model && strcasecmp(model, "FEC")) {
575 priv->gfargrp[priv->num_grps].interruptReceive =
576 irq_of_parse_and_map(np, 1);
577 priv->gfargrp[priv->num_grps].interruptError =
578 irq_of_parse_and_map(np,2);
579 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
580 priv->gfargrp[priv->num_grps].interruptReceive == NO_IRQ ||
581 priv->gfargrp[priv->num_grps].interruptError == NO_IRQ)
582 return -EINVAL;
583 }
584
585 priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
586 priv->gfargrp[priv->num_grps].priv = priv;
587 spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
588 if(priv->mode == MQ_MG_MODE) {
589 queue_mask = (u32 *)of_get_property(np,
590 "fsl,rx-bit-map", NULL);
591 priv->gfargrp[priv->num_grps].rx_bit_map =
592 queue_mask ? *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
593 queue_mask = (u32 *)of_get_property(np,
594 "fsl,tx-bit-map", NULL);
595 priv->gfargrp[priv->num_grps].tx_bit_map =
596 queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
597 } else {
598 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
599 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
600 }
601 priv->num_grps++;
602
603 return 0;
604 }
605
606 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
607 {
608 const char *model;
609 const char *ctype;
610 const void *mac_addr;
611 int err = 0, i;
612 struct net_device *dev = NULL;
613 struct gfar_private *priv = NULL;
614 struct device_node *np = ofdev->dev.of_node;
615 struct device_node *child = NULL;
616 const u32 *stash;
617 const u32 *stash_len;
618 const u32 *stash_idx;
619 unsigned int num_tx_qs, num_rx_qs;
620 u32 *tx_queues, *rx_queues;
621
622 if (!np || !of_device_is_available(np))
623 return -ENODEV;
624
625 /* parse the num of tx and rx queues */
626 tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
627 num_tx_qs = tx_queues ? *tx_queues : 1;
628
629 if (num_tx_qs > MAX_TX_QS) {
630 printk(KERN_ERR "num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
631 num_tx_qs, MAX_TX_QS);
632 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
633 return -EINVAL;
634 }
635
636 rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
637 num_rx_qs = rx_queues ? *rx_queues : 1;
638
639 if (num_rx_qs > MAX_RX_QS) {
640 printk(KERN_ERR "num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
641 num_tx_qs, MAX_TX_QS);
642 printk(KERN_ERR "Cannot do alloc_etherdev, aborting\n");
643 return -EINVAL;
644 }
645
646 *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
647 dev = *pdev;
648 if (NULL == dev)
649 return -ENOMEM;
650
651 priv = netdev_priv(dev);
652 priv->node = ofdev->dev.of_node;
653 priv->ndev = dev;
654
655 priv->num_tx_queues = num_tx_qs;
656 netif_set_real_num_rx_queues(dev, num_rx_qs);
657 priv->num_rx_queues = num_rx_qs;
658 priv->num_grps = 0x0;
659
660 model = of_get_property(np, "model", NULL);
661
662 for (i = 0; i < MAXGROUPS; i++)
663 priv->gfargrp[i].regs = NULL;
664
665 /* Parse and initialize group specific information */
666 if (of_device_is_compatible(np, "fsl,etsec2")) {
667 priv->mode = MQ_MG_MODE;
668 for_each_child_of_node(np, child) {
669 err = gfar_parse_group(child, priv, model);
670 if (err)
671 goto err_grp_init;
672 }
673 } else {
674 priv->mode = SQ_SG_MODE;
675 err = gfar_parse_group(np, priv, model);
676 if(err)
677 goto err_grp_init;
678 }
679
680 for (i = 0; i < priv->num_tx_queues; i++)
681 priv->tx_queue[i] = NULL;
682 for (i = 0; i < priv->num_rx_queues; i++)
683 priv->rx_queue[i] = NULL;
684
685 for (i = 0; i < priv->num_tx_queues; i++) {
686 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
687 GFP_KERNEL);
688 if (!priv->tx_queue[i]) {
689 err = -ENOMEM;
690 goto tx_alloc_failed;
691 }
692 priv->tx_queue[i]->tx_skbuff = NULL;
693 priv->tx_queue[i]->qindex = i;
694 priv->tx_queue[i]->dev = dev;
695 spin_lock_init(&(priv->tx_queue[i]->txlock));
696 }
697
698 for (i = 0; i < priv->num_rx_queues; i++) {
699 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
700 GFP_KERNEL);
701 if (!priv->rx_queue[i]) {
702 err = -ENOMEM;
703 goto rx_alloc_failed;
704 }
705 priv->rx_queue[i]->rx_skbuff = NULL;
706 priv->rx_queue[i]->qindex = i;
707 priv->rx_queue[i]->dev = dev;
708 spin_lock_init(&(priv->rx_queue[i]->rxlock));
709 }
710
711
712 stash = of_get_property(np, "bd-stash", NULL);
713
714 if (stash) {
715 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
716 priv->bd_stash_en = 1;
717 }
718
719 stash_len = of_get_property(np, "rx-stash-len", NULL);
720
721 if (stash_len)
722 priv->rx_stash_size = *stash_len;
723
724 stash_idx = of_get_property(np, "rx-stash-idx", NULL);
725
726 if (stash_idx)
727 priv->rx_stash_index = *stash_idx;
728
729 if (stash_len || stash_idx)
730 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
731
732 mac_addr = of_get_mac_address(np);
733 if (mac_addr)
734 memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
735
736 if (model && !strcasecmp(model, "TSEC"))
737 priv->device_flags =
738 FSL_GIANFAR_DEV_HAS_GIGABIT |
739 FSL_GIANFAR_DEV_HAS_COALESCE |
740 FSL_GIANFAR_DEV_HAS_RMON |
741 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
742 if (model && !strcasecmp(model, "eTSEC"))
743 priv->device_flags =
744 FSL_GIANFAR_DEV_HAS_GIGABIT |
745 FSL_GIANFAR_DEV_HAS_COALESCE |
746 FSL_GIANFAR_DEV_HAS_RMON |
747 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
748 FSL_GIANFAR_DEV_HAS_PADDING |
749 FSL_GIANFAR_DEV_HAS_CSUM |
750 FSL_GIANFAR_DEV_HAS_VLAN |
751 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
752 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
753 FSL_GIANFAR_DEV_HAS_TIMER;
754
755 ctype = of_get_property(np, "phy-connection-type", NULL);
756
757 /* We only care about rgmii-id. The rest are autodetected */
758 if (ctype && !strcmp(ctype, "rgmii-id"))
759 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
760 else
761 priv->interface = PHY_INTERFACE_MODE_MII;
762
763 if (of_get_property(np, "fsl,magic-packet", NULL))
764 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
765
766 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
767
768 /* Find the TBI PHY. If it's not there, we don't support SGMII */
769 priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
770
771 return 0;
772
773 rx_alloc_failed:
774 free_rx_pointers(priv);
775 tx_alloc_failed:
776 free_tx_pointers(priv);
777 err_grp_init:
778 unmap_group_regs(priv);
779 free_netdev(dev);
780 return err;
781 }
782
783 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
784 struct ifreq *ifr, int cmd)
785 {
786 struct hwtstamp_config config;
787 struct gfar_private *priv = netdev_priv(netdev);
788
789 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
790 return -EFAULT;
791
792 /* reserved for future extensions */
793 if (config.flags)
794 return -EINVAL;
795
796 switch (config.tx_type) {
797 case HWTSTAMP_TX_OFF:
798 priv->hwts_tx_en = 0;
799 break;
800 case HWTSTAMP_TX_ON:
801 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
802 return -ERANGE;
803 priv->hwts_tx_en = 1;
804 break;
805 default:
806 return -ERANGE;
807 }
808
809 switch (config.rx_filter) {
810 case HWTSTAMP_FILTER_NONE:
811 if (priv->hwts_rx_en) {
812 stop_gfar(netdev);
813 priv->hwts_rx_en = 0;
814 startup_gfar(netdev);
815 }
816 break;
817 default:
818 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
819 return -ERANGE;
820 if (!priv->hwts_rx_en) {
821 stop_gfar(netdev);
822 priv->hwts_rx_en = 1;
823 startup_gfar(netdev);
824 }
825 config.rx_filter = HWTSTAMP_FILTER_ALL;
826 break;
827 }
828
829 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
830 -EFAULT : 0;
831 }
832
833 /* Ioctl MII Interface */
834 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
835 {
836 struct gfar_private *priv = netdev_priv(dev);
837
838 if (!netif_running(dev))
839 return -EINVAL;
840
841 if (cmd == SIOCSHWTSTAMP)
842 return gfar_hwtstamp_ioctl(dev, rq, cmd);
843
844 if (!priv->phydev)
845 return -ENODEV;
846
847 return phy_mii_ioctl(priv->phydev, rq, cmd);
848 }
849
850 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
851 {
852 unsigned int new_bit_map = 0x0;
853 int mask = 0x1 << (max_qs - 1), i;
854 for (i = 0; i < max_qs; i++) {
855 if (bit_map & mask)
856 new_bit_map = new_bit_map + (1 << i);
857 mask = mask >> 0x1;
858 }
859 return new_bit_map;
860 }
861
862 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
863 u32 class)
864 {
865 u32 rqfpr = FPR_FILER_MASK;
866 u32 rqfcr = 0x0;
867
868 rqfar--;
869 rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
870 ftp_rqfpr[rqfar] = rqfpr;
871 ftp_rqfcr[rqfar] = rqfcr;
872 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
873
874 rqfar--;
875 rqfcr = RQFCR_CMP_NOMATCH;
876 ftp_rqfpr[rqfar] = rqfpr;
877 ftp_rqfcr[rqfar] = rqfcr;
878 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
879
880 rqfar--;
881 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
882 rqfpr = class;
883 ftp_rqfcr[rqfar] = rqfcr;
884 ftp_rqfpr[rqfar] = rqfpr;
885 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
886
887 rqfar--;
888 rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
889 rqfpr = class;
890 ftp_rqfcr[rqfar] = rqfcr;
891 ftp_rqfpr[rqfar] = rqfpr;
892 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
893
894 return rqfar;
895 }
896
897 static void gfar_init_filer_table(struct gfar_private *priv)
898 {
899 int i = 0x0;
900 u32 rqfar = MAX_FILER_IDX;
901 u32 rqfcr = 0x0;
902 u32 rqfpr = FPR_FILER_MASK;
903
904 /* Default rule */
905 rqfcr = RQFCR_CMP_MATCH;
906 ftp_rqfcr[rqfar] = rqfcr;
907 ftp_rqfpr[rqfar] = rqfpr;
908 gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
909
910 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
911 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
912 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
913 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
914 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
915 rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
916
917 /* cur_filer_idx indicated the first non-masked rule */
918 priv->cur_filer_idx = rqfar;
919
920 /* Rest are masked rules */
921 rqfcr = RQFCR_CMP_NOMATCH;
922 for (i = 0; i < rqfar; i++) {
923 ftp_rqfcr[i] = rqfcr;
924 ftp_rqfpr[i] = rqfpr;
925 gfar_write_filer(priv, i, rqfcr, rqfpr);
926 }
927 }
928
929 static void gfar_detect_errata(struct gfar_private *priv)
930 {
931 struct device *dev = &priv->ofdev->dev;
932 unsigned int pvr = mfspr(SPRN_PVR);
933 unsigned int svr = mfspr(SPRN_SVR);
934 unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
935 unsigned int rev = svr & 0xffff;
936
937 /* MPC8313 Rev 2.0 and higher; All MPC837x */
938 if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
939 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
940 priv->errata |= GFAR_ERRATA_74;
941
942 /* MPC8313 and MPC837x all rev */
943 if ((pvr == 0x80850010 && mod == 0x80b0) ||
944 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
945 priv->errata |= GFAR_ERRATA_76;
946
947 /* MPC8313 and MPC837x all rev */
948 if ((pvr == 0x80850010 && mod == 0x80b0) ||
949 (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
950 priv->errata |= GFAR_ERRATA_A002;
951
952 if (priv->errata)
953 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
954 priv->errata);
955 }
956
957 /* Set up the ethernet device structure, private data,
958 * and anything else we need before we start */
959 static int gfar_probe(struct platform_device *ofdev)
960 {
961 u32 tempval;
962 struct net_device *dev = NULL;
963 struct gfar_private *priv = NULL;
964 struct gfar __iomem *regs = NULL;
965 int err = 0, i, grp_idx = 0;
966 int len_devname;
967 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
968 u32 isrg = 0;
969 u32 __iomem *baddr;
970
971 err = gfar_of_init(ofdev, &dev);
972
973 if (err)
974 return err;
975
976 priv = netdev_priv(dev);
977 priv->ndev = dev;
978 priv->ofdev = ofdev;
979 priv->node = ofdev->dev.of_node;
980 SET_NETDEV_DEV(dev, &ofdev->dev);
981
982 spin_lock_init(&priv->bflock);
983 INIT_WORK(&priv->reset_task, gfar_reset_task);
984
985 dev_set_drvdata(&ofdev->dev, priv);
986 regs = priv->gfargrp[0].regs;
987
988 gfar_detect_errata(priv);
989
990 /* Stop the DMA engine now, in case it was running before */
991 /* (The firmware could have used it, and left it running). */
992 gfar_halt(dev);
993
994 /* Reset MAC layer */
995 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
996
997 /* We need to delay at least 3 TX clocks */
998 udelay(2);
999
1000 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1001 gfar_write(&regs->maccfg1, tempval);
1002
1003 /* Initialize MACCFG2. */
1004 tempval = MACCFG2_INIT_SETTINGS;
1005 if (gfar_has_errata(priv, GFAR_ERRATA_74))
1006 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1007 gfar_write(&regs->maccfg2, tempval);
1008
1009 /* Initialize ECNTRL */
1010 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1011
1012 /* Set the dev->base_addr to the gfar reg region */
1013 dev->base_addr = (unsigned long) regs;
1014
1015 SET_NETDEV_DEV(dev, &ofdev->dev);
1016
1017 /* Fill in the dev structure */
1018 dev->watchdog_timeo = TX_TIMEOUT;
1019 dev->mtu = 1500;
1020 dev->netdev_ops = &gfar_netdev_ops;
1021 dev->ethtool_ops = &gfar_ethtool_ops;
1022
1023 /* Register for napi ...We are registering NAPI for each grp */
1024 for (i = 0; i < priv->num_grps; i++)
1025 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1026
1027 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1028 priv->rx_csum_enable = 1;
1029 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_HIGHDMA;
1030 } else
1031 priv->rx_csum_enable = 0;
1032
1033 priv->vlgrp = NULL;
1034
1035 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN)
1036 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1037
1038 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1039 priv->extended_hash = 1;
1040 priv->hash_width = 9;
1041
1042 priv->hash_regs[0] = &regs->igaddr0;
1043 priv->hash_regs[1] = &regs->igaddr1;
1044 priv->hash_regs[2] = &regs->igaddr2;
1045 priv->hash_regs[3] = &regs->igaddr3;
1046 priv->hash_regs[4] = &regs->igaddr4;
1047 priv->hash_regs[5] = &regs->igaddr5;
1048 priv->hash_regs[6] = &regs->igaddr6;
1049 priv->hash_regs[7] = &regs->igaddr7;
1050 priv->hash_regs[8] = &regs->gaddr0;
1051 priv->hash_regs[9] = &regs->gaddr1;
1052 priv->hash_regs[10] = &regs->gaddr2;
1053 priv->hash_regs[11] = &regs->gaddr3;
1054 priv->hash_regs[12] = &regs->gaddr4;
1055 priv->hash_regs[13] = &regs->gaddr5;
1056 priv->hash_regs[14] = &regs->gaddr6;
1057 priv->hash_regs[15] = &regs->gaddr7;
1058
1059 } else {
1060 priv->extended_hash = 0;
1061 priv->hash_width = 8;
1062
1063 priv->hash_regs[0] = &regs->gaddr0;
1064 priv->hash_regs[1] = &regs->gaddr1;
1065 priv->hash_regs[2] = &regs->gaddr2;
1066 priv->hash_regs[3] = &regs->gaddr3;
1067 priv->hash_regs[4] = &regs->gaddr4;
1068 priv->hash_regs[5] = &regs->gaddr5;
1069 priv->hash_regs[6] = &regs->gaddr6;
1070 priv->hash_regs[7] = &regs->gaddr7;
1071 }
1072
1073 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1074 priv->padding = DEFAULT_PADDING;
1075 else
1076 priv->padding = 0;
1077
1078 if (dev->features & NETIF_F_IP_CSUM ||
1079 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1080 dev->hard_header_len += GMAC_FCB_LEN;
1081
1082 /* Program the isrg regs only if number of grps > 1 */
1083 if (priv->num_grps > 1) {
1084 baddr = &regs->isrg0;
1085 for (i = 0; i < priv->num_grps; i++) {
1086 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1087 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1088 gfar_write(baddr, isrg);
1089 baddr++;
1090 isrg = 0x0;
1091 }
1092 }
1093
1094 /* Need to reverse the bit maps as bit_map's MSB is q0
1095 * but, for_each_set_bit parses from right to left, which
1096 * basically reverses the queue numbers */
1097 for (i = 0; i< priv->num_grps; i++) {
1098 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1099 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1100 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1101 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1102 }
1103
1104 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1105 * also assign queues to groups */
1106 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1107 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1108 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1109 priv->num_rx_queues) {
1110 priv->gfargrp[grp_idx].num_rx_queues++;
1111 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1112 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1113 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1114 }
1115 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1116 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1117 priv->num_tx_queues) {
1118 priv->gfargrp[grp_idx].num_tx_queues++;
1119 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1120 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1121 tqueue = tqueue | (TQUEUE_EN0 >> i);
1122 }
1123 priv->gfargrp[grp_idx].rstat = rstat;
1124 priv->gfargrp[grp_idx].tstat = tstat;
1125 rstat = tstat =0;
1126 }
1127
1128 gfar_write(&regs->rqueue, rqueue);
1129 gfar_write(&regs->tqueue, tqueue);
1130
1131 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1132
1133 /* Initializing some of the rx/tx queue level parameters */
1134 for (i = 0; i < priv->num_tx_queues; i++) {
1135 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1136 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1137 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1138 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1139 }
1140
1141 for (i = 0; i < priv->num_rx_queues; i++) {
1142 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1143 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1144 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1145 }
1146
1147 /* enable filer if using multiple RX queues*/
1148 if(priv->num_rx_queues > 1)
1149 priv->rx_filer_enable = 1;
1150 /* Enable most messages by default */
1151 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1152
1153 /* Carrier starts down, phylib will bring it up */
1154 netif_carrier_off(dev);
1155
1156 err = register_netdev(dev);
1157
1158 if (err) {
1159 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
1160 dev->name);
1161 goto register_fail;
1162 }
1163
1164 device_init_wakeup(&dev->dev,
1165 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1166
1167 /* fill out IRQ number and name fields */
1168 len_devname = strlen(dev->name);
1169 for (i = 0; i < priv->num_grps; i++) {
1170 strncpy(&priv->gfargrp[i].int_name_tx[0], dev->name,
1171 len_devname);
1172 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1173 strncpy(&priv->gfargrp[i].int_name_tx[len_devname],
1174 "_g", sizeof("_g"));
1175 priv->gfargrp[i].int_name_tx[
1176 strlen(priv->gfargrp[i].int_name_tx)] = i+48;
1177 strncpy(&priv->gfargrp[i].int_name_tx[strlen(
1178 priv->gfargrp[i].int_name_tx)],
1179 "_tx", sizeof("_tx") + 1);
1180
1181 strncpy(&priv->gfargrp[i].int_name_rx[0], dev->name,
1182 len_devname);
1183 strncpy(&priv->gfargrp[i].int_name_rx[len_devname],
1184 "_g", sizeof("_g"));
1185 priv->gfargrp[i].int_name_rx[
1186 strlen(priv->gfargrp[i].int_name_rx)] = i+48;
1187 strncpy(&priv->gfargrp[i].int_name_rx[strlen(
1188 priv->gfargrp[i].int_name_rx)],
1189 "_rx", sizeof("_rx") + 1);
1190
1191 strncpy(&priv->gfargrp[i].int_name_er[0], dev->name,
1192 len_devname);
1193 strncpy(&priv->gfargrp[i].int_name_er[len_devname],
1194 "_g", sizeof("_g"));
1195 priv->gfargrp[i].int_name_er[strlen(
1196 priv->gfargrp[i].int_name_er)] = i+48;
1197 strncpy(&priv->gfargrp[i].int_name_er[strlen(\
1198 priv->gfargrp[i].int_name_er)],
1199 "_er", sizeof("_er") + 1);
1200 } else
1201 priv->gfargrp[i].int_name_tx[len_devname] = '\0';
1202 }
1203
1204 /* Initialize the filer table */
1205 gfar_init_filer_table(priv);
1206
1207 /* Create all the sysfs files */
1208 gfar_init_sysfs(dev);
1209
1210 /* Print out the device info */
1211 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
1212
1213 /* Even more device info helps when determining which kernel */
1214 /* provided which set of benchmarks. */
1215 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
1216 for (i = 0; i < priv->num_rx_queues; i++)
1217 printk(KERN_INFO "%s: RX BD ring size for Q[%d]: %d\n",
1218 dev->name, i, priv->rx_queue[i]->rx_ring_size);
1219 for(i = 0; i < priv->num_tx_queues; i++)
1220 printk(KERN_INFO "%s: TX BD ring size for Q[%d]: %d\n",
1221 dev->name, i, priv->tx_queue[i]->tx_ring_size);
1222
1223 return 0;
1224
1225 register_fail:
1226 unmap_group_regs(priv);
1227 free_tx_pointers(priv);
1228 free_rx_pointers(priv);
1229 if (priv->phy_node)
1230 of_node_put(priv->phy_node);
1231 if (priv->tbi_node)
1232 of_node_put(priv->tbi_node);
1233 free_netdev(dev);
1234 return err;
1235 }
1236
1237 static int gfar_remove(struct platform_device *ofdev)
1238 {
1239 struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1240
1241 if (priv->phy_node)
1242 of_node_put(priv->phy_node);
1243 if (priv->tbi_node)
1244 of_node_put(priv->tbi_node);
1245
1246 dev_set_drvdata(&ofdev->dev, NULL);
1247
1248 unregister_netdev(priv->ndev);
1249 unmap_group_regs(priv);
1250 free_netdev(priv->ndev);
1251
1252 return 0;
1253 }
1254
1255 #ifdef CONFIG_PM
1256
1257 static int gfar_suspend(struct device *dev)
1258 {
1259 struct gfar_private *priv = dev_get_drvdata(dev);
1260 struct net_device *ndev = priv->ndev;
1261 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1262 unsigned long flags;
1263 u32 tempval;
1264
1265 int magic_packet = priv->wol_en &&
1266 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1267
1268 netif_device_detach(ndev);
1269
1270 if (netif_running(ndev)) {
1271
1272 local_irq_save(flags);
1273 lock_tx_qs(priv);
1274 lock_rx_qs(priv);
1275
1276 gfar_halt_nodisable(ndev);
1277
1278 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1279 tempval = gfar_read(&regs->maccfg1);
1280
1281 tempval &= ~MACCFG1_TX_EN;
1282
1283 if (!magic_packet)
1284 tempval &= ~MACCFG1_RX_EN;
1285
1286 gfar_write(&regs->maccfg1, tempval);
1287
1288 unlock_rx_qs(priv);
1289 unlock_tx_qs(priv);
1290 local_irq_restore(flags);
1291
1292 disable_napi(priv);
1293
1294 if (magic_packet) {
1295 /* Enable interrupt on Magic Packet */
1296 gfar_write(&regs->imask, IMASK_MAG);
1297
1298 /* Enable Magic Packet mode */
1299 tempval = gfar_read(&regs->maccfg2);
1300 tempval |= MACCFG2_MPEN;
1301 gfar_write(&regs->maccfg2, tempval);
1302 } else {
1303 phy_stop(priv->phydev);
1304 }
1305 }
1306
1307 return 0;
1308 }
1309
1310 static int gfar_resume(struct device *dev)
1311 {
1312 struct gfar_private *priv = dev_get_drvdata(dev);
1313 struct net_device *ndev = priv->ndev;
1314 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1315 unsigned long flags;
1316 u32 tempval;
1317 int magic_packet = priv->wol_en &&
1318 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1319
1320 if (!netif_running(ndev)) {
1321 netif_device_attach(ndev);
1322 return 0;
1323 }
1324
1325 if (!magic_packet && priv->phydev)
1326 phy_start(priv->phydev);
1327
1328 /* Disable Magic Packet mode, in case something
1329 * else woke us up.
1330 */
1331 local_irq_save(flags);
1332 lock_tx_qs(priv);
1333 lock_rx_qs(priv);
1334
1335 tempval = gfar_read(&regs->maccfg2);
1336 tempval &= ~MACCFG2_MPEN;
1337 gfar_write(&regs->maccfg2, tempval);
1338
1339 gfar_start(ndev);
1340
1341 unlock_rx_qs(priv);
1342 unlock_tx_qs(priv);
1343 local_irq_restore(flags);
1344
1345 netif_device_attach(ndev);
1346
1347 enable_napi(priv);
1348
1349 return 0;
1350 }
1351
1352 static int gfar_restore(struct device *dev)
1353 {
1354 struct gfar_private *priv = dev_get_drvdata(dev);
1355 struct net_device *ndev = priv->ndev;
1356
1357 if (!netif_running(ndev))
1358 return 0;
1359
1360 gfar_init_bds(ndev);
1361 init_registers(ndev);
1362 gfar_set_mac_address(ndev);
1363 gfar_init_mac(ndev);
1364 gfar_start(ndev);
1365
1366 priv->oldlink = 0;
1367 priv->oldspeed = 0;
1368 priv->oldduplex = -1;
1369
1370 if (priv->phydev)
1371 phy_start(priv->phydev);
1372
1373 netif_device_attach(ndev);
1374 enable_napi(priv);
1375
1376 return 0;
1377 }
1378
1379 static struct dev_pm_ops gfar_pm_ops = {
1380 .suspend = gfar_suspend,
1381 .resume = gfar_resume,
1382 .freeze = gfar_suspend,
1383 .thaw = gfar_resume,
1384 .restore = gfar_restore,
1385 };
1386
1387 #define GFAR_PM_OPS (&gfar_pm_ops)
1388
1389 #else
1390
1391 #define GFAR_PM_OPS NULL
1392
1393 #endif
1394
1395 /* Reads the controller's registers to determine what interface
1396 * connects it to the PHY.
1397 */
1398 static phy_interface_t gfar_get_interface(struct net_device *dev)
1399 {
1400 struct gfar_private *priv = netdev_priv(dev);
1401 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1402 u32 ecntrl;
1403
1404 ecntrl = gfar_read(&regs->ecntrl);
1405
1406 if (ecntrl & ECNTRL_SGMII_MODE)
1407 return PHY_INTERFACE_MODE_SGMII;
1408
1409 if (ecntrl & ECNTRL_TBI_MODE) {
1410 if (ecntrl & ECNTRL_REDUCED_MODE)
1411 return PHY_INTERFACE_MODE_RTBI;
1412 else
1413 return PHY_INTERFACE_MODE_TBI;
1414 }
1415
1416 if (ecntrl & ECNTRL_REDUCED_MODE) {
1417 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1418 return PHY_INTERFACE_MODE_RMII;
1419 else {
1420 phy_interface_t interface = priv->interface;
1421
1422 /*
1423 * This isn't autodetected right now, so it must
1424 * be set by the device tree or platform code.
1425 */
1426 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1427 return PHY_INTERFACE_MODE_RGMII_ID;
1428
1429 return PHY_INTERFACE_MODE_RGMII;
1430 }
1431 }
1432
1433 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1434 return PHY_INTERFACE_MODE_GMII;
1435
1436 return PHY_INTERFACE_MODE_MII;
1437 }
1438
1439
1440 /* Initializes driver's PHY state, and attaches to the PHY.
1441 * Returns 0 on success.
1442 */
1443 static int init_phy(struct net_device *dev)
1444 {
1445 struct gfar_private *priv = netdev_priv(dev);
1446 uint gigabit_support =
1447 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1448 SUPPORTED_1000baseT_Full : 0;
1449 phy_interface_t interface;
1450
1451 priv->oldlink = 0;
1452 priv->oldspeed = 0;
1453 priv->oldduplex = -1;
1454
1455 interface = gfar_get_interface(dev);
1456
1457 priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1458 interface);
1459 if (!priv->phydev)
1460 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1461 interface);
1462 if (!priv->phydev) {
1463 dev_err(&dev->dev, "could not attach to PHY\n");
1464 return -ENODEV;
1465 }
1466
1467 if (interface == PHY_INTERFACE_MODE_SGMII)
1468 gfar_configure_serdes(dev);
1469
1470 /* Remove any features not supported by the controller */
1471 priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1472 priv->phydev->advertising = priv->phydev->supported;
1473
1474 return 0;
1475 }
1476
1477 /*
1478 * Initialize TBI PHY interface for communicating with the
1479 * SERDES lynx PHY on the chip. We communicate with this PHY
1480 * through the MDIO bus on each controller, treating it as a
1481 * "normal" PHY at the address found in the TBIPA register. We assume
1482 * that the TBIPA register is valid. Either the MDIO bus code will set
1483 * it to a value that doesn't conflict with other PHYs on the bus, or the
1484 * value doesn't matter, as there are no other PHYs on the bus.
1485 */
1486 static void gfar_configure_serdes(struct net_device *dev)
1487 {
1488 struct gfar_private *priv = netdev_priv(dev);
1489 struct phy_device *tbiphy;
1490
1491 if (!priv->tbi_node) {
1492 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1493 "device tree specify a tbi-handle\n");
1494 return;
1495 }
1496
1497 tbiphy = of_phy_find_device(priv->tbi_node);
1498 if (!tbiphy) {
1499 dev_err(&dev->dev, "error: Could not get TBI device\n");
1500 return;
1501 }
1502
1503 /*
1504 * If the link is already up, we must already be ok, and don't need to
1505 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1506 * everything for us? Resetting it takes the link down and requires
1507 * several seconds for it to come back.
1508 */
1509 if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1510 return;
1511
1512 /* Single clk mode, mii mode off(for serdes communication) */
1513 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1514
1515 phy_write(tbiphy, MII_ADVERTISE,
1516 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1517 ADVERTISE_1000XPSE_ASYM);
1518
1519 phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1520 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1521 }
1522
1523 static void init_registers(struct net_device *dev)
1524 {
1525 struct gfar_private *priv = netdev_priv(dev);
1526 struct gfar __iomem *regs = NULL;
1527 int i = 0;
1528
1529 for (i = 0; i < priv->num_grps; i++) {
1530 regs = priv->gfargrp[i].regs;
1531 /* Clear IEVENT */
1532 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1533
1534 /* Initialize IMASK */
1535 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1536 }
1537
1538 regs = priv->gfargrp[0].regs;
1539 /* Init hash registers to zero */
1540 gfar_write(&regs->igaddr0, 0);
1541 gfar_write(&regs->igaddr1, 0);
1542 gfar_write(&regs->igaddr2, 0);
1543 gfar_write(&regs->igaddr3, 0);
1544 gfar_write(&regs->igaddr4, 0);
1545 gfar_write(&regs->igaddr5, 0);
1546 gfar_write(&regs->igaddr6, 0);
1547 gfar_write(&regs->igaddr7, 0);
1548
1549 gfar_write(&regs->gaddr0, 0);
1550 gfar_write(&regs->gaddr1, 0);
1551 gfar_write(&regs->gaddr2, 0);
1552 gfar_write(&regs->gaddr3, 0);
1553 gfar_write(&regs->gaddr4, 0);
1554 gfar_write(&regs->gaddr5, 0);
1555 gfar_write(&regs->gaddr6, 0);
1556 gfar_write(&regs->gaddr7, 0);
1557
1558 /* Zero out the rmon mib registers if it has them */
1559 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1560 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1561
1562 /* Mask off the CAM interrupts */
1563 gfar_write(&regs->rmon.cam1, 0xffffffff);
1564 gfar_write(&regs->rmon.cam2, 0xffffffff);
1565 }
1566
1567 /* Initialize the max receive buffer length */
1568 gfar_write(&regs->mrblr, priv->rx_buffer_size);
1569
1570 /* Initialize the Minimum Frame Length Register */
1571 gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1572 }
1573
1574 static int __gfar_is_rx_idle(struct gfar_private *priv)
1575 {
1576 u32 res;
1577
1578 /*
1579 * Normaly TSEC should not hang on GRS commands, so we should
1580 * actually wait for IEVENT_GRSC flag.
1581 */
1582 if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1583 return 0;
1584
1585 /*
1586 * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1587 * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1588 * and the Rx can be safely reset.
1589 */
1590 res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1591 res &= 0x7f807f80;
1592 if ((res & 0xffff) == (res >> 16))
1593 return 1;
1594
1595 return 0;
1596 }
1597
1598 /* Halt the receive and transmit queues */
1599 static void gfar_halt_nodisable(struct net_device *dev)
1600 {
1601 struct gfar_private *priv = netdev_priv(dev);
1602 struct gfar __iomem *regs = NULL;
1603 u32 tempval;
1604 int i = 0;
1605
1606 for (i = 0; i < priv->num_grps; i++) {
1607 regs = priv->gfargrp[i].regs;
1608 /* Mask all interrupts */
1609 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1610
1611 /* Clear all interrupts */
1612 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1613 }
1614
1615 regs = priv->gfargrp[0].regs;
1616 /* Stop the DMA, and wait for it to stop */
1617 tempval = gfar_read(&regs->dmactrl);
1618 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1619 != (DMACTRL_GRS | DMACTRL_GTS)) {
1620 int ret;
1621
1622 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1623 gfar_write(&regs->dmactrl, tempval);
1624
1625 do {
1626 ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1627 (IEVENT_GRSC | IEVENT_GTSC)) ==
1628 (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1629 if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1630 ret = __gfar_is_rx_idle(priv);
1631 } while (!ret);
1632 }
1633 }
1634
1635 /* Halt the receive and transmit queues */
1636 void gfar_halt(struct net_device *dev)
1637 {
1638 struct gfar_private *priv = netdev_priv(dev);
1639 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1640 u32 tempval;
1641
1642 gfar_halt_nodisable(dev);
1643
1644 /* Disable Rx and Tx */
1645 tempval = gfar_read(&regs->maccfg1);
1646 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1647 gfar_write(&regs->maccfg1, tempval);
1648 }
1649
1650 static void free_grp_irqs(struct gfar_priv_grp *grp)
1651 {
1652 free_irq(grp->interruptError, grp);
1653 free_irq(grp->interruptTransmit, grp);
1654 free_irq(grp->interruptReceive, grp);
1655 }
1656
1657 void stop_gfar(struct net_device *dev)
1658 {
1659 struct gfar_private *priv = netdev_priv(dev);
1660 unsigned long flags;
1661 int i;
1662
1663 phy_stop(priv->phydev);
1664
1665
1666 /* Lock it down */
1667 local_irq_save(flags);
1668 lock_tx_qs(priv);
1669 lock_rx_qs(priv);
1670
1671 gfar_halt(dev);
1672
1673 unlock_rx_qs(priv);
1674 unlock_tx_qs(priv);
1675 local_irq_restore(flags);
1676
1677 /* Free the IRQs */
1678 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1679 for (i = 0; i < priv->num_grps; i++)
1680 free_grp_irqs(&priv->gfargrp[i]);
1681 } else {
1682 for (i = 0; i < priv->num_grps; i++)
1683 free_irq(priv->gfargrp[i].interruptTransmit,
1684 &priv->gfargrp[i]);
1685 }
1686
1687 free_skb_resources(priv);
1688 }
1689
1690 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1691 {
1692 struct txbd8 *txbdp;
1693 struct gfar_private *priv = netdev_priv(tx_queue->dev);
1694 int i, j;
1695
1696 txbdp = tx_queue->tx_bd_base;
1697
1698 for (i = 0; i < tx_queue->tx_ring_size; i++) {
1699 if (!tx_queue->tx_skbuff[i])
1700 continue;
1701
1702 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1703 txbdp->length, DMA_TO_DEVICE);
1704 txbdp->lstatus = 0;
1705 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1706 j++) {
1707 txbdp++;
1708 dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1709 txbdp->length, DMA_TO_DEVICE);
1710 }
1711 txbdp++;
1712 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1713 tx_queue->tx_skbuff[i] = NULL;
1714 }
1715 kfree(tx_queue->tx_skbuff);
1716 }
1717
1718 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1719 {
1720 struct rxbd8 *rxbdp;
1721 struct gfar_private *priv = netdev_priv(rx_queue->dev);
1722 int i;
1723
1724 rxbdp = rx_queue->rx_bd_base;
1725
1726 for (i = 0; i < rx_queue->rx_ring_size; i++) {
1727 if (rx_queue->rx_skbuff[i]) {
1728 dma_unmap_single(&priv->ofdev->dev,
1729 rxbdp->bufPtr, priv->rx_buffer_size,
1730 DMA_FROM_DEVICE);
1731 dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1732 rx_queue->rx_skbuff[i] = NULL;
1733 }
1734 rxbdp->lstatus = 0;
1735 rxbdp->bufPtr = 0;
1736 rxbdp++;
1737 }
1738 kfree(rx_queue->rx_skbuff);
1739 }
1740
1741 /* If there are any tx skbs or rx skbs still around, free them.
1742 * Then free tx_skbuff and rx_skbuff */
1743 static void free_skb_resources(struct gfar_private *priv)
1744 {
1745 struct gfar_priv_tx_q *tx_queue = NULL;
1746 struct gfar_priv_rx_q *rx_queue = NULL;
1747 int i;
1748
1749 /* Go through all the buffer descriptors and free their data buffers */
1750 for (i = 0; i < priv->num_tx_queues; i++) {
1751 tx_queue = priv->tx_queue[i];
1752 if(tx_queue->tx_skbuff)
1753 free_skb_tx_queue(tx_queue);
1754 }
1755
1756 for (i = 0; i < priv->num_rx_queues; i++) {
1757 rx_queue = priv->rx_queue[i];
1758 if(rx_queue->rx_skbuff)
1759 free_skb_rx_queue(rx_queue);
1760 }
1761
1762 dma_free_coherent(&priv->ofdev->dev,
1763 sizeof(struct txbd8) * priv->total_tx_ring_size +
1764 sizeof(struct rxbd8) * priv->total_rx_ring_size,
1765 priv->tx_queue[0]->tx_bd_base,
1766 priv->tx_queue[0]->tx_bd_dma_base);
1767 skb_queue_purge(&priv->rx_recycle);
1768 }
1769
1770 void gfar_start(struct net_device *dev)
1771 {
1772 struct gfar_private *priv = netdev_priv(dev);
1773 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1774 u32 tempval;
1775 int i = 0;
1776
1777 /* Enable Rx and Tx in MACCFG1 */
1778 tempval = gfar_read(&regs->maccfg1);
1779 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1780 gfar_write(&regs->maccfg1, tempval);
1781
1782 /* Initialize DMACTRL to have WWR and WOP */
1783 tempval = gfar_read(&regs->dmactrl);
1784 tempval |= DMACTRL_INIT_SETTINGS;
1785 gfar_write(&regs->dmactrl, tempval);
1786
1787 /* Make sure we aren't stopped */
1788 tempval = gfar_read(&regs->dmactrl);
1789 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1790 gfar_write(&regs->dmactrl, tempval);
1791
1792 for (i = 0; i < priv->num_grps; i++) {
1793 regs = priv->gfargrp[i].regs;
1794 /* Clear THLT/RHLT, so that the DMA starts polling now */
1795 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1796 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1797 /* Unmask the interrupts we look for */
1798 gfar_write(&regs->imask, IMASK_DEFAULT);
1799 }
1800
1801 dev->trans_start = jiffies; /* prevent tx timeout */
1802 }
1803
1804 void gfar_configure_coalescing(struct gfar_private *priv,
1805 unsigned long tx_mask, unsigned long rx_mask)
1806 {
1807 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1808 u32 __iomem *baddr;
1809 int i = 0;
1810
1811 /* Backward compatible case ---- even if we enable
1812 * multiple queues, there's only single reg to program
1813 */
1814 gfar_write(&regs->txic, 0);
1815 if(likely(priv->tx_queue[0]->txcoalescing))
1816 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1817
1818 gfar_write(&regs->rxic, 0);
1819 if(unlikely(priv->rx_queue[0]->rxcoalescing))
1820 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1821
1822 if (priv->mode == MQ_MG_MODE) {
1823 baddr = &regs->txic0;
1824 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1825 if (likely(priv->tx_queue[i]->txcoalescing)) {
1826 gfar_write(baddr + i, 0);
1827 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1828 }
1829 }
1830
1831 baddr = &regs->rxic0;
1832 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1833 if (likely(priv->rx_queue[i]->rxcoalescing)) {
1834 gfar_write(baddr + i, 0);
1835 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1836 }
1837 }
1838 }
1839 }
1840
1841 static int register_grp_irqs(struct gfar_priv_grp *grp)
1842 {
1843 struct gfar_private *priv = grp->priv;
1844 struct net_device *dev = priv->ndev;
1845 int err;
1846
1847 /* If the device has multiple interrupts, register for
1848 * them. Otherwise, only register for the one */
1849 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1850 /* Install our interrupt handlers for Error,
1851 * Transmit, and Receive */
1852 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1853 grp->int_name_er,grp)) < 0) {
1854 if (netif_msg_intr(priv))
1855 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1856 dev->name, grp->interruptError);
1857
1858 goto err_irq_fail;
1859 }
1860
1861 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1862 0, grp->int_name_tx, grp)) < 0) {
1863 if (netif_msg_intr(priv))
1864 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1865 dev->name, grp->interruptTransmit);
1866 goto tx_irq_fail;
1867 }
1868
1869 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1870 grp->int_name_rx, grp)) < 0) {
1871 if (netif_msg_intr(priv))
1872 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1873 dev->name, grp->interruptReceive);
1874 goto rx_irq_fail;
1875 }
1876 } else {
1877 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1878 grp->int_name_tx, grp)) < 0) {
1879 if (netif_msg_intr(priv))
1880 printk(KERN_ERR "%s: Can't get IRQ %d\n",
1881 dev->name, grp->interruptTransmit);
1882 goto err_irq_fail;
1883 }
1884 }
1885
1886 return 0;
1887
1888 rx_irq_fail:
1889 free_irq(grp->interruptTransmit, grp);
1890 tx_irq_fail:
1891 free_irq(grp->interruptError, grp);
1892 err_irq_fail:
1893 return err;
1894
1895 }
1896
1897 /* Bring the controller up and running */
1898 int startup_gfar(struct net_device *ndev)
1899 {
1900 struct gfar_private *priv = netdev_priv(ndev);
1901 struct gfar __iomem *regs = NULL;
1902 int err, i, j;
1903
1904 for (i = 0; i < priv->num_grps; i++) {
1905 regs= priv->gfargrp[i].regs;
1906 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1907 }
1908
1909 regs= priv->gfargrp[0].regs;
1910 err = gfar_alloc_skb_resources(ndev);
1911 if (err)
1912 return err;
1913
1914 gfar_init_mac(ndev);
1915
1916 for (i = 0; i < priv->num_grps; i++) {
1917 err = register_grp_irqs(&priv->gfargrp[i]);
1918 if (err) {
1919 for (j = 0; j < i; j++)
1920 free_grp_irqs(&priv->gfargrp[j]);
1921 goto irq_fail;
1922 }
1923 }
1924
1925 /* Start the controller */
1926 gfar_start(ndev);
1927
1928 phy_start(priv->phydev);
1929
1930 gfar_configure_coalescing(priv, 0xFF, 0xFF);
1931
1932 return 0;
1933
1934 irq_fail:
1935 free_skb_resources(priv);
1936 return err;
1937 }
1938
1939 /* Called when something needs to use the ethernet device */
1940 /* Returns 0 for success. */
1941 static int gfar_enet_open(struct net_device *dev)
1942 {
1943 struct gfar_private *priv = netdev_priv(dev);
1944 int err;
1945
1946 enable_napi(priv);
1947
1948 skb_queue_head_init(&priv->rx_recycle);
1949
1950 /* Initialize a bunch of registers */
1951 init_registers(dev);
1952
1953 gfar_set_mac_address(dev);
1954
1955 err = init_phy(dev);
1956
1957 if (err) {
1958 disable_napi(priv);
1959 return err;
1960 }
1961
1962 err = startup_gfar(dev);
1963 if (err) {
1964 disable_napi(priv);
1965 return err;
1966 }
1967
1968 netif_tx_start_all_queues(dev);
1969
1970 device_set_wakeup_enable(&dev->dev, priv->wol_en);
1971
1972 return err;
1973 }
1974
1975 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1976 {
1977 struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1978
1979 memset(fcb, 0, GMAC_FCB_LEN);
1980
1981 return fcb;
1982 }
1983
1984 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1985 {
1986 u8 flags = 0;
1987
1988 /* If we're here, it's a IP packet with a TCP or UDP
1989 * payload. We set it to checksum, using a pseudo-header
1990 * we provide
1991 */
1992 flags = TXFCB_DEFAULT;
1993
1994 /* Tell the controller what the protocol is */
1995 /* And provide the already calculated phcs */
1996 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1997 flags |= TXFCB_UDP;
1998 fcb->phcs = udp_hdr(skb)->check;
1999 } else
2000 fcb->phcs = tcp_hdr(skb)->check;
2001
2002 /* l3os is the distance between the start of the
2003 * frame (skb->data) and the start of the IP hdr.
2004 * l4os is the distance between the start of the
2005 * l3 hdr and the l4 hdr */
2006 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
2007 fcb->l4os = skb_network_header_len(skb);
2008
2009 fcb->flags = flags;
2010 }
2011
2012 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2013 {
2014 fcb->flags |= TXFCB_VLN;
2015 fcb->vlctl = vlan_tx_tag_get(skb);
2016 }
2017
2018 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2019 struct txbd8 *base, int ring_size)
2020 {
2021 struct txbd8 *new_bd = bdp + stride;
2022
2023 return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2024 }
2025
2026 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2027 int ring_size)
2028 {
2029 return skip_txbd(bdp, 1, base, ring_size);
2030 }
2031
2032 /* This is called by the kernel when a frame is ready for transmission. */
2033 /* It is pointed to by the dev->hard_start_xmit function pointer */
2034 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2035 {
2036 struct gfar_private *priv = netdev_priv(dev);
2037 struct gfar_priv_tx_q *tx_queue = NULL;
2038 struct netdev_queue *txq;
2039 struct gfar __iomem *regs = NULL;
2040 struct txfcb *fcb = NULL;
2041 struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2042 u32 lstatus;
2043 int i, rq = 0, do_tstamp = 0;
2044 u32 bufaddr;
2045 unsigned long flags;
2046 unsigned int nr_frags, nr_txbds, length;
2047
2048 /*
2049 * TOE=1 frames larger than 2500 bytes may see excess delays
2050 * before start of transmission.
2051 */
2052 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2053 skb->ip_summed == CHECKSUM_PARTIAL &&
2054 skb->len > 2500)) {
2055 int ret;
2056
2057 ret = skb_checksum_help(skb);
2058 if (ret)
2059 return ret;
2060 }
2061
2062 rq = skb->queue_mapping;
2063 tx_queue = priv->tx_queue[rq];
2064 txq = netdev_get_tx_queue(dev, rq);
2065 base = tx_queue->tx_bd_base;
2066 regs = tx_queue->grp->regs;
2067
2068 /* check if time stamp should be generated */
2069 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2070 priv->hwts_tx_en))
2071 do_tstamp = 1;
2072
2073 /* make space for additional header when fcb is needed */
2074 if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2075 vlan_tx_tag_present(skb) ||
2076 unlikely(do_tstamp)) &&
2077 (skb_headroom(skb) < GMAC_FCB_LEN)) {
2078 struct sk_buff *skb_new;
2079
2080 skb_new = skb_realloc_headroom(skb, GMAC_FCB_LEN);
2081 if (!skb_new) {
2082 dev->stats.tx_errors++;
2083 kfree_skb(skb);
2084 return NETDEV_TX_OK;
2085 }
2086 kfree_skb(skb);
2087 skb = skb_new;
2088 }
2089
2090 /* total number of fragments in the SKB */
2091 nr_frags = skb_shinfo(skb)->nr_frags;
2092
2093 /* calculate the required number of TxBDs for this skb */
2094 if (unlikely(do_tstamp))
2095 nr_txbds = nr_frags + 2;
2096 else
2097 nr_txbds = nr_frags + 1;
2098
2099 /* check if there is space to queue this packet */
2100 if (nr_txbds > tx_queue->num_txbdfree) {
2101 /* no space, stop the queue */
2102 netif_tx_stop_queue(txq);
2103 dev->stats.tx_fifo_errors++;
2104 return NETDEV_TX_BUSY;
2105 }
2106
2107 /* Update transmit stats */
2108 tx_queue->stats.tx_bytes += skb->len;
2109 tx_queue->stats.tx_packets++;
2110
2111 txbdp = txbdp_start = tx_queue->cur_tx;
2112 lstatus = txbdp->lstatus;
2113
2114 /* Time stamp insertion requires one additional TxBD */
2115 if (unlikely(do_tstamp))
2116 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2117 tx_queue->tx_ring_size);
2118
2119 if (nr_frags == 0) {
2120 if (unlikely(do_tstamp))
2121 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2122 TXBD_INTERRUPT);
2123 else
2124 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2125 } else {
2126 /* Place the fragment addresses and lengths into the TxBDs */
2127 for (i = 0; i < nr_frags; i++) {
2128 /* Point at the next BD, wrapping as needed */
2129 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2130
2131 length = skb_shinfo(skb)->frags[i].size;
2132
2133 lstatus = txbdp->lstatus | length |
2134 BD_LFLAG(TXBD_READY);
2135
2136 /* Handle the last BD specially */
2137 if (i == nr_frags - 1)
2138 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2139
2140 bufaddr = dma_map_page(&priv->ofdev->dev,
2141 skb_shinfo(skb)->frags[i].page,
2142 skb_shinfo(skb)->frags[i].page_offset,
2143 length,
2144 DMA_TO_DEVICE);
2145
2146 /* set the TxBD length and buffer pointer */
2147 txbdp->bufPtr = bufaddr;
2148 txbdp->lstatus = lstatus;
2149 }
2150
2151 lstatus = txbdp_start->lstatus;
2152 }
2153
2154 /* Set up checksumming */
2155 if (CHECKSUM_PARTIAL == skb->ip_summed) {
2156 fcb = gfar_add_fcb(skb);
2157 lstatus |= BD_LFLAG(TXBD_TOE);
2158 gfar_tx_checksum(skb, fcb);
2159 }
2160
2161 if (vlan_tx_tag_present(skb)) {
2162 if (unlikely(NULL == fcb)) {
2163 fcb = gfar_add_fcb(skb);
2164 lstatus |= BD_LFLAG(TXBD_TOE);
2165 }
2166
2167 gfar_tx_vlan(skb, fcb);
2168 }
2169
2170 /* Setup tx hardware time stamping if requested */
2171 if (unlikely(do_tstamp)) {
2172 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2173 if (fcb == NULL)
2174 fcb = gfar_add_fcb(skb);
2175 fcb->ptp = 1;
2176 lstatus |= BD_LFLAG(TXBD_TOE);
2177 }
2178
2179 txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2180 skb_headlen(skb), DMA_TO_DEVICE);
2181
2182 /*
2183 * If time stamping is requested one additional TxBD must be set up. The
2184 * first TxBD points to the FCB and must have a data length of
2185 * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2186 * the full frame length.
2187 */
2188 if (unlikely(do_tstamp)) {
2189 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + GMAC_FCB_LEN;
2190 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2191 (skb_headlen(skb) - GMAC_FCB_LEN);
2192 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2193 } else {
2194 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2195 }
2196
2197 /*
2198 * We can work in parallel with gfar_clean_tx_ring(), except
2199 * when modifying num_txbdfree. Note that we didn't grab the lock
2200 * when we were reading the num_txbdfree and checking for available
2201 * space, that's because outside of this function it can only grow,
2202 * and once we've got needed space, it cannot suddenly disappear.
2203 *
2204 * The lock also protects us from gfar_error(), which can modify
2205 * regs->tstat and thus retrigger the transfers, which is why we
2206 * also must grab the lock before setting ready bit for the first
2207 * to be transmitted BD.
2208 */
2209 spin_lock_irqsave(&tx_queue->txlock, flags);
2210
2211 /*
2212 * The powerpc-specific eieio() is used, as wmb() has too strong
2213 * semantics (it requires synchronization between cacheable and
2214 * uncacheable mappings, which eieio doesn't provide and which we
2215 * don't need), thus requiring a more expensive sync instruction. At
2216 * some point, the set of architecture-independent barrier functions
2217 * should be expanded to include weaker barriers.
2218 */
2219 eieio();
2220
2221 txbdp_start->lstatus = lstatus;
2222
2223 eieio(); /* force lstatus write before tx_skbuff */
2224
2225 tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2226
2227 /* Update the current skb pointer to the next entry we will use
2228 * (wrapping if necessary) */
2229 tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2230 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2231
2232 tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2233
2234 /* reduce TxBD free count */
2235 tx_queue->num_txbdfree -= (nr_txbds);
2236
2237 /* If the next BD still needs to be cleaned up, then the bds
2238 are full. We need to tell the kernel to stop sending us stuff. */
2239 if (!tx_queue->num_txbdfree) {
2240 netif_tx_stop_queue(txq);
2241
2242 dev->stats.tx_fifo_errors++;
2243 }
2244
2245 /* Tell the DMA to go go go */
2246 gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2247
2248 /* Unlock priv */
2249 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2250
2251 return NETDEV_TX_OK;
2252 }
2253
2254 /* Stops the kernel queue, and halts the controller */
2255 static int gfar_close(struct net_device *dev)
2256 {
2257 struct gfar_private *priv = netdev_priv(dev);
2258
2259 disable_napi(priv);
2260
2261 cancel_work_sync(&priv->reset_task);
2262 stop_gfar(dev);
2263
2264 /* Disconnect from the PHY */
2265 phy_disconnect(priv->phydev);
2266 priv->phydev = NULL;
2267
2268 netif_tx_stop_all_queues(dev);
2269
2270 return 0;
2271 }
2272
2273 /* Changes the mac address if the controller is not running. */
2274 static int gfar_set_mac_address(struct net_device *dev)
2275 {
2276 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2277
2278 return 0;
2279 }
2280
2281
2282 /* Enables and disables VLAN insertion/extraction */
2283 static void gfar_vlan_rx_register(struct net_device *dev,
2284 struct vlan_group *grp)
2285 {
2286 struct gfar_private *priv = netdev_priv(dev);
2287 struct gfar __iomem *regs = NULL;
2288 unsigned long flags;
2289 u32 tempval;
2290
2291 regs = priv->gfargrp[0].regs;
2292 local_irq_save(flags);
2293 lock_rx_qs(priv);
2294
2295 priv->vlgrp = grp;
2296
2297 if (grp) {
2298 /* Enable VLAN tag insertion */
2299 tempval = gfar_read(&regs->tctrl);
2300 tempval |= TCTRL_VLINS;
2301
2302 gfar_write(&regs->tctrl, tempval);
2303
2304 /* Enable VLAN tag extraction */
2305 tempval = gfar_read(&regs->rctrl);
2306 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2307 gfar_write(&regs->rctrl, tempval);
2308 } else {
2309 /* Disable VLAN tag insertion */
2310 tempval = gfar_read(&regs->tctrl);
2311 tempval &= ~TCTRL_VLINS;
2312 gfar_write(&regs->tctrl, tempval);
2313
2314 /* Disable VLAN tag extraction */
2315 tempval = gfar_read(&regs->rctrl);
2316 tempval &= ~RCTRL_VLEX;
2317 /* If parse is no longer required, then disable parser */
2318 if (tempval & RCTRL_REQ_PARSER)
2319 tempval |= RCTRL_PRSDEP_INIT;
2320 else
2321 tempval &= ~RCTRL_PRSDEP_INIT;
2322 gfar_write(&regs->rctrl, tempval);
2323 }
2324
2325 gfar_change_mtu(dev, dev->mtu);
2326
2327 unlock_rx_qs(priv);
2328 local_irq_restore(flags);
2329 }
2330
2331 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2332 {
2333 int tempsize, tempval;
2334 struct gfar_private *priv = netdev_priv(dev);
2335 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2336 int oldsize = priv->rx_buffer_size;
2337 int frame_size = new_mtu + ETH_HLEN;
2338
2339 if (priv->vlgrp)
2340 frame_size += VLAN_HLEN;
2341
2342 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2343 if (netif_msg_drv(priv))
2344 printk(KERN_ERR "%s: Invalid MTU setting\n",
2345 dev->name);
2346 return -EINVAL;
2347 }
2348
2349 if (gfar_uses_fcb(priv))
2350 frame_size += GMAC_FCB_LEN;
2351
2352 frame_size += priv->padding;
2353
2354 tempsize =
2355 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2356 INCREMENTAL_BUFFER_SIZE;
2357
2358 /* Only stop and start the controller if it isn't already
2359 * stopped, and we changed something */
2360 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2361 stop_gfar(dev);
2362
2363 priv->rx_buffer_size = tempsize;
2364
2365 dev->mtu = new_mtu;
2366
2367 gfar_write(&regs->mrblr, priv->rx_buffer_size);
2368 gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2369
2370 /* If the mtu is larger than the max size for standard
2371 * ethernet frames (ie, a jumbo frame), then set maccfg2
2372 * to allow huge frames, and to check the length */
2373 tempval = gfar_read(&regs->maccfg2);
2374
2375 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2376 gfar_has_errata(priv, GFAR_ERRATA_74))
2377 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2378 else
2379 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2380
2381 gfar_write(&regs->maccfg2, tempval);
2382
2383 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2384 startup_gfar(dev);
2385
2386 return 0;
2387 }
2388
2389 /* gfar_reset_task gets scheduled when a packet has not been
2390 * transmitted after a set amount of time.
2391 * For now, assume that clearing out all the structures, and
2392 * starting over will fix the problem.
2393 */
2394 static void gfar_reset_task(struct work_struct *work)
2395 {
2396 struct gfar_private *priv = container_of(work, struct gfar_private,
2397 reset_task);
2398 struct net_device *dev = priv->ndev;
2399
2400 if (dev->flags & IFF_UP) {
2401 netif_tx_stop_all_queues(dev);
2402 stop_gfar(dev);
2403 startup_gfar(dev);
2404 netif_tx_start_all_queues(dev);
2405 }
2406
2407 netif_tx_schedule_all(dev);
2408 }
2409
2410 static void gfar_timeout(struct net_device *dev)
2411 {
2412 struct gfar_private *priv = netdev_priv(dev);
2413
2414 dev->stats.tx_errors++;
2415 schedule_work(&priv->reset_task);
2416 }
2417
2418 static void gfar_align_skb(struct sk_buff *skb)
2419 {
2420 /* We need the data buffer to be aligned properly. We will reserve
2421 * as many bytes as needed to align the data properly
2422 */
2423 skb_reserve(skb, RXBUF_ALIGNMENT -
2424 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2425 }
2426
2427 /* Interrupt Handler for Transmit complete */
2428 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2429 {
2430 struct net_device *dev = tx_queue->dev;
2431 struct gfar_private *priv = netdev_priv(dev);
2432 struct gfar_priv_rx_q *rx_queue = NULL;
2433 struct txbd8 *bdp, *next = NULL;
2434 struct txbd8 *lbdp = NULL;
2435 struct txbd8 *base = tx_queue->tx_bd_base;
2436 struct sk_buff *skb;
2437 int skb_dirtytx;
2438 int tx_ring_size = tx_queue->tx_ring_size;
2439 int frags = 0, nr_txbds = 0;
2440 int i;
2441 int howmany = 0;
2442 u32 lstatus;
2443 size_t buflen;
2444
2445 rx_queue = priv->rx_queue[tx_queue->qindex];
2446 bdp = tx_queue->dirty_tx;
2447 skb_dirtytx = tx_queue->skb_dirtytx;
2448
2449 while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2450 unsigned long flags;
2451
2452 frags = skb_shinfo(skb)->nr_frags;
2453
2454 /*
2455 * When time stamping, one additional TxBD must be freed.
2456 * Also, we need to dma_unmap_single() the TxPAL.
2457 */
2458 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2459 nr_txbds = frags + 2;
2460 else
2461 nr_txbds = frags + 1;
2462
2463 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2464
2465 lstatus = lbdp->lstatus;
2466
2467 /* Only clean completed frames */
2468 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2469 (lstatus & BD_LENGTH_MASK))
2470 break;
2471
2472 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2473 next = next_txbd(bdp, base, tx_ring_size);
2474 buflen = next->length + GMAC_FCB_LEN;
2475 } else
2476 buflen = bdp->length;
2477
2478 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2479 buflen, DMA_TO_DEVICE);
2480
2481 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2482 struct skb_shared_hwtstamps shhwtstamps;
2483 u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2484 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2485 shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2486 skb_tstamp_tx(skb, &shhwtstamps);
2487 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2488 bdp = next;
2489 }
2490
2491 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2492 bdp = next_txbd(bdp, base, tx_ring_size);
2493
2494 for (i = 0; i < frags; i++) {
2495 dma_unmap_page(&priv->ofdev->dev,
2496 bdp->bufPtr,
2497 bdp->length,
2498 DMA_TO_DEVICE);
2499 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2500 bdp = next_txbd(bdp, base, tx_ring_size);
2501 }
2502
2503 /*
2504 * If there's room in the queue (limit it to rx_buffer_size)
2505 * we add this skb back into the pool, if it's the right size
2506 */
2507 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2508 skb_recycle_check(skb, priv->rx_buffer_size +
2509 RXBUF_ALIGNMENT)) {
2510 gfar_align_skb(skb);
2511 skb_queue_head(&priv->rx_recycle, skb);
2512 } else
2513 dev_kfree_skb_any(skb);
2514
2515 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2516
2517 skb_dirtytx = (skb_dirtytx + 1) &
2518 TX_RING_MOD_MASK(tx_ring_size);
2519
2520 howmany++;
2521 spin_lock_irqsave(&tx_queue->txlock, flags);
2522 tx_queue->num_txbdfree += nr_txbds;
2523 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2524 }
2525
2526 /* If we freed a buffer, we can restart transmission, if necessary */
2527 if (__netif_subqueue_stopped(dev, tx_queue->qindex) && tx_queue->num_txbdfree)
2528 netif_wake_subqueue(dev, tx_queue->qindex);
2529
2530 /* Update dirty indicators */
2531 tx_queue->skb_dirtytx = skb_dirtytx;
2532 tx_queue->dirty_tx = bdp;
2533
2534 return howmany;
2535 }
2536
2537 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2538 {
2539 unsigned long flags;
2540
2541 spin_lock_irqsave(&gfargrp->grplock, flags);
2542 if (napi_schedule_prep(&gfargrp->napi)) {
2543 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2544 __napi_schedule(&gfargrp->napi);
2545 } else {
2546 /*
2547 * Clear IEVENT, so interrupts aren't called again
2548 * because of the packets that have already arrived.
2549 */
2550 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2551 }
2552 spin_unlock_irqrestore(&gfargrp->grplock, flags);
2553
2554 }
2555
2556 /* Interrupt Handler for Transmit complete */
2557 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2558 {
2559 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2560 return IRQ_HANDLED;
2561 }
2562
2563 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2564 struct sk_buff *skb)
2565 {
2566 struct net_device *dev = rx_queue->dev;
2567 struct gfar_private *priv = netdev_priv(dev);
2568 dma_addr_t buf;
2569
2570 buf = dma_map_single(&priv->ofdev->dev, skb->data,
2571 priv->rx_buffer_size, DMA_FROM_DEVICE);
2572 gfar_init_rxbdp(rx_queue, bdp, buf);
2573 }
2574
2575 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2576 {
2577 struct gfar_private *priv = netdev_priv(dev);
2578 struct sk_buff *skb = NULL;
2579
2580 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2581 if (!skb)
2582 return NULL;
2583
2584 gfar_align_skb(skb);
2585
2586 return skb;
2587 }
2588
2589 struct sk_buff * gfar_new_skb(struct net_device *dev)
2590 {
2591 struct gfar_private *priv = netdev_priv(dev);
2592 struct sk_buff *skb = NULL;
2593
2594 skb = skb_dequeue(&priv->rx_recycle);
2595 if (!skb)
2596 skb = gfar_alloc_skb(dev);
2597
2598 return skb;
2599 }
2600
2601 static inline void count_errors(unsigned short status, struct net_device *dev)
2602 {
2603 struct gfar_private *priv = netdev_priv(dev);
2604 struct net_device_stats *stats = &dev->stats;
2605 struct gfar_extra_stats *estats = &priv->extra_stats;
2606
2607 /* If the packet was truncated, none of the other errors
2608 * matter */
2609 if (status & RXBD_TRUNCATED) {
2610 stats->rx_length_errors++;
2611
2612 estats->rx_trunc++;
2613
2614 return;
2615 }
2616 /* Count the errors, if there were any */
2617 if (status & (RXBD_LARGE | RXBD_SHORT)) {
2618 stats->rx_length_errors++;
2619
2620 if (status & RXBD_LARGE)
2621 estats->rx_large++;
2622 else
2623 estats->rx_short++;
2624 }
2625 if (status & RXBD_NONOCTET) {
2626 stats->rx_frame_errors++;
2627 estats->rx_nonoctet++;
2628 }
2629 if (status & RXBD_CRCERR) {
2630 estats->rx_crcerr++;
2631 stats->rx_crc_errors++;
2632 }
2633 if (status & RXBD_OVERRUN) {
2634 estats->rx_overrun++;
2635 stats->rx_crc_errors++;
2636 }
2637 }
2638
2639 irqreturn_t gfar_receive(int irq, void *grp_id)
2640 {
2641 gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2642 return IRQ_HANDLED;
2643 }
2644
2645 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2646 {
2647 /* If valid headers were found, and valid sums
2648 * were verified, then we tell the kernel that no
2649 * checksumming is necessary. Otherwise, it is */
2650 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2651 skb->ip_summed = CHECKSUM_UNNECESSARY;
2652 else
2653 skb_checksum_none_assert(skb);
2654 }
2655
2656
2657 /* gfar_process_frame() -- handle one incoming packet if skb
2658 * isn't NULL. */
2659 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2660 int amount_pull)
2661 {
2662 struct gfar_private *priv = netdev_priv(dev);
2663 struct rxfcb *fcb = NULL;
2664
2665 int ret;
2666
2667 /* fcb is at the beginning if exists */
2668 fcb = (struct rxfcb *)skb->data;
2669
2670 /* Remove the FCB from the skb */
2671 /* Remove the padded bytes, if there are any */
2672 if (amount_pull) {
2673 skb_record_rx_queue(skb, fcb->rq);
2674 skb_pull(skb, amount_pull);
2675 }
2676
2677 /* Get receive timestamp from the skb */
2678 if (priv->hwts_rx_en) {
2679 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2680 u64 *ns = (u64 *) skb->data;
2681 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2682 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2683 }
2684
2685 if (priv->padding)
2686 skb_pull(skb, priv->padding);
2687
2688 if (priv->rx_csum_enable)
2689 gfar_rx_checksum(skb, fcb);
2690
2691 /* Tell the skb what kind of packet this is */
2692 skb->protocol = eth_type_trans(skb, dev);
2693
2694 /* Send the packet up the stack */
2695 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN)))
2696 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp, fcb->vlctl);
2697 else
2698 ret = netif_receive_skb(skb);
2699
2700 if (NET_RX_DROP == ret)
2701 priv->extra_stats.kernel_dropped++;
2702
2703 return 0;
2704 }
2705
2706 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2707 * until the budget/quota has been reached. Returns the number
2708 * of frames handled
2709 */
2710 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2711 {
2712 struct net_device *dev = rx_queue->dev;
2713 struct rxbd8 *bdp, *base;
2714 struct sk_buff *skb;
2715 int pkt_len;
2716 int amount_pull;
2717 int howmany = 0;
2718 struct gfar_private *priv = netdev_priv(dev);
2719
2720 /* Get the first full descriptor */
2721 bdp = rx_queue->cur_rx;
2722 base = rx_queue->rx_bd_base;
2723
2724 amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2725
2726 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2727 struct sk_buff *newskb;
2728 rmb();
2729
2730 /* Add another skb for the future */
2731 newskb = gfar_new_skb(dev);
2732
2733 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2734
2735 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2736 priv->rx_buffer_size, DMA_FROM_DEVICE);
2737
2738 if (unlikely(!(bdp->status & RXBD_ERR) &&
2739 bdp->length > priv->rx_buffer_size))
2740 bdp->status = RXBD_LARGE;
2741
2742 /* We drop the frame if we failed to allocate a new buffer */
2743 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2744 bdp->status & RXBD_ERR)) {
2745 count_errors(bdp->status, dev);
2746
2747 if (unlikely(!newskb))
2748 newskb = skb;
2749 else if (skb)
2750 skb_queue_head(&priv->rx_recycle, skb);
2751 } else {
2752 /* Increment the number of packets */
2753 rx_queue->stats.rx_packets++;
2754 howmany++;
2755
2756 if (likely(skb)) {
2757 pkt_len = bdp->length - ETH_FCS_LEN;
2758 /* Remove the FCS from the packet length */
2759 skb_put(skb, pkt_len);
2760 rx_queue->stats.rx_bytes += pkt_len;
2761 skb_record_rx_queue(skb, rx_queue->qindex);
2762 gfar_process_frame(dev, skb, amount_pull);
2763
2764 } else {
2765 if (netif_msg_rx_err(priv))
2766 printk(KERN_WARNING
2767 "%s: Missing skb!\n", dev->name);
2768 rx_queue->stats.rx_dropped++;
2769 priv->extra_stats.rx_skbmissing++;
2770 }
2771
2772 }
2773
2774 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2775
2776 /* Setup the new bdp */
2777 gfar_new_rxbdp(rx_queue, bdp, newskb);
2778
2779 /* Update to the next pointer */
2780 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2781
2782 /* update to point at the next skb */
2783 rx_queue->skb_currx =
2784 (rx_queue->skb_currx + 1) &
2785 RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2786 }
2787
2788 /* Update the current rxbd pointer to be the next one */
2789 rx_queue->cur_rx = bdp;
2790
2791 return howmany;
2792 }
2793
2794 static int gfar_poll(struct napi_struct *napi, int budget)
2795 {
2796 struct gfar_priv_grp *gfargrp = container_of(napi,
2797 struct gfar_priv_grp, napi);
2798 struct gfar_private *priv = gfargrp->priv;
2799 struct gfar __iomem *regs = gfargrp->regs;
2800 struct gfar_priv_tx_q *tx_queue = NULL;
2801 struct gfar_priv_rx_q *rx_queue = NULL;
2802 int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2803 int tx_cleaned = 0, i, left_over_budget = budget;
2804 unsigned long serviced_queues = 0;
2805 int num_queues = 0;
2806
2807 num_queues = gfargrp->num_rx_queues;
2808 budget_per_queue = budget/num_queues;
2809
2810 /* Clear IEVENT, so interrupts aren't called again
2811 * because of the packets that have already arrived */
2812 gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2813
2814 while (num_queues && left_over_budget) {
2815
2816 budget_per_queue = left_over_budget/num_queues;
2817 left_over_budget = 0;
2818
2819 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2820 if (test_bit(i, &serviced_queues))
2821 continue;
2822 rx_queue = priv->rx_queue[i];
2823 tx_queue = priv->tx_queue[rx_queue->qindex];
2824
2825 tx_cleaned += gfar_clean_tx_ring(tx_queue);
2826 rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2827 budget_per_queue);
2828 rx_cleaned += rx_cleaned_per_queue;
2829 if(rx_cleaned_per_queue < budget_per_queue) {
2830 left_over_budget = left_over_budget +
2831 (budget_per_queue - rx_cleaned_per_queue);
2832 set_bit(i, &serviced_queues);
2833 num_queues--;
2834 }
2835 }
2836 }
2837
2838 if (tx_cleaned)
2839 return budget;
2840
2841 if (rx_cleaned < budget) {
2842 napi_complete(napi);
2843
2844 /* Clear the halt bit in RSTAT */
2845 gfar_write(&regs->rstat, gfargrp->rstat);
2846
2847 gfar_write(&regs->imask, IMASK_DEFAULT);
2848
2849 /* If we are coalescing interrupts, update the timer */
2850 /* Otherwise, clear it */
2851 gfar_configure_coalescing(priv,
2852 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2853 }
2854
2855 return rx_cleaned;
2856 }
2857
2858 #ifdef CONFIG_NET_POLL_CONTROLLER
2859 /*
2860 * Polling 'interrupt' - used by things like netconsole to send skbs
2861 * without having to re-enable interrupts. It's not called while
2862 * the interrupt routine is executing.
2863 */
2864 static void gfar_netpoll(struct net_device *dev)
2865 {
2866 struct gfar_private *priv = netdev_priv(dev);
2867 int i = 0;
2868
2869 /* If the device has multiple interrupts, run tx/rx */
2870 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2871 for (i = 0; i < priv->num_grps; i++) {
2872 disable_irq(priv->gfargrp[i].interruptTransmit);
2873 disable_irq(priv->gfargrp[i].interruptReceive);
2874 disable_irq(priv->gfargrp[i].interruptError);
2875 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2876 &priv->gfargrp[i]);
2877 enable_irq(priv->gfargrp[i].interruptError);
2878 enable_irq(priv->gfargrp[i].interruptReceive);
2879 enable_irq(priv->gfargrp[i].interruptTransmit);
2880 }
2881 } else {
2882 for (i = 0; i < priv->num_grps; i++) {
2883 disable_irq(priv->gfargrp[i].interruptTransmit);
2884 gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2885 &priv->gfargrp[i]);
2886 enable_irq(priv->gfargrp[i].interruptTransmit);
2887 }
2888 }
2889 }
2890 #endif
2891
2892 /* The interrupt handler for devices with one interrupt */
2893 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2894 {
2895 struct gfar_priv_grp *gfargrp = grp_id;
2896
2897 /* Save ievent for future reference */
2898 u32 events = gfar_read(&gfargrp->regs->ievent);
2899
2900 /* Check for reception */
2901 if (events & IEVENT_RX_MASK)
2902 gfar_receive(irq, grp_id);
2903
2904 /* Check for transmit completion */
2905 if (events & IEVENT_TX_MASK)
2906 gfar_transmit(irq, grp_id);
2907
2908 /* Check for errors */
2909 if (events & IEVENT_ERR_MASK)
2910 gfar_error(irq, grp_id);
2911
2912 return IRQ_HANDLED;
2913 }
2914
2915 /* Called every time the controller might need to be made
2916 * aware of new link state. The PHY code conveys this
2917 * information through variables in the phydev structure, and this
2918 * function converts those variables into the appropriate
2919 * register values, and can bring down the device if needed.
2920 */
2921 static void adjust_link(struct net_device *dev)
2922 {
2923 struct gfar_private *priv = netdev_priv(dev);
2924 struct gfar __iomem *regs = priv->gfargrp[0].regs;
2925 unsigned long flags;
2926 struct phy_device *phydev = priv->phydev;
2927 int new_state = 0;
2928
2929 local_irq_save(flags);
2930 lock_tx_qs(priv);
2931
2932 if (phydev->link) {
2933 u32 tempval = gfar_read(&regs->maccfg2);
2934 u32 ecntrl = gfar_read(&regs->ecntrl);
2935
2936 /* Now we make sure that we can be in full duplex mode.
2937 * If not, we operate in half-duplex mode. */
2938 if (phydev->duplex != priv->oldduplex) {
2939 new_state = 1;
2940 if (!(phydev->duplex))
2941 tempval &= ~(MACCFG2_FULL_DUPLEX);
2942 else
2943 tempval |= MACCFG2_FULL_DUPLEX;
2944
2945 priv->oldduplex = phydev->duplex;
2946 }
2947
2948 if (phydev->speed != priv->oldspeed) {
2949 new_state = 1;
2950 switch (phydev->speed) {
2951 case 1000:
2952 tempval =
2953 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2954
2955 ecntrl &= ~(ECNTRL_R100);
2956 break;
2957 case 100:
2958 case 10:
2959 tempval =
2960 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2961
2962 /* Reduced mode distinguishes
2963 * between 10 and 100 */
2964 if (phydev->speed == SPEED_100)
2965 ecntrl |= ECNTRL_R100;
2966 else
2967 ecntrl &= ~(ECNTRL_R100);
2968 break;
2969 default:
2970 if (netif_msg_link(priv))
2971 printk(KERN_WARNING
2972 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
2973 dev->name, phydev->speed);
2974 break;
2975 }
2976
2977 priv->oldspeed = phydev->speed;
2978 }
2979
2980 gfar_write(&regs->maccfg2, tempval);
2981 gfar_write(&regs->ecntrl, ecntrl);
2982
2983 if (!priv->oldlink) {
2984 new_state = 1;
2985 priv->oldlink = 1;
2986 }
2987 } else if (priv->oldlink) {
2988 new_state = 1;
2989 priv->oldlink = 0;
2990 priv->oldspeed = 0;
2991 priv->oldduplex = -1;
2992 }
2993
2994 if (new_state && netif_msg_link(priv))
2995 phy_print_status(phydev);
2996 unlock_tx_qs(priv);
2997 local_irq_restore(flags);
2998 }
2999
3000 /* Update the hash table based on the current list of multicast
3001 * addresses we subscribe to. Also, change the promiscuity of
3002 * the device based on the flags (this function is called
3003 * whenever dev->flags is changed */
3004 static void gfar_set_multi(struct net_device *dev)
3005 {
3006 struct netdev_hw_addr *ha;
3007 struct gfar_private *priv = netdev_priv(dev);
3008 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3009 u32 tempval;
3010
3011 if (dev->flags & IFF_PROMISC) {
3012 /* Set RCTRL to PROM */
3013 tempval = gfar_read(&regs->rctrl);
3014 tempval |= RCTRL_PROM;
3015 gfar_write(&regs->rctrl, tempval);
3016 } else {
3017 /* Set RCTRL to not PROM */
3018 tempval = gfar_read(&regs->rctrl);
3019 tempval &= ~(RCTRL_PROM);
3020 gfar_write(&regs->rctrl, tempval);
3021 }
3022
3023 if (dev->flags & IFF_ALLMULTI) {
3024 /* Set the hash to rx all multicast frames */
3025 gfar_write(&regs->igaddr0, 0xffffffff);
3026 gfar_write(&regs->igaddr1, 0xffffffff);
3027 gfar_write(&regs->igaddr2, 0xffffffff);
3028 gfar_write(&regs->igaddr3, 0xffffffff);
3029 gfar_write(&regs->igaddr4, 0xffffffff);
3030 gfar_write(&regs->igaddr5, 0xffffffff);
3031 gfar_write(&regs->igaddr6, 0xffffffff);
3032 gfar_write(&regs->igaddr7, 0xffffffff);
3033 gfar_write(&regs->gaddr0, 0xffffffff);
3034 gfar_write(&regs->gaddr1, 0xffffffff);
3035 gfar_write(&regs->gaddr2, 0xffffffff);
3036 gfar_write(&regs->gaddr3, 0xffffffff);
3037 gfar_write(&regs->gaddr4, 0xffffffff);
3038 gfar_write(&regs->gaddr5, 0xffffffff);
3039 gfar_write(&regs->gaddr6, 0xffffffff);
3040 gfar_write(&regs->gaddr7, 0xffffffff);
3041 } else {
3042 int em_num;
3043 int idx;
3044
3045 /* zero out the hash */
3046 gfar_write(&regs->igaddr0, 0x0);
3047 gfar_write(&regs->igaddr1, 0x0);
3048 gfar_write(&regs->igaddr2, 0x0);
3049 gfar_write(&regs->igaddr3, 0x0);
3050 gfar_write(&regs->igaddr4, 0x0);
3051 gfar_write(&regs->igaddr5, 0x0);
3052 gfar_write(&regs->igaddr6, 0x0);
3053 gfar_write(&regs->igaddr7, 0x0);
3054 gfar_write(&regs->gaddr0, 0x0);
3055 gfar_write(&regs->gaddr1, 0x0);
3056 gfar_write(&regs->gaddr2, 0x0);
3057 gfar_write(&regs->gaddr3, 0x0);
3058 gfar_write(&regs->gaddr4, 0x0);
3059 gfar_write(&regs->gaddr5, 0x0);
3060 gfar_write(&regs->gaddr6, 0x0);
3061 gfar_write(&regs->gaddr7, 0x0);
3062
3063 /* If we have extended hash tables, we need to
3064 * clear the exact match registers to prepare for
3065 * setting them */
3066 if (priv->extended_hash) {
3067 em_num = GFAR_EM_NUM + 1;
3068 gfar_clear_exact_match(dev);
3069 idx = 1;
3070 } else {
3071 idx = 0;
3072 em_num = 0;
3073 }
3074
3075 if (netdev_mc_empty(dev))
3076 return;
3077
3078 /* Parse the list, and set the appropriate bits */
3079 netdev_for_each_mc_addr(ha, dev) {
3080 if (idx < em_num) {
3081 gfar_set_mac_for_addr(dev, idx, ha->addr);
3082 idx++;
3083 } else
3084 gfar_set_hash_for_addr(dev, ha->addr);
3085 }
3086 }
3087 }
3088
3089
3090 /* Clears each of the exact match registers to zero, so they
3091 * don't interfere with normal reception */
3092 static void gfar_clear_exact_match(struct net_device *dev)
3093 {
3094 int idx;
3095 static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
3096
3097 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3098 gfar_set_mac_for_addr(dev, idx, zero_arr);
3099 }
3100
3101 /* Set the appropriate hash bit for the given addr */
3102 /* The algorithm works like so:
3103 * 1) Take the Destination Address (ie the multicast address), and
3104 * do a CRC on it (little endian), and reverse the bits of the
3105 * result.
3106 * 2) Use the 8 most significant bits as a hash into a 256-entry
3107 * table. The table is controlled through 8 32-bit registers:
3108 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
3109 * gaddr7. This means that the 3 most significant bits in the
3110 * hash index which gaddr register to use, and the 5 other bits
3111 * indicate which bit (assuming an IBM numbering scheme, which
3112 * for PowerPC (tm) is usually the case) in the register holds
3113 * the entry. */
3114 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3115 {
3116 u32 tempval;
3117 struct gfar_private *priv = netdev_priv(dev);
3118 u32 result = ether_crc(MAC_ADDR_LEN, addr);
3119 int width = priv->hash_width;
3120 u8 whichbit = (result >> (32 - width)) & 0x1f;
3121 u8 whichreg = result >> (32 - width + 5);
3122 u32 value = (1 << (31-whichbit));
3123
3124 tempval = gfar_read(priv->hash_regs[whichreg]);
3125 tempval |= value;
3126 gfar_write(priv->hash_regs[whichreg], tempval);
3127 }
3128
3129
3130 /* There are multiple MAC Address register pairs on some controllers
3131 * This function sets the numth pair to a given address
3132 */
3133 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3134 const u8 *addr)
3135 {
3136 struct gfar_private *priv = netdev_priv(dev);
3137 struct gfar __iomem *regs = priv->gfargrp[0].regs;
3138 int idx;
3139 char tmpbuf[MAC_ADDR_LEN];
3140 u32 tempval;
3141 u32 __iomem *macptr = &regs->macstnaddr1;
3142
3143 macptr += num*2;
3144
3145 /* Now copy it into the mac registers backwards, cuz */
3146 /* little endian is silly */
3147 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
3148 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
3149
3150 gfar_write(macptr, *((u32 *) (tmpbuf)));
3151
3152 tempval = *((u32 *) (tmpbuf + 4));
3153
3154 gfar_write(macptr+1, tempval);
3155 }
3156
3157 /* GFAR error interrupt handler */
3158 static irqreturn_t gfar_error(int irq, void *grp_id)
3159 {
3160 struct gfar_priv_grp *gfargrp = grp_id;
3161 struct gfar __iomem *regs = gfargrp->regs;
3162 struct gfar_private *priv= gfargrp->priv;
3163 struct net_device *dev = priv->ndev;
3164
3165 /* Save ievent for future reference */
3166 u32 events = gfar_read(&regs->ievent);
3167
3168 /* Clear IEVENT */
3169 gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3170
3171 /* Magic Packet is not an error. */
3172 if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3173 (events & IEVENT_MAG))
3174 events &= ~IEVENT_MAG;
3175
3176 /* Hmm... */
3177 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3178 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
3179 dev->name, events, gfar_read(&regs->imask));
3180
3181 /* Update the error counters */
3182 if (events & IEVENT_TXE) {
3183 dev->stats.tx_errors++;
3184
3185 if (events & IEVENT_LC)
3186 dev->stats.tx_window_errors++;
3187 if (events & IEVENT_CRL)
3188 dev->stats.tx_aborted_errors++;
3189 if (events & IEVENT_XFUN) {
3190 unsigned long flags;
3191
3192 if (netif_msg_tx_err(priv))
3193 printk(KERN_DEBUG "%s: TX FIFO underrun, "
3194 "packet dropped.\n", dev->name);
3195 dev->stats.tx_dropped++;
3196 priv->extra_stats.tx_underrun++;
3197
3198 local_irq_save(flags);
3199 lock_tx_qs(priv);
3200
3201 /* Reactivate the Tx Queues */
3202 gfar_write(&regs->tstat, gfargrp->tstat);
3203
3204 unlock_tx_qs(priv);
3205 local_irq_restore(flags);
3206 }
3207 if (netif_msg_tx_err(priv))
3208 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
3209 }
3210 if (events & IEVENT_BSY) {
3211 dev->stats.rx_errors++;
3212 priv->extra_stats.rx_bsy++;
3213
3214 gfar_receive(irq, grp_id);
3215
3216 if (netif_msg_rx_err(priv))
3217 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
3218 dev->name, gfar_read(&regs->rstat));
3219 }
3220 if (events & IEVENT_BABR) {
3221 dev->stats.rx_errors++;
3222 priv->extra_stats.rx_babr++;
3223
3224 if (netif_msg_rx_err(priv))
3225 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
3226 }
3227 if (events & IEVENT_EBERR) {
3228 priv->extra_stats.eberr++;
3229 if (netif_msg_rx_err(priv))
3230 printk(KERN_DEBUG "%s: bus error\n", dev->name);
3231 }
3232 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
3233 printk(KERN_DEBUG "%s: control frame\n", dev->name);
3234
3235 if (events & IEVENT_BABT) {
3236 priv->extra_stats.tx_babt++;
3237 if (netif_msg_tx_err(priv))
3238 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
3239 }
3240 return IRQ_HANDLED;
3241 }
3242
3243 static struct of_device_id gfar_match[] =
3244 {
3245 {
3246 .type = "network",
3247 .compatible = "gianfar",
3248 },
3249 {
3250 .compatible = "fsl,etsec2",
3251 },
3252 {},
3253 };
3254 MODULE_DEVICE_TABLE(of, gfar_match);
3255
3256 /* Structure for a device driver */
3257 static struct platform_driver gfar_driver = {
3258 .driver = {
3259 .name = "fsl-gianfar",
3260 .owner = THIS_MODULE,
3261 .pm = GFAR_PM_OPS,
3262 .of_match_table = gfar_match,
3263 },
3264 .probe = gfar_probe,
3265 .remove = gfar_remove,
3266 };
3267
3268 static int __init gfar_init(void)
3269 {
3270 return platform_driver_register(&gfar_driver);
3271 }
3272
3273 static void __exit gfar_exit(void)
3274 {
3275 platform_driver_unregister(&gfar_driver);
3276 }
3277
3278 module_init(gfar_init);
3279 module_exit(gfar_exit);
3280
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree