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[PATCH] xtensa: Fix TIOCGICOUNT macro
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / include / asm-mips / stackframe.h
blobc4856a874965f3ad851808c9ec7886fd45bcd2a7
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
7 * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
8 * Copyright (C) 1999 Silicon Graphics, Inc.
9 */
10 #ifndef _ASM_STACKFRAME_H
11 #define _ASM_STACKFRAME_H
12
13 #include <linux/config.h>
14 #include <linux/threads.h>
15
16 #include <asm/asm.h>
17 #include <asm/asmmacro.h>
18 #include <asm/mipsregs.h>
19 #include <asm/asm-offsets.h>
20
21 #ifdef CONFIG_MIPS_MT_SMTC
22 #include <asm/mipsmtregs.h>
23 #endif /* CONFIG_MIPS_MT_SMTC */
24
25 .macro SAVE_AT
26 .set push
27 .set noat
28 LONG_S $1, PT_R1(sp)
29 .set pop
30 .endm
31
32 .macro SAVE_TEMP
33 mfhi v1
34 #ifdef CONFIG_32BIT
35 LONG_S $8, PT_R8(sp)
36 LONG_S $9, PT_R9(sp)
37 #endif
38 LONG_S v1, PT_HI(sp)
39 mflo v1
40 LONG_S $10, PT_R10(sp)
41 LONG_S $11, PT_R11(sp)
42 LONG_S v1, PT_LO(sp)
43 LONG_S $12, PT_R12(sp)
44 LONG_S $13, PT_R13(sp)
45 LONG_S $14, PT_R14(sp)
46 LONG_S $15, PT_R15(sp)
47 LONG_S $24, PT_R24(sp)
48 .endm
49
50 .macro SAVE_STATIC
51 LONG_S $16, PT_R16(sp)
52 LONG_S $17, PT_R17(sp)
53 LONG_S $18, PT_R18(sp)
54 LONG_S $19, PT_R19(sp)
55 LONG_S $20, PT_R20(sp)
56 LONG_S $21, PT_R21(sp)
57 LONG_S $22, PT_R22(sp)
58 LONG_S $23, PT_R23(sp)
59 LONG_S $30, PT_R30(sp)
60 .endm
61
62 #ifdef CONFIG_SMP
63 .macro get_saved_sp /* SMP variation */
64 #ifdef CONFIG_32BIT
65 #ifdef CONFIG_MIPS_MT_SMTC
66 .set mips32
67 mfc0 k0, CP0_TCBIND;
68 .set mips0
69 lui k1, %hi(kernelsp)
70 srl k0, k0, 19
71 /* No need to shift down and up to clear bits 0-1 */
72 #else
73 mfc0 k0, CP0_CONTEXT
74 lui k1, %hi(kernelsp)
75 srl k0, k0, 23
76 #endif
77 addu k1, k0
78 LONG_L k1, %lo(kernelsp)(k1)
79 #endif
80 #ifdef CONFIG_64BIT
81 #ifdef CONFIG_MIPS_MT_SMTC
82 .set mips64
83 mfc0 k0, CP0_TCBIND;
84 .set mips0
85 lui k0, %highest(kernelsp)
86 dsrl k1, 19
87 /* No need to shift down and up to clear bits 0-2 */
88 #else
89 MFC0 k1, CP0_CONTEXT
90 lui k0, %highest(kernelsp)
91 dsrl k1, 23
92 daddiu k0, %higher(kernelsp)
93 dsll k0, k0, 16
94 daddiu k0, %hi(kernelsp)
95 dsll k0, k0, 16
96 #endif /* CONFIG_MIPS_MT_SMTC */
97 daddu k1, k1, k0
98 LONG_L k1, %lo(kernelsp)(k1)
99 #endif /* CONFIG_64BIT */
100 .endm
101
102 .macro set_saved_sp stackp temp temp2
103 #ifdef CONFIG_32BIT
104 #ifdef CONFIG_MIPS_MT_SMTC
105 mfc0 \temp, CP0_TCBIND
106 srl \temp, 19
107 #else
108 mfc0 \temp, CP0_CONTEXT
109 srl \temp, 23
110 #endif
111 #endif
112 #ifdef CONFIG_64BIT
113 #ifdef CONFIG_MIPS_MT_SMTC
114 mfc0 \temp, CP0_TCBIND
115 dsrl \temp, 19
116 #else
117 MFC0 \temp, CP0_CONTEXT
118 dsrl \temp, 23
119 #endif
120 #endif
121 LONG_S \stackp, kernelsp(\temp)
122 .endm
123 #else
124 .macro get_saved_sp /* Uniprocessor variation */
125 #ifdef CONFIG_64BIT
126 lui k1, %highest(kernelsp)
127 daddiu k1, %higher(kernelsp)
128 dsll k1, k1, 16
129 daddiu k1, %hi(kernelsp)
130 dsll k1, k1, 16
131 #else
132 lui k1, %hi(kernelsp)
133 #endif
134 LONG_L k1, %lo(kernelsp)(k1)
135 .endm
136
137 .macro set_saved_sp stackp temp temp2
138 LONG_S \stackp, kernelsp
139 .endm
140 #endif
141
142 .macro SAVE_SOME
143 .set push
144 .set noat
145 .set reorder
146 mfc0 k0, CP0_STATUS
147 sll k0, 3 /* extract cu0 bit */
148 .set noreorder
149 bltz k0, 8f
150 move k1, sp
151 .set reorder
152 /* Called from user mode, new stack. */
153 get_saved_sp
154 8: move k0, sp
155 PTR_SUBU sp, k1, PT_SIZE
156 LONG_S k0, PT_R29(sp)
157 LONG_S $3, PT_R3(sp)
158 /*
159 * You might think that you don't need to save $0,
160 * but the FPU emulator and gdb remote debug stub
161 * need it to operate correctly
162 */
163 LONG_S $0, PT_R0(sp)
164 mfc0 v1, CP0_STATUS
165 LONG_S $2, PT_R2(sp)
166 LONG_S v1, PT_STATUS(sp)
167 #ifdef CONFIG_MIPS_MT_SMTC
168 /*
169 * Ideally, these instructions would be shuffled in
170 * to cover the pipeline delay.
171 */
172 .set mips32
173 mfc0 v1, CP0_TCSTATUS
174 .set mips0
175 LONG_S v1, PT_TCSTATUS(sp)
176 #endif /* CONFIG_MIPS_MT_SMTC */
177 LONG_S $4, PT_R4(sp)
178 mfc0 v1, CP0_CAUSE
179 LONG_S $5, PT_R5(sp)
180 LONG_S v1, PT_CAUSE(sp)
181 LONG_S $6, PT_R6(sp)
182 MFC0 v1, CP0_EPC
183 LONG_S $7, PT_R7(sp)
184 #ifdef CONFIG_64BIT
185 LONG_S $8, PT_R8(sp)
186 LONG_S $9, PT_R9(sp)
187 #endif
188 LONG_S v1, PT_EPC(sp)
189 LONG_S $25, PT_R25(sp)
190 LONG_S $28, PT_R28(sp)
191 LONG_S $31, PT_R31(sp)
192 ori $28, sp, _THREAD_MASK
193 xori $28, _THREAD_MASK
194 .set pop
195 .endm
196
197 .macro SAVE_ALL
198 SAVE_SOME
199 SAVE_AT
200 SAVE_TEMP
201 SAVE_STATIC
202 .endm
203
204 .macro RESTORE_AT
205 .set push
206 .set noat
207 LONG_L $1, PT_R1(sp)
208 .set pop
209 .endm
210
211 .macro RESTORE_TEMP
212 LONG_L $24, PT_LO(sp)
213 #ifdef CONFIG_32BIT
214 LONG_L $8, PT_R8(sp)
215 LONG_L $9, PT_R9(sp)
216 #endif
217 mtlo $24
218 LONG_L $24, PT_HI(sp)
219 LONG_L $10, PT_R10(sp)
220 LONG_L $11, PT_R11(sp)
221 mthi $24
222 LONG_L $12, PT_R12(sp)
223 LONG_L $13, PT_R13(sp)
224 LONG_L $14, PT_R14(sp)
225 LONG_L $15, PT_R15(sp)
226 LONG_L $24, PT_R24(sp)
227 .endm
228
229 .macro RESTORE_STATIC
230 LONG_L $16, PT_R16(sp)
231 LONG_L $17, PT_R17(sp)
232 LONG_L $18, PT_R18(sp)
233 LONG_L $19, PT_R19(sp)
234 LONG_L $20, PT_R20(sp)
235 LONG_L $21, PT_R21(sp)
236 LONG_L $22, PT_R22(sp)
237 LONG_L $23, PT_R23(sp)
238 LONG_L $30, PT_R30(sp)
239 .endm
240
241 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
242
243 .macro RESTORE_SOME
244 .set push
245 .set reorder
246 .set noat
247 mfc0 a0, CP0_STATUS
248 ori a0, 0x1f
249 xori a0, 0x1f
250 mtc0 a0, CP0_STATUS
251 li v1, 0xff00
252 and a0, v1
253 LONG_L v0, PT_STATUS(sp)
254 nor v1, $0, v1
255 and v0, v1
256 or v0, a0
257 mtc0 v0, CP0_STATUS
258 LONG_L $31, PT_R31(sp)
259 LONG_L $28, PT_R28(sp)
260 LONG_L $25, PT_R25(sp)
261 #ifdef CONFIG_64BIT
262 LONG_L $8, PT_R8(sp)
263 LONG_L $9, PT_R9(sp)
264 #endif
265 LONG_L $7, PT_R7(sp)
266 LONG_L $6, PT_R6(sp)
267 LONG_L $5, PT_R5(sp)
268 LONG_L $4, PT_R4(sp)
269 LONG_L $3, PT_R3(sp)
270 LONG_L $2, PT_R2(sp)
271 .set pop
272 .endm
273
274 .macro RESTORE_SP_AND_RET
275 .set push
276 .set noreorder
277 LONG_L k0, PT_EPC(sp)
278 LONG_L sp, PT_R29(sp)
279 jr k0
280 rfe
281 .set pop
282 .endm
283
284 #else
285 /*
286 * For SMTC kernel, global IE should be left set, and interrupts
287 * controlled exclusively via IXMT.
288 */
289
290 #ifdef CONFIG_MIPS_MT_SMTC
291 #define STATMASK 0x1e
292 #else
293 #define STATMASK 0x1f
294 #endif
295 .macro RESTORE_SOME
296 .set push
297 .set reorder
298 .set noat
299 #ifdef CONFIG_MIPS_MT_SMTC
300 .set mips32r2
301 /*
302 * This may not really be necessary if ints are already
303 * inhibited here.
304 */
305 mfc0 v0, CP0_TCSTATUS
306 ori v0, TCSTATUS_IXMT
307 mtc0 v0, CP0_TCSTATUS
308 ehb
309 DMT 5 # dmt a1
310 jal mips_ihb
311 #endif /* CONFIG_MIPS_MT_SMTC */
312 mfc0 a0, CP0_STATUS
313 ori a0, STATMASK
314 xori a0, STATMASK
315 mtc0 a0, CP0_STATUS
316 li v1, 0xff00
317 and a0, v1
318 LONG_L v0, PT_STATUS(sp)
319 nor v1, $0, v1
320 and v0, v1
321 or v0, a0
322 mtc0 v0, CP0_STATUS
323 #ifdef CONFIG_MIPS_MT_SMTC
324 /*
325 * Only after EXL/ERL have been restored to status can we
326 * restore TCStatus.IXMT.
327 */
328 LONG_L v1, PT_TCSTATUS(sp)
329 ehb
330 mfc0 v0, CP0_TCSTATUS
331 andi v1, TCSTATUS_IXMT
332 /* We know that TCStatua.IXMT should be set from above */
333 xori v0, v0, TCSTATUS_IXMT
334 or v0, v0, v1
335 mtc0 v0, CP0_TCSTATUS
336 ehb
337 andi a1, a1, VPECONTROL_TE
338 beqz a1, 1f
339 emt
340 1:
341 .set mips0
342 #endif /* CONFIG_MIPS_MT_SMTC */
343 LONG_L v1, PT_EPC(sp)
344 MTC0 v1, CP0_EPC
345 LONG_L $31, PT_R31(sp)
346 LONG_L $28, PT_R28(sp)
347 LONG_L $25, PT_R25(sp)
348 #ifdef CONFIG_64BIT
349 LONG_L $8, PT_R8(sp)
350 LONG_L $9, PT_R9(sp)
351 #endif
352 LONG_L $7, PT_R7(sp)
353 LONG_L $6, PT_R6(sp)
354 LONG_L $5, PT_R5(sp)
355 LONG_L $4, PT_R4(sp)
356 LONG_L $3, PT_R3(sp)
357 LONG_L $2, PT_R2(sp)
358 .set pop
359 .endm
360
361 .macro RESTORE_SP_AND_RET
362 LONG_L sp, PT_R29(sp)
363 .set mips3
364 eret
365 .set mips0
366 .endm
367
368 #endif
369
370 .macro RESTORE_SP
371 LONG_L sp, PT_R29(sp)
372 .endm
373
374 .macro RESTORE_ALL
375 RESTORE_TEMP
376 RESTORE_STATIC
377 RESTORE_AT
378 RESTORE_SOME
379 RESTORE_SP
380 .endm
381
382 .macro RESTORE_ALL_AND_RET
383 RESTORE_TEMP
384 RESTORE_STATIC
385 RESTORE_AT
386 RESTORE_SOME
387 RESTORE_SP_AND_RET
388 .endm
389
390 /*
391 * Move to kernel mode and disable interrupts.
392 * Set cp0 enable bit as sign that we're running on the kernel stack
393 */
394 .macro CLI
395 #if !defined(CONFIG_MIPS_MT_SMTC)
396 mfc0 t0, CP0_STATUS
397 li t1, ST0_CU0 | 0x1f
398 or t0, t1
399 xori t0, 0x1f
400 mtc0 t0, CP0_STATUS
401 #else /* CONFIG_MIPS_MT_SMTC */
402 /*
403 * For SMTC, we need to set privilege
404 * and disable interrupts only for the
405 * current TC, using the TCStatus register.
406 */
407 mfc0 t0,CP0_TCSTATUS
408 /* Fortunately CU 0 is in the same place in both registers */
409 /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
410 li t1, ST0_CU0 | 0x08001c00
411 or t0,t1
412 /* Clear TKSU, leave IXMT */
413 xori t0, 0x00001800
414 mtc0 t0, CP0_TCSTATUS
415 ehb
416 /* We need to leave the global IE bit set, but clear EXL...*/
417 mfc0 t0, CP0_STATUS
418 ori t0, ST0_EXL | ST0_ERL
419 xori t0, ST0_EXL | ST0_ERL
420 mtc0 t0, CP0_STATUS
421 #endif /* CONFIG_MIPS_MT_SMTC */
422 irq_disable_hazard
423 .endm
424
425 /*
426 * Move to kernel mode and enable interrupts.
427 * Set cp0 enable bit as sign that we're running on the kernel stack
428 */
429 .macro STI
430 #if !defined(CONFIG_MIPS_MT_SMTC)
431 mfc0 t0, CP0_STATUS
432 li t1, ST0_CU0 | 0x1f
433 or t0, t1
434 xori t0, 0x1e
435 mtc0 t0, CP0_STATUS
436 #else /* CONFIG_MIPS_MT_SMTC */
437 /*
438 * For SMTC, we need to set privilege
439 * and enable interrupts only for the
440 * current TC, using the TCStatus register.
441 */
442 ehb
443 mfc0 t0,CP0_TCSTATUS
444 /* Fortunately CU 0 is in the same place in both registers */
445 /* Set TCU0, TKSU (for later inversion) and IXMT */
446 li t1, ST0_CU0 | 0x08001c00
447 or t0,t1
448 /* Clear TKSU *and* IXMT */
449 xori t0, 0x00001c00
450 mtc0 t0, CP0_TCSTATUS
451 ehb
452 /* We need to leave the global IE bit set, but clear EXL...*/
453 mfc0 t0, CP0_STATUS
454 ori t0, ST0_EXL
455 xori t0, ST0_EXL
456 mtc0 t0, CP0_STATUS
457 /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
458 #endif /* CONFIG_MIPS_MT_SMTC */
459 irq_enable_hazard
460 .endm
461
462 /*
463 * Just move to kernel mode and leave interrupts as they are.
464 * Set cp0 enable bit as sign that we're running on the kernel stack
465 */
466 .macro KMODE
467 #ifdef CONFIG_MIPS_MT_SMTC
468 /*
469 * This gets baroque in SMTC. We want to
470 * protect the non-atomic clearing of EXL
471 * with DMT/EMT, but we don't want to take
472 * an interrupt while DMT is still in effect.
473 */
474
475 /* KMODE gets invoked from both reorder and noreorder code */
476 .set push
477 .set mips32r2
478 .set noreorder
479 mfc0 v0, CP0_TCSTATUS
480 andi v1, v0, TCSTATUS_IXMT
481 ori v0, TCSTATUS_IXMT
482 mtc0 v0, CP0_TCSTATUS
483 ehb
484 DMT 2 # dmt v0
485 /*
486 * We don't know a priori if ra is "live"
487 */
488 move t0, ra
489 jal mips_ihb
490 nop /* delay slot */
491 move ra, t0
492 #endif /* CONFIG_MIPS_MT_SMTC */
493 mfc0 t0, CP0_STATUS
494 li t1, ST0_CU0 | 0x1e
495 or t0, t1
496 xori t0, 0x1e
497 mtc0 t0, CP0_STATUS
498 #ifdef CONFIG_MIPS_MT_SMTC
499 ehb
500 andi v0, v0, VPECONTROL_TE
501 beqz v0, 2f
502 nop /* delay slot */
503 emt
504 2:
505 mfc0 v0, CP0_TCSTATUS
506 /* Clear IXMT, then OR in previous value */
507 ori v0, TCSTATUS_IXMT
508 xori v0, TCSTATUS_IXMT
509 or v0, v1, v0
510 mtc0 v0, CP0_TCSTATUS
511 /*
512 * irq_disable_hazard below should expand to EHB
513 * on 24K/34K CPUS
514 */
515 .set pop
516 #endif /* CONFIG_MIPS_MT_SMTC */
517 irq_disable_hazard
518 .endm
519
520 #endif /* _ASM_STACKFRAME_H */
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