?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86, apic: Fix spurious error interrupts triggering on all non-boot APs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / atmel-mci.c
blobee337df816a63e849a545cb9e11d035c972a9cf9
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/stat.h>
26
27 #include <linux/mmc/host.h>
28
29 #include <mach/atmel-mci.h>
30 #include <linux/atmel-mci.h>
31
32 #include <asm/io.h>
33 #include <asm/unaligned.h>
34
35 #include <mach/cpu.h>
36 #include <mach/board.h>
37
38 #include "atmel-mci-regs.h"
39
40 #define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE)
41 #define ATMCI_DMA_THRESHOLD 16
42
43 enum {
44 EVENT_CMD_COMPLETE = 0,
45 EVENT_XFER_COMPLETE,
46 EVENT_DATA_COMPLETE,
47 EVENT_DATA_ERROR,
48 };
49
50 enum atmel_mci_state {
51 STATE_IDLE = 0,
52 STATE_SENDING_CMD,
53 STATE_SENDING_DATA,
54 STATE_DATA_BUSY,
55 STATE_SENDING_STOP,
56 STATE_DATA_ERROR,
57 };
58
59 struct atmel_mci_dma {
60 #ifdef CONFIG_MMC_ATMELMCI_DMA
61 struct dma_chan *chan;
62 struct dma_async_tx_descriptor *data_desc;
63 #endif
64 };
65
66 /**
67 * struct atmel_mci - MMC controller state shared between all slots
68 * @lock: Spinlock protecting the queue and associated data.
69 * @regs: Pointer to MMIO registers.
70 * @sg: Scatterlist entry currently being processed by PIO code, if any.
71 * @pio_offset: Offset into the current scatterlist entry.
72 * @cur_slot: The slot which is currently using the controller.
73 * @mrq: The request currently being processed on @cur_slot,
74 * or NULL if the controller is idle.
75 * @cmd: The command currently being sent to the card, or NULL.
76 * @data: The data currently being transferred, or NULL if no data
77 * transfer is in progress.
78 * @dma: DMA client state.
79 * @data_chan: DMA channel being used for the current data transfer.
80 * @cmd_status: Snapshot of SR taken upon completion of the current
81 * command. Only valid when EVENT_CMD_COMPLETE is pending.
82 * @data_status: Snapshot of SR taken upon completion of the current
83 * data transfer. Only valid when EVENT_DATA_COMPLETE or
84 * EVENT_DATA_ERROR is pending.
85 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
86 * to be sent.
87 * @tasklet: Tasklet running the request state machine.
88 * @pending_events: Bitmask of events flagged by the interrupt handler
89 * to be processed by the tasklet.
90 * @completed_events: Bitmask of events which the state machine has
91 * processed.
92 * @state: Tasklet state.
93 * @queue: List of slots waiting for access to the controller.
94 * @need_clock_update: Update the clock rate before the next request.
95 * @need_reset: Reset controller before next request.
96 * @mode_reg: Value of the MR register.
97 * @cfg_reg: Value of the CFG register.
98 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
99 * rate and timeout calculations.
100 * @mapbase: Physical address of the MMIO registers.
101 * @mck: The peripheral bus clock hooked up to the MMC controller.
102 * @pdev: Platform device associated with the MMC controller.
103 * @slot: Slots sharing this MMC controller.
104 *
105 * Locking
106 * =======
107 *
108 * @lock is a softirq-safe spinlock protecting @queue as well as
109 * @cur_slot, @mrq and @state. These must always be updated
110 * at the same time while holding @lock.
111 *
112 * @lock also protects mode_reg and need_clock_update since these are
113 * used to synchronize mode register updates with the queue
114 * processing.
115 *
116 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
117 * and must always be written at the same time as the slot is added to
118 * @queue.
119 *
120 * @pending_events and @completed_events are accessed using atomic bit
121 * operations, so they don't need any locking.
122 *
123 * None of the fields touched by the interrupt handler need any
124 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
125 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
126 * interrupts must be disabled and @data_status updated with a
127 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
128 * CMDRDY interupt must be disabled and @cmd_status updated with a
129 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
130 * bytes_xfered field of @data must be written. This is ensured by
131 * using barriers.
132 */
133 struct atmel_mci {
134 spinlock_t lock;
135 void __iomem *regs;
136
137 struct scatterlist *sg;
138 unsigned int pio_offset;
139
140 struct atmel_mci_slot *cur_slot;
141 struct mmc_request *mrq;
142 struct mmc_command *cmd;
143 struct mmc_data *data;
144
145 struct atmel_mci_dma dma;
146 struct dma_chan *data_chan;
147
148 u32 cmd_status;
149 u32 data_status;
150 u32 stop_cmdr;
151
152 struct tasklet_struct tasklet;
153 unsigned long pending_events;
154 unsigned long completed_events;
155 enum atmel_mci_state state;
156 struct list_head queue;
157
158 bool need_clock_update;
159 bool need_reset;
160 u32 mode_reg;
161 u32 cfg_reg;
162 unsigned long bus_hz;
163 unsigned long mapbase;
164 struct clk *mck;
165 struct platform_device *pdev;
166
167 struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS];
168 };
169
170 /**
171 * struct atmel_mci_slot - MMC slot state
172 * @mmc: The mmc_host representing this slot.
173 * @host: The MMC controller this slot is using.
174 * @sdc_reg: Value of SDCR to be written before using this slot.
175 * @mrq: mmc_request currently being processed or waiting to be
176 * processed, or NULL when the slot is idle.
177 * @queue_node: List node for placing this node in the @queue list of
178 * &struct atmel_mci.
179 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
180 * @flags: Random state bits associated with the slot.
181 * @detect_pin: GPIO pin used for card detection, or negative if not
182 * available.
183 * @wp_pin: GPIO pin used for card write protect sending, or negative
184 * if not available.
185 * @detect_is_active_high: The state of the detect pin when it is active.
186 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
187 */
188 struct atmel_mci_slot {
189 struct mmc_host *mmc;
190 struct atmel_mci *host;
191
192 u32 sdc_reg;
193
194 struct mmc_request *mrq;
195 struct list_head queue_node;
196
197 unsigned int clock;
198 unsigned long flags;
199 #define ATMCI_CARD_PRESENT 0
200 #define ATMCI_CARD_NEED_INIT 1
201 #define ATMCI_SHUTDOWN 2
202
203 int detect_pin;
204 int wp_pin;
205 bool detect_is_active_high;
206
207 struct timer_list detect_timer;
208 };
209
210 #define atmci_test_and_clear_pending(host, event) \
211 test_and_clear_bit(event, &host->pending_events)
212 #define atmci_set_completed(host, event) \
213 set_bit(event, &host->completed_events)
214 #define atmci_set_pending(host, event) \
215 set_bit(event, &host->pending_events)
216
217 /*
218 * Enable or disable features/registers based on
219 * whether the processor supports them
220 */
221 static bool mci_has_rwproof(void)
222 {
223 if (cpu_is_at91sam9261() || cpu_is_at91rm9200())
224 return false;
225 else
226 return true;
227 }
228
229 /*
230 * The new MCI2 module isn't 100% compatible with the old MCI module,
231 * and it has a few nice features which we want to use...
232 */
233 static inline bool atmci_is_mci2(void)
234 {
235 if (cpu_is_at91sam9g45())
236 return true;
237
238 return false;
239 }
240
241
242 /*
243 * The debugfs stuff below is mostly optimized away when
244 * CONFIG_DEBUG_FS is not set.
245 */
246 static int atmci_req_show(struct seq_file *s, void *v)
247 {
248 struct atmel_mci_slot *slot = s->private;
249 struct mmc_request *mrq;
250 struct mmc_command *cmd;
251 struct mmc_command *stop;
252 struct mmc_data *data;
253
254 /* Make sure we get a consistent snapshot */
255 spin_lock_bh(&slot->host->lock);
256 mrq = slot->mrq;
257
258 if (mrq) {
259 cmd = mrq->cmd;
260 data = mrq->data;
261 stop = mrq->stop;
262
263 if (cmd)
264 seq_printf(s,
265 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
266 cmd->opcode, cmd->arg, cmd->flags,
267 cmd->resp[0], cmd->resp[1], cmd->resp[2],
268 cmd->resp[2], cmd->error);
269 if (data)
270 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
271 data->bytes_xfered, data->blocks,
272 data->blksz, data->flags, data->error);
273 if (stop)
274 seq_printf(s,
275 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
276 stop->opcode, stop->arg, stop->flags,
277 stop->resp[0], stop->resp[1], stop->resp[2],
278 stop->resp[2], stop->error);
279 }
280
281 spin_unlock_bh(&slot->host->lock);
282
283 return 0;
284 }
285
286 static int atmci_req_open(struct inode *inode, struct file *file)
287 {
288 return single_open(file, atmci_req_show, inode->i_private);
289 }
290
291 static const struct file_operations atmci_req_fops = {
292 .owner = THIS_MODULE,
293 .open = atmci_req_open,
294 .read = seq_read,
295 .llseek = seq_lseek,
296 .release = single_release,
297 };
298
299 static void atmci_show_status_reg(struct seq_file *s,
300 const char *regname, u32 value)
301 {
302 static const char *sr_bit[] = {
303 [0] = "CMDRDY",
304 [1] = "RXRDY",
305 [2] = "TXRDY",
306 [3] = "BLKE",
307 [4] = "DTIP",
308 [5] = "NOTBUSY",
309 [6] = "ENDRX",
310 [7] = "ENDTX",
311 [8] = "SDIOIRQA",
312 [9] = "SDIOIRQB",
313 [12] = "SDIOWAIT",
314 [14] = "RXBUFF",
315 [15] = "TXBUFE",
316 [16] = "RINDE",
317 [17] = "RDIRE",
318 [18] = "RCRCE",
319 [19] = "RENDE",
320 [20] = "RTOE",
321 [21] = "DCRCE",
322 [22] = "DTOE",
323 [23] = "CSTOE",
324 [24] = "BLKOVRE",
325 [25] = "DMADONE",
326 [26] = "FIFOEMPTY",
327 [27] = "XFRDONE",
328 [30] = "OVRE",
329 [31] = "UNRE",
330 };
331 unsigned int i;
332
333 seq_printf(s, "%s:\t0x%08x", regname, value);
334 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
335 if (value & (1 << i)) {
336 if (sr_bit[i])
337 seq_printf(s, " %s", sr_bit[i]);
338 else
339 seq_puts(s, " UNKNOWN");
340 }
341 }
342 seq_putc(s, '\n');
343 }
344
345 static int atmci_regs_show(struct seq_file *s, void *v)
346 {
347 struct atmel_mci *host = s->private;
348 u32 *buf;
349
350 buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL);
351 if (!buf)
352 return -ENOMEM;
353
354 /*
355 * Grab a more or less consistent snapshot. Note that we're
356 * not disabling interrupts, so IMR and SR may not be
357 * consistent.
358 */
359 spin_lock_bh(&host->lock);
360 clk_enable(host->mck);
361 memcpy_fromio(buf, host->regs, MCI_REGS_SIZE);
362 clk_disable(host->mck);
363 spin_unlock_bh(&host->lock);
364
365 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
366 buf[MCI_MR / 4],
367 buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "",
368 buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "",
369 buf[MCI_MR / 4] & 0xff);
370 seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]);
371 seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]);
372 seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]);
373 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
374 buf[MCI_BLKR / 4],
375 buf[MCI_BLKR / 4] & 0xffff,
376 (buf[MCI_BLKR / 4] >> 16) & 0xffff);
377 if (atmci_is_mci2())
378 seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]);
379
380 /* Don't read RSPR and RDR; it will consume the data there */
381
382 atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]);
383 atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]);
384
385 if (atmci_is_mci2()) {
386 u32 val;
387
388 val = buf[MCI_DMA / 4];
389 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
390 val, val & 3,
391 ((val >> 4) & 3) ?
392 1 << (((val >> 4) & 3) + 1) : 1,
393 val & MCI_DMAEN ? " DMAEN" : "");
394
395 val = buf[MCI_CFG / 4];
396 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
397 val,
398 val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
399 val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
400 val & MCI_CFG_HSMODE ? " HSMODE" : "",
401 val & MCI_CFG_LSYNC ? " LSYNC" : "");
402 }
403
404 kfree(buf);
405
406 return 0;
407 }
408
409 static int atmci_regs_open(struct inode *inode, struct file *file)
410 {
411 return single_open(file, atmci_regs_show, inode->i_private);
412 }
413
414 static const struct file_operations atmci_regs_fops = {
415 .owner = THIS_MODULE,
416 .open = atmci_regs_open,
417 .read = seq_read,
418 .llseek = seq_lseek,
419 .release = single_release,
420 };
421
422 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
423 {
424 struct mmc_host *mmc = slot->mmc;
425 struct atmel_mci *host = slot->host;
426 struct dentry *root;
427 struct dentry *node;
428
429 root = mmc->debugfs_root;
430 if (!root)
431 return;
432
433 node = debugfs_create_file("regs", S_IRUSR, root, host,
434 &atmci_regs_fops);
435 if (IS_ERR(node))
436 return;
437 if (!node)
438 goto err;
439
440 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
441 if (!node)
442 goto err;
443
444 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
445 if (!node)
446 goto err;
447
448 node = debugfs_create_x32("pending_events", S_IRUSR, root,
449 (u32 *)&host->pending_events);
450 if (!node)
451 goto err;
452
453 node = debugfs_create_x32("completed_events", S_IRUSR, root,
454 (u32 *)&host->completed_events);
455 if (!node)
456 goto err;
457
458 return;
459
460 err:
461 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
462 }
463
464 static inline unsigned int ns_to_clocks(struct atmel_mci *host,
465 unsigned int ns)
466 {
467 return (ns * (host->bus_hz / 1000000) + 999) / 1000;
468 }
469
470 static void atmci_set_timeout(struct atmel_mci *host,
471 struct atmel_mci_slot *slot, struct mmc_data *data)
472 {
473 static unsigned dtomul_to_shift[] = {
474 0, 4, 7, 8, 10, 12, 16, 20
475 };
476 unsigned timeout;
477 unsigned dtocyc;
478 unsigned dtomul;
479
480 timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks;
481
482 for (dtomul = 0; dtomul < 8; dtomul++) {
483 unsigned shift = dtomul_to_shift[dtomul];
484 dtocyc = (timeout + (1 << shift) - 1) >> shift;
485 if (dtocyc < 15)
486 break;
487 }
488
489 if (dtomul >= 8) {
490 dtomul = 7;
491 dtocyc = 15;
492 }
493
494 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
495 dtocyc << dtomul_to_shift[dtomul]);
496 mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc)));
497 }
498
499 /*
500 * Return mask with command flags to be enabled for this command.
501 */
502 static u32 atmci_prepare_command(struct mmc_host *mmc,
503 struct mmc_command *cmd)
504 {
505 struct mmc_data *data;
506 u32 cmdr;
507
508 cmd->error = -EINPROGRESS;
509
510 cmdr = MCI_CMDR_CMDNB(cmd->opcode);
511
512 if (cmd->flags & MMC_RSP_PRESENT) {
513 if (cmd->flags & MMC_RSP_136)
514 cmdr |= MCI_CMDR_RSPTYP_136BIT;
515 else
516 cmdr |= MCI_CMDR_RSPTYP_48BIT;
517 }
518
519 /*
520 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
521 * it's too difficult to determine whether this is an ACMD or
522 * not. Better make it 64.
523 */
524 cmdr |= MCI_CMDR_MAXLAT_64CYC;
525
526 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
527 cmdr |= MCI_CMDR_OPDCMD;
528
529 data = cmd->data;
530 if (data) {
531 cmdr |= MCI_CMDR_START_XFER;
532 if (data->flags & MMC_DATA_STREAM)
533 cmdr |= MCI_CMDR_STREAM;
534 else if (data->blocks > 1)
535 cmdr |= MCI_CMDR_MULTI_BLOCK;
536 else
537 cmdr |= MCI_CMDR_BLOCK;
538
539 if (data->flags & MMC_DATA_READ)
540 cmdr |= MCI_CMDR_TRDIR_READ;
541 }
542
543 return cmdr;
544 }
545
546 static void atmci_start_command(struct atmel_mci *host,
547 struct mmc_command *cmd, u32 cmd_flags)
548 {
549 WARN_ON(host->cmd);
550 host->cmd = cmd;
551
552 dev_vdbg(&host->pdev->dev,
553 "start command: ARGR=0x%08x CMDR=0x%08x\n",
554 cmd->arg, cmd_flags);
555
556 mci_writel(host, ARGR, cmd->arg);
557 mci_writel(host, CMDR, cmd_flags);
558 }
559
560 static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
561 {
562 atmci_start_command(host, data->stop, host->stop_cmdr);
563 mci_writel(host, IER, MCI_CMDRDY);
564 }
565
566 #ifdef CONFIG_MMC_ATMELMCI_DMA
567 static void atmci_dma_cleanup(struct atmel_mci *host)
568 {
569 struct mmc_data *data = host->data;
570
571 if (data)
572 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
573 ((data->flags & MMC_DATA_WRITE)
574 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
575 }
576
577 static void atmci_stop_dma(struct atmel_mci *host)
578 {
579 struct dma_chan *chan = host->data_chan;
580
581 if (chan) {
582 chan->device->device_terminate_all(chan);
583 atmci_dma_cleanup(host);
584 } else {
585 /* Data transfer was stopped by the interrupt handler */
586 atmci_set_pending(host, EVENT_XFER_COMPLETE);
587 mci_writel(host, IER, MCI_NOTBUSY);
588 }
589 }
590
591 /* This function is called by the DMA driver from tasklet context. */
592 static void atmci_dma_complete(void *arg)
593 {
594 struct atmel_mci *host = arg;
595 struct mmc_data *data = host->data;
596
597 dev_vdbg(&host->pdev->dev, "DMA complete\n");
598
599 if (atmci_is_mci2())
600 /* Disable DMA hardware handshaking on MCI */
601 mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN);
602
603 atmci_dma_cleanup(host);
604
605 /*
606 * If the card was removed, data will be NULL. No point trying
607 * to send the stop command or waiting for NBUSY in this case.
608 */
609 if (data) {
610 atmci_set_pending(host, EVENT_XFER_COMPLETE);
611 tasklet_schedule(&host->tasklet);
612
613 /*
614 * Regardless of what the documentation says, we have
615 * to wait for NOTBUSY even after block read
616 * operations.
617 *
618 * When the DMA transfer is complete, the controller
619 * may still be reading the CRC from the card, i.e.
620 * the data transfer is still in progress and we
621 * haven't seen all the potential error bits yet.
622 *
623 * The interrupt handler will schedule a different
624 * tasklet to finish things up when the data transfer
625 * is completely done.
626 *
627 * We may not complete the mmc request here anyway
628 * because the mmc layer may call back and cause us to
629 * violate the "don't submit new operations from the
630 * completion callback" rule of the dma engine
631 * framework.
632 */
633 mci_writel(host, IER, MCI_NOTBUSY);
634 }
635 }
636
637 static int
638 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
639 {
640 struct dma_chan *chan;
641 struct dma_async_tx_descriptor *desc;
642 struct scatterlist *sg;
643 unsigned int i;
644 enum dma_data_direction direction;
645 unsigned int sglen;
646
647 /*
648 * We don't do DMA on "complex" transfers, i.e. with
649 * non-word-aligned buffers or lengths. Also, we don't bother
650 * with all the DMA setup overhead for short transfers.
651 */
652 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
653 return -EINVAL;
654 if (data->blksz & 3)
655 return -EINVAL;
656
657 for_each_sg(data->sg, sg, data->sg_len, i) {
658 if (sg->offset & 3 || sg->length & 3)
659 return -EINVAL;
660 }
661
662 /* If we don't have a channel, we can't do DMA */
663 chan = host->dma.chan;
664 if (chan)
665 host->data_chan = chan;
666
667 if (!chan)
668 return -ENODEV;
669
670 if (atmci_is_mci2())
671 mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN);
672
673 if (data->flags & MMC_DATA_READ)
674 direction = DMA_FROM_DEVICE;
675 else
676 direction = DMA_TO_DEVICE;
677
678 sglen = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, direction);
679 if (sglen != data->sg_len)
680 goto unmap_exit;
681 desc = chan->device->device_prep_slave_sg(chan,
682 data->sg, data->sg_len, direction,
683 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
684 if (!desc)
685 goto unmap_exit;
686
687 host->dma.data_desc = desc;
688 desc->callback = atmci_dma_complete;
689 desc->callback_param = host;
690
691 return 0;
692 unmap_exit:
693 dma_unmap_sg(&host->pdev->dev, data->sg, sglen, direction);
694 return -ENOMEM;
695 }
696
697 static void atmci_submit_data(struct atmel_mci *host)
698 {
699 struct dma_chan *chan = host->data_chan;
700 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
701
702 if (chan) {
703 desc->tx_submit(desc);
704 chan->device->device_issue_pending(chan);
705 }
706 }
707
708 #else /* CONFIG_MMC_ATMELMCI_DMA */
709
710 static int atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
711 {
712 return -ENOSYS;
713 }
714
715 static void atmci_submit_data(struct atmel_mci *host) {}
716
717 static void atmci_stop_dma(struct atmel_mci *host)
718 {
719 /* Data transfer was stopped by the interrupt handler */
720 atmci_set_pending(host, EVENT_XFER_COMPLETE);
721 mci_writel(host, IER, MCI_NOTBUSY);
722 }
723
724 #endif /* CONFIG_MMC_ATMELMCI_DMA */
725
726 /*
727 * Returns a mask of interrupt flags to be enabled after the whole
728 * request has been prepared.
729 */
730 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
731 {
732 u32 iflags;
733
734 data->error = -EINPROGRESS;
735
736 WARN_ON(host->data);
737 host->sg = NULL;
738 host->data = data;
739
740 iflags = ATMCI_DATA_ERROR_FLAGS;
741 if (atmci_prepare_data_dma(host, data)) {
742 host->data_chan = NULL;
743
744 /*
745 * Errata: MMC data write operation with less than 12
746 * bytes is impossible.
747 *
748 * Errata: MCI Transmit Data Register (TDR) FIFO
749 * corruption when length is not multiple of 4.
750 */
751 if (data->blocks * data->blksz < 12
752 || (data->blocks * data->blksz) & 3)
753 host->need_reset = true;
754
755 host->sg = data->sg;
756 host->pio_offset = 0;
757 if (data->flags & MMC_DATA_READ)
758 iflags |= MCI_RXRDY;
759 else
760 iflags |= MCI_TXRDY;
761 }
762
763 return iflags;
764 }
765
766 static void atmci_start_request(struct atmel_mci *host,
767 struct atmel_mci_slot *slot)
768 {
769 struct mmc_request *mrq;
770 struct mmc_command *cmd;
771 struct mmc_data *data;
772 u32 iflags;
773 u32 cmdflags;
774
775 mrq = slot->mrq;
776 host->cur_slot = slot;
777 host->mrq = mrq;
778
779 host->pending_events = 0;
780 host->completed_events = 0;
781 host->data_status = 0;
782
783 if (host->need_reset) {
784 mci_writel(host, CR, MCI_CR_SWRST);
785 mci_writel(host, CR, MCI_CR_MCIEN);
786 mci_writel(host, MR, host->mode_reg);
787 if (atmci_is_mci2())
788 mci_writel(host, CFG, host->cfg_reg);
789 host->need_reset = false;
790 }
791 mci_writel(host, SDCR, slot->sdc_reg);
792
793 iflags = mci_readl(host, IMR);
794 if (iflags)
795 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
796 iflags);
797
798 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
799 /* Send init sequence (74 clock cycles) */
800 mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT);
801 while (!(mci_readl(host, SR) & MCI_CMDRDY))
802 cpu_relax();
803 }
804 iflags = 0;
805 data = mrq->data;
806 if (data) {
807 atmci_set_timeout(host, slot, data);
808
809 /* Must set block count/size before sending command */
810 mci_writel(host, BLKR, MCI_BCNT(data->blocks)
811 | MCI_BLKLEN(data->blksz));
812 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
813 MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz));
814
815 iflags |= atmci_prepare_data(host, data);
816 }
817
818 iflags |= MCI_CMDRDY;
819 cmd = mrq->cmd;
820 cmdflags = atmci_prepare_command(slot->mmc, cmd);
821 atmci_start_command(host, cmd, cmdflags);
822
823 if (data)
824 atmci_submit_data(host);
825
826 if (mrq->stop) {
827 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
828 host->stop_cmdr |= MCI_CMDR_STOP_XFER;
829 if (!(data->flags & MMC_DATA_WRITE))
830 host->stop_cmdr |= MCI_CMDR_TRDIR_READ;
831 if (data->flags & MMC_DATA_STREAM)
832 host->stop_cmdr |= MCI_CMDR_STREAM;
833 else
834 host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK;
835 }
836
837 /*
838 * We could have enabled interrupts earlier, but I suspect
839 * that would open up a nice can of interesting race
840 * conditions (e.g. command and data complete, but stop not
841 * prepared yet.)
842 */
843 mci_writel(host, IER, iflags);
844 }
845
846 static void atmci_queue_request(struct atmel_mci *host,
847 struct atmel_mci_slot *slot, struct mmc_request *mrq)
848 {
849 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
850 host->state);
851
852 spin_lock_bh(&host->lock);
853 slot->mrq = mrq;
854 if (host->state == STATE_IDLE) {
855 host->state = STATE_SENDING_CMD;
856 atmci_start_request(host, slot);
857 } else {
858 list_add_tail(&slot->queue_node, &host->queue);
859 }
860 spin_unlock_bh(&host->lock);
861 }
862
863 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
864 {
865 struct atmel_mci_slot *slot = mmc_priv(mmc);
866 struct atmel_mci *host = slot->host;
867 struct mmc_data *data;
868
869 WARN_ON(slot->mrq);
870
871 /*
872 * We may "know" the card is gone even though there's still an
873 * electrical connection. If so, we really need to communicate
874 * this to the MMC core since there won't be any more
875 * interrupts as the card is completely removed. Otherwise,
876 * the MMC core might believe the card is still there even
877 * though the card was just removed very slowly.
878 */
879 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
880 mrq->cmd->error = -ENOMEDIUM;
881 mmc_request_done(mmc, mrq);
882 return;
883 }
884
885 /* We don't support multiple blocks of weird lengths. */
886 data = mrq->data;
887 if (data && data->blocks > 1 && data->blksz & 3) {
888 mrq->cmd->error = -EINVAL;
889 mmc_request_done(mmc, mrq);
890 }
891
892 atmci_queue_request(host, slot, mrq);
893 }
894
895 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
896 {
897 struct atmel_mci_slot *slot = mmc_priv(mmc);
898 struct atmel_mci *host = slot->host;
899 unsigned int i;
900
901 slot->sdc_reg &= ~MCI_SDCBUS_MASK;
902 switch (ios->bus_width) {
903 case MMC_BUS_WIDTH_1:
904 slot->sdc_reg |= MCI_SDCBUS_1BIT;
905 break;
906 case MMC_BUS_WIDTH_4:
907 slot->sdc_reg |= MCI_SDCBUS_4BIT;
908 break;
909 }
910
911 if (ios->clock) {
912 unsigned int clock_min = ~0U;
913 u32 clkdiv;
914
915 spin_lock_bh(&host->lock);
916 if (!host->mode_reg) {
917 clk_enable(host->mck);
918 mci_writel(host, CR, MCI_CR_SWRST);
919 mci_writel(host, CR, MCI_CR_MCIEN);
920 if (atmci_is_mci2())
921 mci_writel(host, CFG, host->cfg_reg);
922 }
923
924 /*
925 * Use mirror of ios->clock to prevent race with mmc
926 * core ios update when finding the minimum.
927 */
928 slot->clock = ios->clock;
929 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
930 if (host->slot[i] && host->slot[i]->clock
931 && host->slot[i]->clock < clock_min)
932 clock_min = host->slot[i]->clock;
933 }
934
935 /* Calculate clock divider */
936 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
937 if (clkdiv > 255) {
938 dev_warn(&mmc->class_dev,
939 "clock %u too slow; using %lu\n",
940 clock_min, host->bus_hz / (2 * 256));
941 clkdiv = 255;
942 }
943
944 host->mode_reg = MCI_MR_CLKDIV(clkdiv);
945
946 /*
947 * WRPROOF and RDPROOF prevent overruns/underruns by
948 * stopping the clock when the FIFO is full/empty.
949 * This state is not expected to last for long.
950 */
951 if (mci_has_rwproof())
952 host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF);
953
954 if (list_empty(&host->queue))
955 mci_writel(host, MR, host->mode_reg);
956 else
957 host->need_clock_update = true;
958
959 spin_unlock_bh(&host->lock);
960 } else {
961 bool any_slot_active = false;
962
963 spin_lock_bh(&host->lock);
964 slot->clock = 0;
965 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
966 if (host->slot[i] && host->slot[i]->clock) {
967 any_slot_active = true;
968 break;
969 }
970 }
971 if (!any_slot_active) {
972 mci_writel(host, CR, MCI_CR_MCIDIS);
973 if (host->mode_reg) {
974 mci_readl(host, MR);
975 clk_disable(host->mck);
976 }
977 host->mode_reg = 0;
978 }
979 spin_unlock_bh(&host->lock);
980 }
981
982 switch (ios->power_mode) {
983 case MMC_POWER_UP:
984 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
985 break;
986 default:
987 /*
988 * TODO: None of the currently available AVR32-based
989 * boards allow MMC power to be turned off. Implement
990 * power control when this can be tested properly.
991 *
992 * We also need to hook this into the clock management
993 * somehow so that newly inserted cards aren't
994 * subjected to a fast clock before we have a chance
995 * to figure out what the maximum rate is. Currently,
996 * there's no way to avoid this, and there never will
997 * be for boards that don't support power control.
998 */
999 break;
1000 }
1001 }
1002
1003 static int atmci_get_ro(struct mmc_host *mmc)
1004 {
1005 int read_only = -ENOSYS;
1006 struct atmel_mci_slot *slot = mmc_priv(mmc);
1007
1008 if (gpio_is_valid(slot->wp_pin)) {
1009 read_only = gpio_get_value(slot->wp_pin);
1010 dev_dbg(&mmc->class_dev, "card is %s\n",
1011 read_only ? "read-only" : "read-write");
1012 }
1013
1014 return read_only;
1015 }
1016
1017 static int atmci_get_cd(struct mmc_host *mmc)
1018 {
1019 int present = -ENOSYS;
1020 struct atmel_mci_slot *slot = mmc_priv(mmc);
1021
1022 if (gpio_is_valid(slot->detect_pin)) {
1023 present = !(gpio_get_value(slot->detect_pin) ^
1024 slot->detect_is_active_high);
1025 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1026 present ? "" : "not ");
1027 }
1028
1029 return present;
1030 }
1031
1032 static const struct mmc_host_ops atmci_ops = {
1033 .request = atmci_request,
1034 .set_ios = atmci_set_ios,
1035 .get_ro = atmci_get_ro,
1036 .get_cd = atmci_get_cd,
1037 };
1038
1039 /* Called with host->lock held */
1040 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1041 __releases(&host->lock)
1042 __acquires(&host->lock)
1043 {
1044 struct atmel_mci_slot *slot = NULL;
1045 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1046
1047 WARN_ON(host->cmd || host->data);
1048
1049 /*
1050 * Update the MMC clock rate if necessary. This may be
1051 * necessary if set_ios() is called when a different slot is
1052 * busy transfering data.
1053 */
1054 if (host->need_clock_update)
1055 mci_writel(host, MR, host->mode_reg);
1056
1057 host->cur_slot->mrq = NULL;
1058 host->mrq = NULL;
1059 if (!list_empty(&host->queue)) {
1060 slot = list_entry(host->queue.next,
1061 struct atmel_mci_slot, queue_node);
1062 list_del(&slot->queue_node);
1063 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1064 mmc_hostname(slot->mmc));
1065 host->state = STATE_SENDING_CMD;
1066 atmci_start_request(host, slot);
1067 } else {
1068 dev_vdbg(&host->pdev->dev, "list empty\n");
1069 host->state = STATE_IDLE;
1070 }
1071
1072 spin_unlock(&host->lock);
1073 mmc_request_done(prev_mmc, mrq);
1074 spin_lock(&host->lock);
1075 }
1076
1077 static void atmci_command_complete(struct atmel_mci *host,
1078 struct mmc_command *cmd)
1079 {
1080 u32 status = host->cmd_status;
1081
1082 /* Read the response from the card (up to 16 bytes) */
1083 cmd->resp[0] = mci_readl(host, RSPR);
1084 cmd->resp[1] = mci_readl(host, RSPR);
1085 cmd->resp[2] = mci_readl(host, RSPR);
1086 cmd->resp[3] = mci_readl(host, RSPR);
1087
1088 if (status & MCI_RTOE)
1089 cmd->error = -ETIMEDOUT;
1090 else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE))
1091 cmd->error = -EILSEQ;
1092 else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE))
1093 cmd->error = -EIO;
1094 else
1095 cmd->error = 0;
1096
1097 if (cmd->error) {
1098 dev_dbg(&host->pdev->dev,
1099 "command error: status=0x%08x\n", status);
1100
1101 if (cmd->data) {
1102 atmci_stop_dma(host);
1103 host->data = NULL;
1104 mci_writel(host, IDR, MCI_NOTBUSY
1105 | MCI_TXRDY | MCI_RXRDY
1106 | ATMCI_DATA_ERROR_FLAGS);
1107 }
1108 }
1109 }
1110
1111 static void atmci_detect_change(unsigned long data)
1112 {
1113 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1114 bool present;
1115 bool present_old;
1116
1117 /*
1118 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1119 * freeing the interrupt. We must not re-enable the interrupt
1120 * if it has been freed, and if we're shutting down, it
1121 * doesn't really matter whether the card is present or not.
1122 */
1123 smp_rmb();
1124 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1125 return;
1126
1127 enable_irq(gpio_to_irq(slot->detect_pin));
1128 present = !(gpio_get_value(slot->detect_pin) ^
1129 slot->detect_is_active_high);
1130 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1131
1132 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1133 present, present_old);
1134
1135 if (present != present_old) {
1136 struct atmel_mci *host = slot->host;
1137 struct mmc_request *mrq;
1138
1139 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1140 present ? "inserted" : "removed");
1141
1142 spin_lock(&host->lock);
1143
1144 if (!present)
1145 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1146 else
1147 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1148
1149 /* Clean up queue if present */
1150 mrq = slot->mrq;
1151 if (mrq) {
1152 if (mrq == host->mrq) {
1153 /*
1154 * Reset controller to terminate any ongoing
1155 * commands or data transfers.
1156 */
1157 mci_writel(host, CR, MCI_CR_SWRST);
1158 mci_writel(host, CR, MCI_CR_MCIEN);
1159 mci_writel(host, MR, host->mode_reg);
1160 if (atmci_is_mci2())
1161 mci_writel(host, CFG, host->cfg_reg);
1162
1163 host->data = NULL;
1164 host->cmd = NULL;
1165
1166 switch (host->state) {
1167 case STATE_IDLE:
1168 break;
1169 case STATE_SENDING_CMD:
1170 mrq->cmd->error = -ENOMEDIUM;
1171 if (!mrq->data)
1172 break;
1173 /* fall through */
1174 case STATE_SENDING_DATA:
1175 mrq->data->error = -ENOMEDIUM;
1176 atmci_stop_dma(host);
1177 break;
1178 case STATE_DATA_BUSY:
1179 case STATE_DATA_ERROR:
1180 if (mrq->data->error == -EINPROGRESS)
1181 mrq->data->error = -ENOMEDIUM;
1182 if (!mrq->stop)
1183 break;
1184 /* fall through */
1185 case STATE_SENDING_STOP:
1186 mrq->stop->error = -ENOMEDIUM;
1187 break;
1188 }
1189
1190 atmci_request_end(host, mrq);
1191 } else {
1192 list_del(&slot->queue_node);
1193 mrq->cmd->error = -ENOMEDIUM;
1194 if (mrq->data)
1195 mrq->data->error = -ENOMEDIUM;
1196 if (mrq->stop)
1197 mrq->stop->error = -ENOMEDIUM;
1198
1199 spin_unlock(&host->lock);
1200 mmc_request_done(slot->mmc, mrq);
1201 spin_lock(&host->lock);
1202 }
1203 }
1204 spin_unlock(&host->lock);
1205
1206 mmc_detect_change(slot->mmc, 0);
1207 }
1208 }
1209
1210 static void atmci_tasklet_func(unsigned long priv)
1211 {
1212 struct atmel_mci *host = (struct atmel_mci *)priv;
1213 struct mmc_request *mrq = host->mrq;
1214 struct mmc_data *data = host->data;
1215 struct mmc_command *cmd = host->cmd;
1216 enum atmel_mci_state state = host->state;
1217 enum atmel_mci_state prev_state;
1218 u32 status;
1219
1220 spin_lock(&host->lock);
1221
1222 state = host->state;
1223
1224 dev_vdbg(&host->pdev->dev,
1225 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1226 state, host->pending_events, host->completed_events,
1227 mci_readl(host, IMR));
1228
1229 do {
1230 prev_state = state;
1231
1232 switch (state) {
1233 case STATE_IDLE:
1234 break;
1235
1236 case STATE_SENDING_CMD:
1237 if (!atmci_test_and_clear_pending(host,
1238 EVENT_CMD_COMPLETE))
1239 break;
1240
1241 host->cmd = NULL;
1242 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1243 atmci_command_complete(host, mrq->cmd);
1244 if (!mrq->data || cmd->error) {
1245 atmci_request_end(host, host->mrq);
1246 goto unlock;
1247 }
1248
1249 prev_state = state = STATE_SENDING_DATA;
1250 /* fall through */
1251
1252 case STATE_SENDING_DATA:
1253 if (atmci_test_and_clear_pending(host,
1254 EVENT_DATA_ERROR)) {
1255 atmci_stop_dma(host);
1256 if (data->stop)
1257 send_stop_cmd(host, data);
1258 state = STATE_DATA_ERROR;
1259 break;
1260 }
1261
1262 if (!atmci_test_and_clear_pending(host,
1263 EVENT_XFER_COMPLETE))
1264 break;
1265
1266 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1267 prev_state = state = STATE_DATA_BUSY;
1268 /* fall through */
1269
1270 case STATE_DATA_BUSY:
1271 if (!atmci_test_and_clear_pending(host,
1272 EVENT_DATA_COMPLETE))
1273 break;
1274
1275 host->data = NULL;
1276 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1277 status = host->data_status;
1278 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1279 if (status & MCI_DTOE) {
1280 dev_dbg(&host->pdev->dev,
1281 "data timeout error\n");
1282 data->error = -ETIMEDOUT;
1283 } else if (status & MCI_DCRCE) {
1284 dev_dbg(&host->pdev->dev,
1285 "data CRC error\n");
1286 data->error = -EILSEQ;
1287 } else {
1288 dev_dbg(&host->pdev->dev,
1289 "data FIFO error (status=%08x)\n",
1290 status);
1291 data->error = -EIO;
1292 }
1293 } else {
1294 data->bytes_xfered = data->blocks * data->blksz;
1295 data->error = 0;
1296 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS);
1297 }
1298
1299 if (!data->stop) {
1300 atmci_request_end(host, host->mrq);
1301 goto unlock;
1302 }
1303
1304 prev_state = state = STATE_SENDING_STOP;
1305 if (!data->error)
1306 send_stop_cmd(host, data);
1307 /* fall through */
1308
1309 case STATE_SENDING_STOP:
1310 if (!atmci_test_and_clear_pending(host,
1311 EVENT_CMD_COMPLETE))
1312 break;
1313
1314 host->cmd = NULL;
1315 atmci_command_complete(host, mrq->stop);
1316 atmci_request_end(host, host->mrq);
1317 goto unlock;
1318
1319 case STATE_DATA_ERROR:
1320 if (!atmci_test_and_clear_pending(host,
1321 EVENT_XFER_COMPLETE))
1322 break;
1323
1324 state = STATE_DATA_BUSY;
1325 break;
1326 }
1327 } while (state != prev_state);
1328
1329 host->state = state;
1330
1331 unlock:
1332 spin_unlock(&host->lock);
1333 }
1334
1335 static void atmci_read_data_pio(struct atmel_mci *host)
1336 {
1337 struct scatterlist *sg = host->sg;
1338 void *buf = sg_virt(sg);
1339 unsigned int offset = host->pio_offset;
1340 struct mmc_data *data = host->data;
1341 u32 value;
1342 u32 status;
1343 unsigned int nbytes = 0;
1344
1345 do {
1346 value = mci_readl(host, RDR);
1347 if (likely(offset + 4 <= sg->length)) {
1348 put_unaligned(value, (u32 *)(buf + offset));
1349
1350 offset += 4;
1351 nbytes += 4;
1352
1353 if (offset == sg->length) {
1354 flush_dcache_page(sg_page(sg));
1355 host->sg = sg = sg_next(sg);
1356 if (!sg)
1357 goto done;
1358
1359 offset = 0;
1360 buf = sg_virt(sg);
1361 }
1362 } else {
1363 unsigned int remaining = sg->length - offset;
1364 memcpy(buf + offset, &value, remaining);
1365 nbytes += remaining;
1366
1367 flush_dcache_page(sg_page(sg));
1368 host->sg = sg = sg_next(sg);
1369 if (!sg)
1370 goto done;
1371
1372 offset = 4 - remaining;
1373 buf = sg_virt(sg);
1374 memcpy(buf, (u8 *)&value + remaining, offset);
1375 nbytes += offset;
1376 }
1377
1378 status = mci_readl(host, SR);
1379 if (status & ATMCI_DATA_ERROR_FLAGS) {
1380 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY
1381 | ATMCI_DATA_ERROR_FLAGS));
1382 host->data_status = status;
1383 data->bytes_xfered += nbytes;
1384 smp_wmb();
1385 atmci_set_pending(host, EVENT_DATA_ERROR);
1386 tasklet_schedule(&host->tasklet);
1387 return;
1388 }
1389 } while (status & MCI_RXRDY);
1390
1391 host->pio_offset = offset;
1392 data->bytes_xfered += nbytes;
1393
1394 return;
1395
1396 done:
1397 mci_writel(host, IDR, MCI_RXRDY);
1398 mci_writel(host, IER, MCI_NOTBUSY);
1399 data->bytes_xfered += nbytes;
1400 smp_wmb();
1401 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1402 }
1403
1404 static void atmci_write_data_pio(struct atmel_mci *host)
1405 {
1406 struct scatterlist *sg = host->sg;
1407 void *buf = sg_virt(sg);
1408 unsigned int offset = host->pio_offset;
1409 struct mmc_data *data = host->data;
1410 u32 value;
1411 u32 status;
1412 unsigned int nbytes = 0;
1413
1414 do {
1415 if (likely(offset + 4 <= sg->length)) {
1416 value = get_unaligned((u32 *)(buf + offset));
1417 mci_writel(host, TDR, value);
1418
1419 offset += 4;
1420 nbytes += 4;
1421 if (offset == sg->length) {
1422 host->sg = sg = sg_next(sg);
1423 if (!sg)
1424 goto done;
1425
1426 offset = 0;
1427 buf = sg_virt(sg);
1428 }
1429 } else {
1430 unsigned int remaining = sg->length - offset;
1431
1432 value = 0;
1433 memcpy(&value, buf + offset, remaining);
1434 nbytes += remaining;
1435
1436 host->sg = sg = sg_next(sg);
1437 if (!sg) {
1438 mci_writel(host, TDR, value);
1439 goto done;
1440 }
1441
1442 offset = 4 - remaining;
1443 buf = sg_virt(sg);
1444 memcpy((u8 *)&value + remaining, buf, offset);
1445 mci_writel(host, TDR, value);
1446 nbytes += offset;
1447 }
1448
1449 status = mci_readl(host, SR);
1450 if (status & ATMCI_DATA_ERROR_FLAGS) {
1451 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY
1452 | ATMCI_DATA_ERROR_FLAGS));
1453 host->data_status = status;
1454 data->bytes_xfered += nbytes;
1455 smp_wmb();
1456 atmci_set_pending(host, EVENT_DATA_ERROR);
1457 tasklet_schedule(&host->tasklet);
1458 return;
1459 }
1460 } while (status & MCI_TXRDY);
1461
1462 host->pio_offset = offset;
1463 data->bytes_xfered += nbytes;
1464
1465 return;
1466
1467 done:
1468 mci_writel(host, IDR, MCI_TXRDY);
1469 mci_writel(host, IER, MCI_NOTBUSY);
1470 data->bytes_xfered += nbytes;
1471 smp_wmb();
1472 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1473 }
1474
1475 static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1476 {
1477 mci_writel(host, IDR, MCI_CMDRDY);
1478
1479 host->cmd_status = status;
1480 smp_wmb();
1481 atmci_set_pending(host, EVENT_CMD_COMPLETE);
1482 tasklet_schedule(&host->tasklet);
1483 }
1484
1485 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1486 {
1487 struct atmel_mci *host = dev_id;
1488 u32 status, mask, pending;
1489 unsigned int pass_count = 0;
1490
1491 do {
1492 status = mci_readl(host, SR);
1493 mask = mci_readl(host, IMR);
1494 pending = status & mask;
1495 if (!pending)
1496 break;
1497
1498 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1499 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
1500 | MCI_RXRDY | MCI_TXRDY);
1501 pending &= mci_readl(host, IMR);
1502
1503 host->data_status = status;
1504 smp_wmb();
1505 atmci_set_pending(host, EVENT_DATA_ERROR);
1506 tasklet_schedule(&host->tasklet);
1507 }
1508 if (pending & MCI_NOTBUSY) {
1509 mci_writel(host, IDR,
1510 ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY);
1511 if (!host->data_status)
1512 host->data_status = status;
1513 smp_wmb();
1514 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1515 tasklet_schedule(&host->tasklet);
1516 }
1517 if (pending & MCI_RXRDY)
1518 atmci_read_data_pio(host);
1519 if (pending & MCI_TXRDY)
1520 atmci_write_data_pio(host);
1521
1522 if (pending & MCI_CMDRDY)
1523 atmci_cmd_interrupt(host, status);
1524 } while (pass_count++ < 5);
1525
1526 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1527 }
1528
1529 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1530 {
1531 struct atmel_mci_slot *slot = dev_id;
1532
1533 /*
1534 * Disable interrupts until the pin has stabilized and check
1535 * the state then. Use mod_timer() since we may be in the
1536 * middle of the timer routine when this interrupt triggers.
1537 */
1538 disable_irq_nosync(irq);
1539 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1540
1541 return IRQ_HANDLED;
1542 }
1543
1544 static int __init atmci_init_slot(struct atmel_mci *host,
1545 struct mci_slot_pdata *slot_data, unsigned int id,
1546 u32 sdc_reg)
1547 {
1548 struct mmc_host *mmc;
1549 struct atmel_mci_slot *slot;
1550
1551 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1552 if (!mmc)
1553 return -ENOMEM;
1554
1555 slot = mmc_priv(mmc);
1556 slot->mmc = mmc;
1557 slot->host = host;
1558 slot->detect_pin = slot_data->detect_pin;
1559 slot->wp_pin = slot_data->wp_pin;
1560 slot->detect_is_active_high = slot_data->detect_is_active_high;
1561 slot->sdc_reg = sdc_reg;
1562
1563 mmc->ops = &atmci_ops;
1564 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1565 mmc->f_max = host->bus_hz / 2;
1566 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1567 if (slot_data->bus_width >= 4)
1568 mmc->caps |= MMC_CAP_4_BIT_DATA;
1569
1570 mmc->max_hw_segs = 64;
1571 mmc->max_phys_segs = 64;
1572 mmc->max_req_size = 32768 * 512;
1573 mmc->max_blk_size = 32768;
1574 mmc->max_blk_count = 512;
1575
1576 /* Assume card is present initially */
1577 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1578 if (gpio_is_valid(slot->detect_pin)) {
1579 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1580 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1581 slot->detect_pin = -EBUSY;
1582 } else if (gpio_get_value(slot->detect_pin) ^
1583 slot->detect_is_active_high) {
1584 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1585 }
1586 }
1587
1588 if (!gpio_is_valid(slot->detect_pin))
1589 mmc->caps |= MMC_CAP_NEEDS_POLL;
1590
1591 if (gpio_is_valid(slot->wp_pin)) {
1592 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1593 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1594 slot->wp_pin = -EBUSY;
1595 }
1596 }
1597
1598 host->slot[id] = slot;
1599 mmc_add_host(mmc);
1600
1601 if (gpio_is_valid(slot->detect_pin)) {
1602 int ret;
1603
1604 setup_timer(&slot->detect_timer, atmci_detect_change,
1605 (unsigned long)slot);
1606
1607 ret = request_irq(gpio_to_irq(slot->detect_pin),
1608 atmci_detect_interrupt,
1609 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1610 "mmc-detect", slot);
1611 if (ret) {
1612 dev_dbg(&mmc->class_dev,
1613 "could not request IRQ %d for detect pin\n",
1614 gpio_to_irq(slot->detect_pin));
1615 gpio_free(slot->detect_pin);
1616 slot->detect_pin = -EBUSY;
1617 }
1618 }
1619
1620 atmci_init_debugfs(slot);
1621
1622 return 0;
1623 }
1624
1625 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1626 unsigned int id)
1627 {
1628 /* Debugfs stuff is cleaned up by mmc core */
1629
1630 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1631 smp_wmb();
1632
1633 mmc_remove_host(slot->mmc);
1634
1635 if (gpio_is_valid(slot->detect_pin)) {
1636 int pin = slot->detect_pin;
1637
1638 free_irq(gpio_to_irq(pin), slot);
1639 del_timer_sync(&slot->detect_timer);
1640 gpio_free(pin);
1641 }
1642 if (gpio_is_valid(slot->wp_pin))
1643 gpio_free(slot->wp_pin);
1644
1645 slot->host->slot[id] = NULL;
1646 mmc_free_host(slot->mmc);
1647 }
1648
1649 #ifdef CONFIG_MMC_ATMELMCI_DMA
1650 static bool filter(struct dma_chan *chan, void *slave)
1651 {
1652 struct mci_dma_data *sl = slave;
1653
1654 if (sl && find_slave_dev(sl) == chan->device->dev) {
1655 chan->private = slave_data_ptr(sl);
1656 return true;
1657 } else {
1658 return false;
1659 }
1660 }
1661
1662 static void atmci_configure_dma(struct atmel_mci *host)
1663 {
1664 struct mci_platform_data *pdata;
1665
1666 if (host == NULL)
1667 return;
1668
1669 pdata = host->pdev->dev.platform_data;
1670
1671 if (pdata && find_slave_dev(pdata->dma_slave)) {
1672 dma_cap_mask_t mask;
1673
1674 setup_dma_addr(pdata->dma_slave,
1675 host->mapbase + MCI_TDR,
1676 host->mapbase + MCI_RDR);
1677
1678 /* Try to grab a DMA channel */
1679 dma_cap_zero(mask);
1680 dma_cap_set(DMA_SLAVE, mask);
1681 host->dma.chan =
1682 dma_request_channel(mask, filter, pdata->dma_slave);
1683 }
1684 if (!host->dma.chan)
1685 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n");
1686 else
1687 dev_info(&host->pdev->dev,
1688 "Using %s for DMA transfers\n",
1689 dma_chan_name(host->dma.chan));
1690 }
1691 #else
1692 static void atmci_configure_dma(struct atmel_mci *host) {}
1693 #endif
1694
1695 static int __init atmci_probe(struct platform_device *pdev)
1696 {
1697 struct mci_platform_data *pdata;
1698 struct atmel_mci *host;
1699 struct resource *regs;
1700 unsigned int nr_slots;
1701 int irq;
1702 int ret;
1703
1704 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1705 if (!regs)
1706 return -ENXIO;
1707 pdata = pdev->dev.platform_data;
1708 if (!pdata)
1709 return -ENXIO;
1710 irq = platform_get_irq(pdev, 0);
1711 if (irq < 0)
1712 return irq;
1713
1714 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
1715 if (!host)
1716 return -ENOMEM;
1717
1718 host->pdev = pdev;
1719 spin_lock_init(&host->lock);
1720 INIT_LIST_HEAD(&host->queue);
1721
1722 host->mck = clk_get(&pdev->dev, "mci_clk");
1723 if (IS_ERR(host->mck)) {
1724 ret = PTR_ERR(host->mck);
1725 goto err_clk_get;
1726 }
1727
1728 ret = -ENOMEM;
1729 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1730 if (!host->regs)
1731 goto err_ioremap;
1732
1733 clk_enable(host->mck);
1734 mci_writel(host, CR, MCI_CR_SWRST);
1735 host->bus_hz = clk_get_rate(host->mck);
1736 clk_disable(host->mck);
1737
1738 host->mapbase = regs->start;
1739
1740 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
1741
1742 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
1743 if (ret)
1744 goto err_request_irq;
1745
1746 atmci_configure_dma(host);
1747
1748 platform_set_drvdata(pdev, host);
1749
1750 /* We need at least one slot to succeed */
1751 nr_slots = 0;
1752 ret = -ENODEV;
1753 if (pdata->slot[0].bus_width) {
1754 ret = atmci_init_slot(host, &pdata->slot[0],
1755 0, MCI_SDCSEL_SLOT_A);
1756 if (!ret)
1757 nr_slots++;
1758 }
1759 if (pdata->slot[1].bus_width) {
1760 ret = atmci_init_slot(host, &pdata->slot[1],
1761 1, MCI_SDCSEL_SLOT_B);
1762 if (!ret)
1763 nr_slots++;
1764 }
1765
1766 if (!nr_slots) {
1767 dev_err(&pdev->dev, "init failed: no slot defined\n");
1768 goto err_init_slot;
1769 }
1770
1771 dev_info(&pdev->dev,
1772 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
1773 host->mapbase, irq, nr_slots);
1774
1775 return 0;
1776
1777 err_init_slot:
1778 #ifdef CONFIG_MMC_ATMELMCI_DMA
1779 if (host->dma.chan)
1780 dma_release_channel(host->dma.chan);
1781 #endif
1782 free_irq(irq, host);
1783 err_request_irq:
1784 iounmap(host->regs);
1785 err_ioremap:
1786 clk_put(host->mck);
1787 err_clk_get:
1788 kfree(host);
1789 return ret;
1790 }
1791
1792 static int __exit atmci_remove(struct platform_device *pdev)
1793 {
1794 struct atmel_mci *host = platform_get_drvdata(pdev);
1795 unsigned int i;
1796
1797 platform_set_drvdata(pdev, NULL);
1798
1799 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) {
1800 if (host->slot[i])
1801 atmci_cleanup_slot(host->slot[i], i);
1802 }
1803
1804 clk_enable(host->mck);
1805 mci_writel(host, IDR, ~0UL);
1806 mci_writel(host, CR, MCI_CR_MCIDIS);
1807 mci_readl(host, SR);
1808 clk_disable(host->mck);
1809
1810 #ifdef CONFIG_MMC_ATMELMCI_DMA
1811 if (host->dma.chan)
1812 dma_release_channel(host->dma.chan);
1813 #endif
1814
1815 free_irq(platform_get_irq(pdev, 0), host);
1816 iounmap(host->regs);
1817
1818 clk_put(host->mck);
1819 kfree(host);
1820
1821 return 0;
1822 }
1823
1824 static struct platform_driver atmci_driver = {
1825 .remove = __exit_p(atmci_remove),
1826 .driver = {
1827 .name = "atmel_mci",
1828 },
1829 };
1830
1831 static int __init atmci_init(void)
1832 {
1833 return platform_driver_probe(&atmci_driver, atmci_probe);
1834 }
1835
1836 static void __exit atmci_exit(void)
1837 {
1838 platform_driver_unregister(&atmci_driver);
1839 }
1840
1841 late_initcall(atmci_init); /* try to load after dma driver when built-in */
1842 module_exit(atmci_exit);
1843
1844 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
1845 MODULE_AUTHOR("Haavard Skinnemoen <haavard.skinnemoen@atmel.com>");
1846 MODULE_LICENSE("GPL v2");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree