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davinci: DA850/OMAP-L138: allow async3 source to be changed
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-davinci / da850.c
blob575e9ccbb25f50a78a4c5b2d0e0c89666527bd3e
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18
19 #include <asm/mach/map.h>
20
21 #include <mach/clock.h>
22 #include <mach/psc.h>
23 #include <mach/mux.h>
24 #include <mach/irqs.h>
25 #include <mach/cputype.h>
26 #include <mach/common.h>
27 #include <mach/time.h>
28 #include <mach/da8xx.h>
29
30 #include "clock.h"
31 #include "mux.h"
32
33 /* SoC specific clock flags */
34 #define DA850_CLK_ASYNC3 BIT(16)
35
36 #define DA850_PLL1_BASE 0x01e1a000
37 #define DA850_TIMER64P2_BASE 0x01f0c000
38 #define DA850_TIMER64P3_BASE 0x01f0d000
39
40 #define DA850_REF_FREQ 24000000
41
42 #define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
43
44 static struct pll_data pll0_data = {
45 .num = 1,
46 .phys_base = DA8XX_PLL0_BASE,
47 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
48 };
49
50 static struct clk ref_clk = {
51 .name = "ref_clk",
52 .rate = DA850_REF_FREQ,
53 };
54
55 static struct clk pll0_clk = {
56 .name = "pll0",
57 .parent = &ref_clk,
58 .pll_data = &pll0_data,
59 .flags = CLK_PLL,
60 };
61
62 static struct clk pll0_aux_clk = {
63 .name = "pll0_aux_clk",
64 .parent = &pll0_clk,
65 .flags = CLK_PLL | PRE_PLL,
66 };
67
68 static struct clk pll0_sysclk2 = {
69 .name = "pll0_sysclk2",
70 .parent = &pll0_clk,
71 .flags = CLK_PLL,
72 .div_reg = PLLDIV2,
73 };
74
75 static struct clk pll0_sysclk3 = {
76 .name = "pll0_sysclk3",
77 .parent = &pll0_clk,
78 .flags = CLK_PLL,
79 .div_reg = PLLDIV3,
80 };
81
82 static struct clk pll0_sysclk4 = {
83 .name = "pll0_sysclk4",
84 .parent = &pll0_clk,
85 .flags = CLK_PLL,
86 .div_reg = PLLDIV4,
87 };
88
89 static struct clk pll0_sysclk5 = {
90 .name = "pll0_sysclk5",
91 .parent = &pll0_clk,
92 .flags = CLK_PLL,
93 .div_reg = PLLDIV5,
94 };
95
96 static struct clk pll0_sysclk6 = {
97 .name = "pll0_sysclk6",
98 .parent = &pll0_clk,
99 .flags = CLK_PLL,
100 .div_reg = PLLDIV6,
101 };
102
103 static struct clk pll0_sysclk7 = {
104 .name = "pll0_sysclk7",
105 .parent = &pll0_clk,
106 .flags = CLK_PLL,
107 .div_reg = PLLDIV7,
108 };
109
110 static struct pll_data pll1_data = {
111 .num = 2,
112 .phys_base = DA850_PLL1_BASE,
113 .flags = PLL_HAS_POSTDIV,
114 };
115
116 static struct clk pll1_clk = {
117 .name = "pll1",
118 .parent = &ref_clk,
119 .pll_data = &pll1_data,
120 .flags = CLK_PLL,
121 };
122
123 static struct clk pll1_aux_clk = {
124 .name = "pll1_aux_clk",
125 .parent = &pll1_clk,
126 .flags = CLK_PLL | PRE_PLL,
127 };
128
129 static struct clk pll1_sysclk2 = {
130 .name = "pll1_sysclk2",
131 .parent = &pll1_clk,
132 .flags = CLK_PLL,
133 .div_reg = PLLDIV2,
134 };
135
136 static struct clk pll1_sysclk3 = {
137 .name = "pll1_sysclk3",
138 .parent = &pll1_clk,
139 .flags = CLK_PLL,
140 .div_reg = PLLDIV3,
141 };
142
143 static struct clk pll1_sysclk4 = {
144 .name = "pll1_sysclk4",
145 .parent = &pll1_clk,
146 .flags = CLK_PLL,
147 .div_reg = PLLDIV4,
148 };
149
150 static struct clk pll1_sysclk5 = {
151 .name = "pll1_sysclk5",
152 .parent = &pll1_clk,
153 .flags = CLK_PLL,
154 .div_reg = PLLDIV5,
155 };
156
157 static struct clk pll1_sysclk6 = {
158 .name = "pll0_sysclk6",
159 .parent = &pll0_clk,
160 .flags = CLK_PLL,
161 .div_reg = PLLDIV6,
162 };
163
164 static struct clk pll1_sysclk7 = {
165 .name = "pll1_sysclk7",
166 .parent = &pll1_clk,
167 .flags = CLK_PLL,
168 .div_reg = PLLDIV7,
169 };
170
171 static struct clk i2c0_clk = {
172 .name = "i2c0",
173 .parent = &pll0_aux_clk,
174 };
175
176 static struct clk timerp64_0_clk = {
177 .name = "timer0",
178 .parent = &pll0_aux_clk,
179 };
180
181 static struct clk timerp64_1_clk = {
182 .name = "timer1",
183 .parent = &pll0_aux_clk,
184 };
185
186 static struct clk arm_rom_clk = {
187 .name = "arm_rom",
188 .parent = &pll0_sysclk2,
189 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
190 .flags = ALWAYS_ENABLED,
191 };
192
193 static struct clk tpcc0_clk = {
194 .name = "tpcc0",
195 .parent = &pll0_sysclk2,
196 .lpsc = DA8XX_LPSC0_TPCC,
197 .flags = ALWAYS_ENABLED | CLK_PSC,
198 };
199
200 static struct clk tptc0_clk = {
201 .name = "tptc0",
202 .parent = &pll0_sysclk2,
203 .lpsc = DA8XX_LPSC0_TPTC0,
204 .flags = ALWAYS_ENABLED,
205 };
206
207 static struct clk tptc1_clk = {
208 .name = "tptc1",
209 .parent = &pll0_sysclk2,
210 .lpsc = DA8XX_LPSC0_TPTC1,
211 .flags = ALWAYS_ENABLED,
212 };
213
214 static struct clk tpcc1_clk = {
215 .name = "tpcc1",
216 .parent = &pll0_sysclk2,
217 .lpsc = DA850_LPSC1_TPCC1,
218 .flags = CLK_PSC | ALWAYS_ENABLED,
219 .psc_ctlr = 1,
220 };
221
222 static struct clk tptc2_clk = {
223 .name = "tptc2",
224 .parent = &pll0_sysclk2,
225 .lpsc = DA850_LPSC1_TPTC2,
226 .flags = ALWAYS_ENABLED,
227 .psc_ctlr = 1,
228 };
229
230 static struct clk uart0_clk = {
231 .name = "uart0",
232 .parent = &pll0_sysclk2,
233 .lpsc = DA8XX_LPSC0_UART0,
234 };
235
236 static struct clk uart1_clk = {
237 .name = "uart1",
238 .parent = &pll0_sysclk2,
239 .lpsc = DA8XX_LPSC1_UART1,
240 .flags = DA850_CLK_ASYNC3,
241 .psc_ctlr = 1,
242 };
243
244 static struct clk uart2_clk = {
245 .name = "uart2",
246 .parent = &pll0_sysclk2,
247 .lpsc = DA8XX_LPSC1_UART2,
248 .flags = DA850_CLK_ASYNC3,
249 .psc_ctlr = 1,
250 };
251
252 static struct clk aintc_clk = {
253 .name = "aintc",
254 .parent = &pll0_sysclk4,
255 .lpsc = DA8XX_LPSC0_AINTC,
256 .flags = ALWAYS_ENABLED,
257 };
258
259 static struct clk gpio_clk = {
260 .name = "gpio",
261 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC1_GPIO,
263 .psc_ctlr = 1,
264 };
265
266 static struct clk i2c1_clk = {
267 .name = "i2c1",
268 .parent = &pll0_sysclk4,
269 .lpsc = DA8XX_LPSC1_I2C,
270 .psc_ctlr = 1,
271 };
272
273 static struct clk emif3_clk = {
274 .name = "emif3",
275 .parent = &pll0_sysclk5,
276 .lpsc = DA8XX_LPSC1_EMIF3C,
277 .flags = ALWAYS_ENABLED,
278 .psc_ctlr = 1,
279 };
280
281 static struct clk arm_clk = {
282 .name = "arm",
283 .parent = &pll0_sysclk6,
284 .lpsc = DA8XX_LPSC0_ARM,
285 .flags = ALWAYS_ENABLED,
286 };
287
288 static struct clk rmii_clk = {
289 .name = "rmii",
290 .parent = &pll0_sysclk7,
291 };
292
293 static struct clk emac_clk = {
294 .name = "emac",
295 .parent = &pll0_sysclk4,
296 .lpsc = DA8XX_LPSC1_CPGMAC,
297 .psc_ctlr = 1,
298 };
299
300 static struct clk mcasp_clk = {
301 .name = "mcasp",
302 .parent = &pll0_sysclk2,
303 .lpsc = DA8XX_LPSC1_McASP0,
304 .psc_ctlr = 1,
305 };
306
307 static struct clk lcdc_clk = {
308 .name = "lcdc",
309 .parent = &pll0_sysclk2,
310 .lpsc = DA8XX_LPSC1_LCDC,
311 .psc_ctlr = 1,
312 };
313
314 static struct clk mmcsd_clk = {
315 .name = "mmcsd",
316 .parent = &pll0_sysclk2,
317 .lpsc = DA8XX_LPSC0_MMC_SD,
318 };
319
320 static struct clk aemif_clk = {
321 .name = "aemif",
322 .parent = &pll0_sysclk3,
323 .lpsc = DA8XX_LPSC0_EMIF25,
324 .flags = ALWAYS_ENABLED,
325 };
326
327 static struct davinci_clk da850_clks[] = {
328 CLK(NULL, "ref", &ref_clk),
329 CLK(NULL, "pll0", &pll0_clk),
330 CLK(NULL, "pll0_aux", &pll0_aux_clk),
331 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
332 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
333 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
334 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
335 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
336 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
337 CLK(NULL, "pll1", &pll1_clk),
338 CLK(NULL, "pll1_aux", &pll1_aux_clk),
339 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
340 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
341 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
342 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
343 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
344 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
345 CLK("i2c_davinci.1", NULL, &i2c0_clk),
346 CLK(NULL, "timer0", &timerp64_0_clk),
347 CLK("watchdog", NULL, &timerp64_1_clk),
348 CLK(NULL, "arm_rom", &arm_rom_clk),
349 CLK(NULL, "tpcc0", &tpcc0_clk),
350 CLK(NULL, "tptc0", &tptc0_clk),
351 CLK(NULL, "tptc1", &tptc1_clk),
352 CLK(NULL, "tpcc1", &tpcc1_clk),
353 CLK(NULL, "tptc2", &tptc2_clk),
354 CLK(NULL, "uart0", &uart0_clk),
355 CLK(NULL, "uart1", &uart1_clk),
356 CLK(NULL, "uart2", &uart2_clk),
357 CLK(NULL, "aintc", &aintc_clk),
358 CLK(NULL, "gpio", &gpio_clk),
359 CLK("i2c_davinci.2", NULL, &i2c1_clk),
360 CLK(NULL, "emif3", &emif3_clk),
361 CLK(NULL, "arm", &arm_clk),
362 CLK(NULL, "rmii", &rmii_clk),
363 CLK("davinci_emac.1", NULL, &emac_clk),
364 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
365 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
366 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
367 CLK(NULL, "aemif", &aemif_clk),
368 CLK(NULL, NULL, NULL),
369 };
370
371 /*
372 * Device specific mux setup
373 *
374 * soc description mux mode mode mux dbg
375 * reg offset mask mode
376 */
377 static const struct mux_config da850_pins[] = {
378 #ifdef CONFIG_DAVINCI_MUX
379 /* UART0 function */
380 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
381 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
382 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
383 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
384 /* UART1 function */
385 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
386 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
387 /* UART2 function */
388 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
389 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
390 /* I2C1 function */
391 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
392 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
393 /* I2C0 function */
394 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
395 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
396 /* EMAC function */
397 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
398 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
399 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
400 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
401 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
402 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
403 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
404 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
405 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
406 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
407 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
408 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
409 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
410 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
411 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
412 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
413 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
414 /* McASP function */
415 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
416 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
417 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
418 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
419 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
420 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
421 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
422 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
423 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
424 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
425 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
426 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
427 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
428 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
429 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
430 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
431 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
432 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
433 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
434 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
435 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
436 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
437 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
438 /* LCD function */
439 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
440 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
441 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
442 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
443 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
444 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
445 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
446 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
447 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
448 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
449 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
450 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
451 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
452 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
453 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
454 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
455 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
456 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
457 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
458 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
459 /* MMC/SD0 function */
460 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
461 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
462 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
463 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
464 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
465 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
466 /* EMIF2.5/EMIFA function */
467 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
468 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
469 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
470 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
471 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
472 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
473 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
474 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
475 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
476 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
477 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
478 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
479 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
480 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
481 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
482 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
483 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
484 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
485 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
486 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
487 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
488 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
489 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
490 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
491 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
492 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
493 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
494 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
495 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
496 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
497 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
498 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
499 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
500 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
503 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
504 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
505 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
506 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
507 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
508 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
509 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
510 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
511 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
512 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
513 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
514 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
515 /* GPIO function */
516 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
517 MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false)
518 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
519 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
520 #endif
521 };
522
523 const short da850_uart0_pins[] __initdata = {
524 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
525 -1
526 };
527
528 const short da850_uart1_pins[] __initdata = {
529 DA850_UART1_RXD, DA850_UART1_TXD,
530 -1
531 };
532
533 const short da850_uart2_pins[] __initdata = {
534 DA850_UART2_RXD, DA850_UART2_TXD,
535 -1
536 };
537
538 const short da850_i2c0_pins[] __initdata = {
539 DA850_I2C0_SDA, DA850_I2C0_SCL,
540 -1
541 };
542
543 const short da850_i2c1_pins[] __initdata = {
544 DA850_I2C1_SCL, DA850_I2C1_SDA,
545 -1
546 };
547
548 const short da850_cpgmac_pins[] __initdata = {
549 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
550 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
551 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
552 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
553 DA850_MDIO_D,
554 -1
555 };
556
557 const short da850_mcasp_pins[] __initdata = {
558 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
559 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
560 DA850_AXR_11, DA850_AXR_12,
561 -1
562 };
563
564 const short da850_lcdcntl_pins[] __initdata = {
565 DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4,
566 DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8,
567 DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12,
568 DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK,
569 DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15,
570 DA850_GPIO8_10,
571 -1
572 };
573
574 const short da850_mmcsd0_pins[] __initdata = {
575 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
576 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
577 DA850_GPIO4_0, DA850_GPIO4_1,
578 -1
579 };
580
581 const short da850_nand_pins[] __initdata = {
582 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
583 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
584 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
585 DA850_NEMA_WE, DA850_NEMA_OE,
586 -1
587 };
588
589 const short da850_nor_pins[] __initdata = {
590 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
591 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
592 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
593 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
594 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
595 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
596 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
597 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
598 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
599 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
600 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
601 DA850_EMA_A_22, DA850_EMA_A_23,
602 -1
603 };
604
605 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
606 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
607 [IRQ_DA8XX_COMMTX] = 7,
608 [IRQ_DA8XX_COMMRX] = 7,
609 [IRQ_DA8XX_NINT] = 7,
610 [IRQ_DA8XX_EVTOUT0] = 7,
611 [IRQ_DA8XX_EVTOUT1] = 7,
612 [IRQ_DA8XX_EVTOUT2] = 7,
613 [IRQ_DA8XX_EVTOUT3] = 7,
614 [IRQ_DA8XX_EVTOUT4] = 7,
615 [IRQ_DA8XX_EVTOUT5] = 7,
616 [IRQ_DA8XX_EVTOUT6] = 7,
617 [IRQ_DA8XX_EVTOUT6] = 7,
618 [IRQ_DA8XX_EVTOUT7] = 7,
619 [IRQ_DA8XX_CCINT0] = 7,
620 [IRQ_DA8XX_CCERRINT] = 7,
621 [IRQ_DA8XX_TCERRINT0] = 7,
622 [IRQ_DA8XX_AEMIFINT] = 7,
623 [IRQ_DA8XX_I2CINT0] = 7,
624 [IRQ_DA8XX_MMCSDINT0] = 7,
625 [IRQ_DA8XX_MMCSDINT1] = 7,
626 [IRQ_DA8XX_ALLINT0] = 7,
627 [IRQ_DA8XX_RTC] = 7,
628 [IRQ_DA8XX_SPINT0] = 7,
629 [IRQ_DA8XX_TINT12_0] = 7,
630 [IRQ_DA8XX_TINT34_0] = 7,
631 [IRQ_DA8XX_TINT12_1] = 7,
632 [IRQ_DA8XX_TINT34_1] = 7,
633 [IRQ_DA8XX_UARTINT0] = 7,
634 [IRQ_DA8XX_KEYMGRINT] = 7,
635 [IRQ_DA8XX_SECINT] = 7,
636 [IRQ_DA8XX_SECKEYERR] = 7,
637 [IRQ_DA850_MPUADDRERR0] = 7,
638 [IRQ_DA850_MPUPROTERR0] = 7,
639 [IRQ_DA850_IOPUADDRERR0] = 7,
640 [IRQ_DA850_IOPUPROTERR0] = 7,
641 [IRQ_DA850_IOPUADDRERR1] = 7,
642 [IRQ_DA850_IOPUPROTERR1] = 7,
643 [IRQ_DA850_IOPUADDRERR2] = 7,
644 [IRQ_DA850_IOPUPROTERR2] = 7,
645 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
646 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
647 [IRQ_DA850_MPUADDRERR1] = 7,
648 [IRQ_DA850_MPUPROTERR1] = 7,
649 [IRQ_DA850_IOPUADDRERR3] = 7,
650 [IRQ_DA850_IOPUPROTERR3] = 7,
651 [IRQ_DA850_IOPUADDRERR4] = 7,
652 [IRQ_DA850_IOPUPROTERR4] = 7,
653 [IRQ_DA850_IOPUADDRERR5] = 7,
654 [IRQ_DA850_IOPUPROTERR5] = 7,
655 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
656 [IRQ_DA8XX_CHIPINT0] = 7,
657 [IRQ_DA8XX_CHIPINT1] = 7,
658 [IRQ_DA8XX_CHIPINT2] = 7,
659 [IRQ_DA8XX_CHIPINT3] = 7,
660 [IRQ_DA8XX_TCERRINT1] = 7,
661 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
662 [IRQ_DA8XX_C0_RX_PULSE] = 7,
663 [IRQ_DA8XX_C0_TX_PULSE] = 7,
664 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
665 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
666 [IRQ_DA8XX_C1_RX_PULSE] = 7,
667 [IRQ_DA8XX_C1_TX_PULSE] = 7,
668 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
669 [IRQ_DA8XX_MEMERR] = 7,
670 [IRQ_DA8XX_GPIO0] = 7,
671 [IRQ_DA8XX_GPIO1] = 7,
672 [IRQ_DA8XX_GPIO2] = 7,
673 [IRQ_DA8XX_GPIO3] = 7,
674 [IRQ_DA8XX_GPIO4] = 7,
675 [IRQ_DA8XX_GPIO5] = 7,
676 [IRQ_DA8XX_GPIO6] = 7,
677 [IRQ_DA8XX_GPIO7] = 7,
678 [IRQ_DA8XX_GPIO8] = 7,
679 [IRQ_DA8XX_I2CINT1] = 7,
680 [IRQ_DA8XX_LCDINT] = 7,
681 [IRQ_DA8XX_UARTINT1] = 7,
682 [IRQ_DA8XX_MCASPINT] = 7,
683 [IRQ_DA8XX_ALLINT1] = 7,
684 [IRQ_DA8XX_SPINT1] = 7,
685 [IRQ_DA8XX_UHPI_INT1] = 7,
686 [IRQ_DA8XX_USB_INT] = 7,
687 [IRQ_DA8XX_IRQN] = 7,
688 [IRQ_DA8XX_RWAKEUP] = 7,
689 [IRQ_DA8XX_UARTINT2] = 7,
690 [IRQ_DA8XX_DFTSSINT] = 7,
691 [IRQ_DA8XX_EHRPWM0] = 7,
692 [IRQ_DA8XX_EHRPWM0TZ] = 7,
693 [IRQ_DA8XX_EHRPWM1] = 7,
694 [IRQ_DA8XX_EHRPWM1TZ] = 7,
695 [IRQ_DA850_SATAINT] = 7,
696 [IRQ_DA850_TINT12_2] = 7,
697 [IRQ_DA850_TINT34_2] = 7,
698 [IRQ_DA850_TINTALL_2] = 7,
699 [IRQ_DA8XX_ECAP0] = 7,
700 [IRQ_DA8XX_ECAP1] = 7,
701 [IRQ_DA8XX_ECAP2] = 7,
702 [IRQ_DA850_MMCSDINT0_1] = 7,
703 [IRQ_DA850_MMCSDINT1_1] = 7,
704 [IRQ_DA850_T12CMPINT0_2] = 7,
705 [IRQ_DA850_T12CMPINT1_2] = 7,
706 [IRQ_DA850_T12CMPINT2_2] = 7,
707 [IRQ_DA850_T12CMPINT3_2] = 7,
708 [IRQ_DA850_T12CMPINT4_2] = 7,
709 [IRQ_DA850_T12CMPINT5_2] = 7,
710 [IRQ_DA850_T12CMPINT6_2] = 7,
711 [IRQ_DA850_T12CMPINT7_2] = 7,
712 [IRQ_DA850_T12CMPINT0_3] = 7,
713 [IRQ_DA850_T12CMPINT1_3] = 7,
714 [IRQ_DA850_T12CMPINT2_3] = 7,
715 [IRQ_DA850_T12CMPINT3_3] = 7,
716 [IRQ_DA850_T12CMPINT4_3] = 7,
717 [IRQ_DA850_T12CMPINT5_3] = 7,
718 [IRQ_DA850_T12CMPINT6_3] = 7,
719 [IRQ_DA850_T12CMPINT7_3] = 7,
720 [IRQ_DA850_RPIINT] = 7,
721 [IRQ_DA850_VPIFINT] = 7,
722 [IRQ_DA850_CCINT1] = 7,
723 [IRQ_DA850_CCERRINT1] = 7,
724 [IRQ_DA850_TCERRINT2] = 7,
725 [IRQ_DA850_TINT12_3] = 7,
726 [IRQ_DA850_TINT34_3] = 7,
727 [IRQ_DA850_TINTALL_3] = 7,
728 [IRQ_DA850_MCBSP0RINT] = 7,
729 [IRQ_DA850_MCBSP0XINT] = 7,
730 [IRQ_DA850_MCBSP1RINT] = 7,
731 [IRQ_DA850_MCBSP1XINT] = 7,
732 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
733 };
734
735 static struct map_desc da850_io_desc[] = {
736 {
737 .virtual = IO_VIRT,
738 .pfn = __phys_to_pfn(IO_PHYS),
739 .length = IO_SIZE,
740 .type = MT_DEVICE
741 },
742 {
743 .virtual = DA8XX_CP_INTC_VIRT,
744 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
745 .length = DA8XX_CP_INTC_SIZE,
746 .type = MT_DEVICE
747 },
748 };
749
750 static void __iomem *da850_psc_bases[] = {
751 IO_ADDRESS(DA8XX_PSC0_BASE),
752 IO_ADDRESS(DA8XX_PSC1_BASE),
753 };
754
755 /* Contents of JTAG ID register used to identify exact cpu type */
756 static struct davinci_id da850_ids[] = {
757 {
758 .variant = 0x0,
759 .part_no = 0xb7d1,
760 .manufacturer = 0x017, /* 0x02f >> 1 */
761 .cpu_id = DAVINCI_CPU_ID_DA850,
762 .name = "da850/omap-l138",
763 },
764 };
765
766 static struct davinci_timer_instance da850_timer_instance[4] = {
767 {
768 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
769 .bottom_irq = IRQ_DA8XX_TINT12_0,
770 .top_irq = IRQ_DA8XX_TINT34_0,
771 },
772 {
773 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
774 .bottom_irq = IRQ_DA8XX_TINT12_1,
775 .top_irq = IRQ_DA8XX_TINT34_1,
776 },
777 {
778 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
779 .bottom_irq = IRQ_DA850_TINT12_2,
780 .top_irq = IRQ_DA850_TINT34_2,
781 },
782 {
783 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
784 .bottom_irq = IRQ_DA850_TINT12_3,
785 .top_irq = IRQ_DA850_TINT34_3,
786 },
787 };
788
789 /*
790 * T0_BOT: Timer 0, bottom : Used for clock_event
791 * T0_TOP: Timer 0, top : Used for clocksource
792 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
793 */
794 static struct davinci_timer_info da850_timer_info = {
795 .timers = da850_timer_instance,
796 .clockevent_id = T0_BOT,
797 .clocksource_id = T0_TOP,
798 };
799
800 static void da850_set_async3_src(int pllnum)
801 {
802 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
803 struct davinci_clk *c;
804 unsigned int v;
805 int ret;
806
807 for (c = da850_clks; c->lk.clk; c++) {
808 clk = c->lk.clk;
809 if (clk->flags & DA850_CLK_ASYNC3) {
810 ret = clk_set_parent(clk, newparent);
811 WARN(ret, "DA850: unable to re-parent clock %s",
812 clk->name);
813 }
814 }
815
816 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
817 if (pllnum)
818 v |= CFGCHIP3_ASYNC3_CLKSRC;
819 else
820 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
821 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
822 }
823
824 static struct davinci_soc_info davinci_soc_info_da850 = {
825 .io_desc = da850_io_desc,
826 .io_desc_num = ARRAY_SIZE(da850_io_desc),
827 .ids = da850_ids,
828 .ids_num = ARRAY_SIZE(da850_ids),
829 .cpu_clks = da850_clks,
830 .psc_bases = da850_psc_bases,
831 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
832 .pinmux_pins = da850_pins,
833 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
834 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
835 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
836 .intc_irq_prios = da850_default_priorities,
837 .intc_irq_num = DA850_N_CP_INTC_IRQ,
838 .timer_info = &da850_timer_info,
839 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
840 .gpio_num = 144,
841 .gpio_irq = IRQ_DA8XX_GPIO0,
842 .serial_dev = &da8xx_serial_device,
843 .emac_pdata = &da8xx_emac_pdata,
844 };
845
846 void __init da850_init(void)
847 {
848 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
849 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
850 return;
851
852 davinci_soc_info_da850.jtag_id_base =
853 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
854 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
855
856 davinci_common_init(&davinci_soc_info_da850);
857
858 /*
859 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
860 * This helps keeping the peripherals on this domain insulated
861 * from CPU frequency changes caused by DVFS. The firmware sets
862 * both PLL0 and PLL1 to the same frequency so, there should not
863 * be any noticible change even in non-DVFS use cases.
864 */
865 da850_set_async3_src(1);
866 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree