2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit
= 32;
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_NONE
= 0x00,
94 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
95 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25
= 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26
= 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27
= 0x1b // 8168DP
123 #define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126 static const struct {
129 u32 RxConfigMask
; /* Clears the bits supported by this chip */
130 } rtl_chip_info
[] = {
131 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
137 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26
, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27
, 0xff7e1880) // PCI-E
167 static void rtl_hw_start_8169(struct net_device
*);
168 static void rtl_hw_start_8168(struct net_device
*);
169 static void rtl_hw_start_8101(struct net_device
*);
171 static struct pci_device_id rtl8169_pci_tbl
[] = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
180 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
181 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
183 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
187 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
190 * we set our copybreak very high so that we don't have
191 * to allocate 16k frames all the time (see note in
194 static int rx_copybreak
= 16383;
201 MAC0
= 0, /* Ethernet hardware address. */
203 MAR0
= 8, /* Multicast filter. */
204 CounterAddrLow
= 0x10,
205 CounterAddrHigh
= 0x14,
206 TxDescStartAddrLow
= 0x20,
207 TxDescStartAddrHigh
= 0x24,
208 TxHDescStartAddrLow
= 0x28,
209 TxHDescStartAddrHigh
= 0x2c,
232 RxDescAddrLow
= 0xe4,
233 RxDescAddrHigh
= 0xe8,
236 FuncEventMask
= 0xf4,
237 FuncPresetState
= 0xf8,
238 FuncForceEvent
= 0xfc,
241 enum rtl8110_registers
{
247 enum rtl8168_8101_registers
{
250 #define CSIAR_FLAG 0x80000000
251 #define CSIAR_WRITE_CMD 0x80000000
252 #define CSIAR_BYTE_ENABLE 0x0f
253 #define CSIAR_BYTE_ENABLE_SHIFT 12
254 #define CSIAR_ADDR_MASK 0x0fff
257 #define EPHYAR_FLAG 0x80000000
258 #define EPHYAR_WRITE_CMD 0x80000000
259 #define EPHYAR_REG_MASK 0x1f
260 #define EPHYAR_REG_SHIFT 16
261 #define EPHYAR_DATA_MASK 0xffff
263 #define FIX_NAK_1 (1 << 4)
264 #define FIX_NAK_2 (1 << 3)
266 #define EFUSEAR_FLAG 0x80000000
267 #define EFUSEAR_WRITE_CMD 0x80000000
268 #define EFUSEAR_READ_CMD 0x00000000
269 #define EFUSEAR_REG_MASK 0x03ff
270 #define EFUSEAR_REG_SHIFT 8
271 #define EFUSEAR_DATA_MASK 0xff
274 enum rtl_register_content
{
275 /* InterruptStatusBits */
279 TxDescUnavail
= 0x0080,
301 /* TXPoll register p.5 */
302 HPQ
= 0x80, /* Poll cmd on the high prio queue */
303 NPQ
= 0x40, /* Poll cmd on the low prio queue */
304 FSWInt
= 0x01, /* Forced software interrupt */
308 Cfg9346_Unlock
= 0xc0,
313 AcceptBroadcast
= 0x08,
314 AcceptMulticast
= 0x04,
316 AcceptAllPhys
= 0x01,
323 TxInterFrameGapShift
= 24,
324 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
326 /* Config1 register p.24 */
329 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
330 Speed_down
= (1 << 4),
334 PMEnable
= (1 << 0), /* Power Management Enable */
336 /* Config2 register p. 25 */
337 PCI_Clock_66MHz
= 0x01,
338 PCI_Clock_33MHz
= 0x00,
340 /* Config3 register p.25 */
341 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
342 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
343 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
345 /* Config5 register p.27 */
346 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
347 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
348 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
349 LanWake
= (1 << 1), /* LanWake enable/disable */
350 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
353 TBIReset
= 0x80000000,
354 TBILoopback
= 0x40000000,
355 TBINwEnable
= 0x20000000,
356 TBINwRestart
= 0x10000000,
357 TBILinkOk
= 0x02000000,
358 TBINwComplete
= 0x01000000,
361 EnableBist
= (1 << 15), // 8168 8101
362 Mac_dbgo_oe
= (1 << 14), // 8168 8101
363 Normal_mode
= (1 << 13), // unused
364 Force_half_dup
= (1 << 12), // 8168 8101
365 Force_rxflow_en
= (1 << 11), // 8168 8101
366 Force_txflow_en
= (1 << 10), // 8168 8101
367 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
368 ASF
= (1 << 8), // 8168 8101
369 PktCntrDisable
= (1 << 7), // 8168 8101
370 Mac_dbgo_sel
= 0x001c, // 8168
375 INTT_0
= 0x0000, // 8168
376 INTT_1
= 0x0001, // 8168
377 INTT_2
= 0x0002, // 8168
378 INTT_3
= 0x0003, // 8168
380 /* rtl8169_PHYstatus */
391 TBILinkOK
= 0x02000000,
393 /* DumpCounterCommand */
397 enum desc_status_bit
{
398 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
399 RingEnd
= (1 << 30), /* End of descriptor ring */
400 FirstFrag
= (1 << 29), /* First segment of a packet */
401 LastFrag
= (1 << 28), /* Final segment of a packet */
404 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
405 MSSShift
= 16, /* MSS value position */
406 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
407 IPCS
= (1 << 18), /* Calculate IP checksum */
408 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
409 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
410 TxVlanTag
= (1 << 17), /* Add VLAN tag */
413 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
414 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
416 #define RxProtoUDP (PID1)
417 #define RxProtoTCP (PID0)
418 #define RxProtoIP (PID1 | PID0)
419 #define RxProtoMask RxProtoIP
421 IPFail
= (1 << 16), /* IP checksum failed */
422 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
423 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
424 RxVlanTag
= (1 << 16), /* VLAN tag available */
427 #define RsvdMask 0x3fffc000
444 u8 __pad
[sizeof(void *) - sizeof(u32
)];
448 RTL_FEATURE_WOL
= (1 << 0),
449 RTL_FEATURE_MSI
= (1 << 1),
450 RTL_FEATURE_GMII
= (1 << 2),
453 struct rtl8169_counters
{
460 __le32 tx_one_collision
;
461 __le32 tx_multi_collision
;
469 struct rtl8169_private
{
470 void __iomem
*mmio_addr
; /* memory map physical address */
471 struct pci_dev
*pci_dev
; /* Index of PCI device */
472 struct net_device
*dev
;
473 struct napi_struct napi
;
474 spinlock_t lock
; /* spin lock flag */
478 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
479 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
482 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
483 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
484 dma_addr_t TxPhyAddr
;
485 dma_addr_t RxPhyAddr
;
486 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
487 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
490 struct timer_list timer
;
495 int phy_1000_ctrl_reg
;
496 #ifdef CONFIG_R8169_VLAN
497 struct vlan_group
*vlgrp
;
499 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
500 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
501 void (*phy_reset_enable
)(void __iomem
*);
502 void (*hw_start
)(struct net_device
*);
503 unsigned int (*phy_reset_pending
)(void __iomem
*);
504 unsigned int (*link_ok
)(void __iomem
*);
505 int (*do_ioctl
)(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
);
507 struct delayed_work task
;
510 struct mii_if_info mii
;
511 struct rtl8169_counters counters
;
514 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
515 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
516 module_param(rx_copybreak
, int, 0);
517 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
518 module_param(use_dac
, int, 0);
519 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
520 module_param_named(debug
, debug
.msg_enable
, int, 0);
521 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
522 MODULE_LICENSE("GPL");
523 MODULE_VERSION(RTL8169_VERSION
);
525 static int rtl8169_open(struct net_device
*dev
);
526 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
527 struct net_device
*dev
);
528 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
529 static int rtl8169_init_ring(struct net_device
*dev
);
530 static void rtl_hw_start(struct net_device
*dev
);
531 static int rtl8169_close(struct net_device
*dev
);
532 static void rtl_set_rx_mode(struct net_device
*dev
);
533 static void rtl8169_tx_timeout(struct net_device
*dev
);
534 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
535 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
536 void __iomem
*, u32 budget
);
537 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
538 static void rtl8169_down(struct net_device
*dev
);
539 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
540 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
542 static const unsigned int rtl8169_rx_config
=
543 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
545 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
549 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
551 for (i
= 20; i
> 0; i
--) {
553 * Check if the RTL8169 has completed writing to the specified
556 if (!(RTL_R32(PHYAR
) & 0x80000000))
561 * According to hardware specs a 20us delay is required after write
562 * complete indication, but before sending next command.
567 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
571 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
573 for (i
= 20; i
> 0; i
--) {
575 * Check if the RTL8169 has completed retrieving data from
576 * the specified MII register.
578 if (RTL_R32(PHYAR
) & 0x80000000) {
579 value
= RTL_R32(PHYAR
) & 0xffff;
585 * According to hardware specs a 20us delay is required after read
586 * complete indication, but before sending next command.
593 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
595 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
598 static void mdio_plus_minus(void __iomem
*ioaddr
, int reg_addr
, int p
, int m
)
602 val
= mdio_read(ioaddr
, reg_addr
);
603 mdio_write(ioaddr
, reg_addr
, (val
| p
) & ~m
);
606 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
609 struct rtl8169_private
*tp
= netdev_priv(dev
);
610 void __iomem
*ioaddr
= tp
->mmio_addr
;
612 mdio_write(ioaddr
, location
, val
);
615 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
617 struct rtl8169_private
*tp
= netdev_priv(dev
);
618 void __iomem
*ioaddr
= tp
->mmio_addr
;
620 return mdio_read(ioaddr
, location
);
623 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
627 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
628 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
630 for (i
= 0; i
< 100; i
++) {
631 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
637 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
642 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
644 for (i
= 0; i
< 100; i
++) {
645 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
646 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
655 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
659 RTL_W32(CSIDR
, value
);
660 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
661 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
663 for (i
= 0; i
< 100; i
++) {
664 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
670 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
675 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
676 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
678 for (i
= 0; i
< 100; i
++) {
679 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
680 value
= RTL_R32(CSIDR
);
689 static u8
rtl8168d_efuse_read(void __iomem
*ioaddr
, int reg_addr
)
694 RTL_W32(EFUSEAR
, (reg_addr
& EFUSEAR_REG_MASK
) << EFUSEAR_REG_SHIFT
);
696 for (i
= 0; i
< 300; i
++) {
697 if (RTL_R32(EFUSEAR
) & EFUSEAR_FLAG
) {
698 value
= RTL_R32(EFUSEAR
) & EFUSEAR_DATA_MASK
;
707 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
709 RTL_W16(IntrMask
, 0x0000);
711 RTL_W16(IntrStatus
, 0xffff);
714 static void rtl8169_asic_down(void __iomem
*ioaddr
)
716 RTL_W8(ChipCmd
, 0x00);
717 rtl8169_irq_mask_and_ack(ioaddr
);
721 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
723 return RTL_R32(TBICSR
) & TBIReset
;
726 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
728 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
731 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
733 return RTL_R32(TBICSR
) & TBILinkOk
;
736 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
738 return RTL_R8(PHYstatus
) & LinkStatus
;
741 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
743 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
746 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
750 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
751 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
754 static void rtl8169_check_link_status(struct net_device
*dev
,
755 struct rtl8169_private
*tp
,
756 void __iomem
*ioaddr
)
760 spin_lock_irqsave(&tp
->lock
, flags
);
761 if (tp
->link_ok(ioaddr
)) {
762 netif_carrier_on(dev
);
763 if (netif_msg_ifup(tp
))
764 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
766 if (netif_msg_ifdown(tp
))
767 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
768 netif_carrier_off(dev
);
770 spin_unlock_irqrestore(&tp
->lock
, flags
);
773 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
775 struct rtl8169_private
*tp
= netdev_priv(dev
);
776 void __iomem
*ioaddr
= tp
->mmio_addr
;
781 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
782 wol
->supported
= WAKE_ANY
;
784 spin_lock_irq(&tp
->lock
);
786 options
= RTL_R8(Config1
);
787 if (!(options
& PMEnable
))
790 options
= RTL_R8(Config3
);
791 if (options
& LinkUp
)
792 wol
->wolopts
|= WAKE_PHY
;
793 if (options
& MagicPacket
)
794 wol
->wolopts
|= WAKE_MAGIC
;
796 options
= RTL_R8(Config5
);
798 wol
->wolopts
|= WAKE_UCAST
;
800 wol
->wolopts
|= WAKE_BCAST
;
802 wol
->wolopts
|= WAKE_MCAST
;
805 spin_unlock_irq(&tp
->lock
);
808 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
810 struct rtl8169_private
*tp
= netdev_priv(dev
);
811 void __iomem
*ioaddr
= tp
->mmio_addr
;
813 static const struct {
818 { WAKE_ANY
, Config1
, PMEnable
},
819 { WAKE_PHY
, Config3
, LinkUp
},
820 { WAKE_MAGIC
, Config3
, MagicPacket
},
821 { WAKE_UCAST
, Config5
, UWF
},
822 { WAKE_BCAST
, Config5
, BWF
},
823 { WAKE_MCAST
, Config5
, MWF
},
824 { WAKE_ANY
, Config5
, LanWake
}
827 spin_lock_irq(&tp
->lock
);
829 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
831 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
832 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
833 if (wol
->wolopts
& cfg
[i
].opt
)
834 options
|= cfg
[i
].mask
;
835 RTL_W8(cfg
[i
].reg
, options
);
838 RTL_W8(Cfg9346
, Cfg9346_Lock
);
841 tp
->features
|= RTL_FEATURE_WOL
;
843 tp
->features
&= ~RTL_FEATURE_WOL
;
844 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
846 spin_unlock_irq(&tp
->lock
);
851 static void rtl8169_get_drvinfo(struct net_device
*dev
,
852 struct ethtool_drvinfo
*info
)
854 struct rtl8169_private
*tp
= netdev_priv(dev
);
856 strcpy(info
->driver
, MODULENAME
);
857 strcpy(info
->version
, RTL8169_VERSION
);
858 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
861 static int rtl8169_get_regs_len(struct net_device
*dev
)
863 return R8169_REGS_SIZE
;
866 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
867 u8 autoneg
, u16 speed
, u8 duplex
)
869 struct rtl8169_private
*tp
= netdev_priv(dev
);
870 void __iomem
*ioaddr
= tp
->mmio_addr
;
874 reg
= RTL_R32(TBICSR
);
875 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
876 (duplex
== DUPLEX_FULL
)) {
877 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
878 } else if (autoneg
== AUTONEG_ENABLE
)
879 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
881 if (netif_msg_link(tp
)) {
882 printk(KERN_WARNING
"%s: "
883 "incorrect speed setting refused in TBI mode\n",
892 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
893 u8 autoneg
, u16 speed
, u8 duplex
)
895 struct rtl8169_private
*tp
= netdev_priv(dev
);
896 void __iomem
*ioaddr
= tp
->mmio_addr
;
899 if (autoneg
== AUTONEG_ENABLE
) {
902 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
903 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
904 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
905 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
907 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
908 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
910 /* The 8100e/8101e/8102e do Fast Ethernet only. */
911 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_07
) &&
912 (tp
->mac_version
!= RTL_GIGA_MAC_VER_08
) &&
913 (tp
->mac_version
!= RTL_GIGA_MAC_VER_09
) &&
914 (tp
->mac_version
!= RTL_GIGA_MAC_VER_10
) &&
915 (tp
->mac_version
!= RTL_GIGA_MAC_VER_13
) &&
916 (tp
->mac_version
!= RTL_GIGA_MAC_VER_14
) &&
917 (tp
->mac_version
!= RTL_GIGA_MAC_VER_15
) &&
918 (tp
->mac_version
!= RTL_GIGA_MAC_VER_16
)) {
919 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
920 } else if (netif_msg_link(tp
)) {
921 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
925 bmcr
= BMCR_ANENABLE
| BMCR_ANRESTART
;
927 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
928 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
929 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
932 * Vendor specific (0x1f) and reserved (0x0e) MII
935 mdio_write(ioaddr
, 0x1f, 0x0000);
936 mdio_write(ioaddr
, 0x0e, 0x0000);
939 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
940 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
944 if (speed
== SPEED_10
)
946 else if (speed
== SPEED_100
)
947 bmcr
= BMCR_SPEED100
;
951 if (duplex
== DUPLEX_FULL
)
952 bmcr
|= BMCR_FULLDPLX
;
954 mdio_write(ioaddr
, 0x1f, 0x0000);
957 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
959 mdio_write(ioaddr
, MII_BMCR
, bmcr
);
961 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
962 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
963 if ((speed
== SPEED_100
) && (autoneg
!= AUTONEG_ENABLE
)) {
964 mdio_write(ioaddr
, 0x17, 0x2138);
965 mdio_write(ioaddr
, 0x0e, 0x0260);
967 mdio_write(ioaddr
, 0x17, 0x2108);
968 mdio_write(ioaddr
, 0x0e, 0x0000);
975 static int rtl8169_set_speed(struct net_device
*dev
,
976 u8 autoneg
, u16 speed
, u8 duplex
)
978 struct rtl8169_private
*tp
= netdev_priv(dev
);
981 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
983 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
984 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
989 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
991 struct rtl8169_private
*tp
= netdev_priv(dev
);
995 spin_lock_irqsave(&tp
->lock
, flags
);
996 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
997 spin_unlock_irqrestore(&tp
->lock
, flags
);
1002 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
1004 struct rtl8169_private
*tp
= netdev_priv(dev
);
1006 return tp
->cp_cmd
& RxChkSum
;
1009 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
1011 struct rtl8169_private
*tp
= netdev_priv(dev
);
1012 void __iomem
*ioaddr
= tp
->mmio_addr
;
1013 unsigned long flags
;
1015 spin_lock_irqsave(&tp
->lock
, flags
);
1018 tp
->cp_cmd
|= RxChkSum
;
1020 tp
->cp_cmd
&= ~RxChkSum
;
1022 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1025 spin_unlock_irqrestore(&tp
->lock
, flags
);
1030 #ifdef CONFIG_R8169_VLAN
1032 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1033 struct sk_buff
*skb
)
1035 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
1036 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
1039 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
1040 struct vlan_group
*grp
)
1042 struct rtl8169_private
*tp
= netdev_priv(dev
);
1043 void __iomem
*ioaddr
= tp
->mmio_addr
;
1044 unsigned long flags
;
1046 spin_lock_irqsave(&tp
->lock
, flags
);
1049 * Do not disable RxVlan on 8110SCd.
1051 if (tp
->vlgrp
|| (tp
->mac_version
== RTL_GIGA_MAC_VER_05
))
1052 tp
->cp_cmd
|= RxVlan
;
1054 tp
->cp_cmd
&= ~RxVlan
;
1055 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
1057 spin_unlock_irqrestore(&tp
->lock
, flags
);
1060 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1061 struct sk_buff
*skb
)
1063 u32 opts2
= le32_to_cpu(desc
->opts2
);
1064 struct vlan_group
*vlgrp
= tp
->vlgrp
;
1067 if (vlgrp
&& (opts2
& RxVlanTag
)) {
1068 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1076 #else /* !CONFIG_R8169_VLAN */
1078 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1079 struct sk_buff
*skb
)
1084 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1085 struct sk_buff
*skb
)
1092 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1094 struct rtl8169_private
*tp
= netdev_priv(dev
);
1095 void __iomem
*ioaddr
= tp
->mmio_addr
;
1099 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1100 cmd
->port
= PORT_FIBRE
;
1101 cmd
->transceiver
= XCVR_INTERNAL
;
1103 status
= RTL_R32(TBICSR
);
1104 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1105 cmd
->autoneg
= !!(status
& TBINwEnable
);
1107 cmd
->speed
= SPEED_1000
;
1108 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1113 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1115 struct rtl8169_private
*tp
= netdev_priv(dev
);
1117 return mii_ethtool_gset(&tp
->mii
, cmd
);
1120 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1122 struct rtl8169_private
*tp
= netdev_priv(dev
);
1123 unsigned long flags
;
1126 spin_lock_irqsave(&tp
->lock
, flags
);
1128 rc
= tp
->get_settings(dev
, cmd
);
1130 spin_unlock_irqrestore(&tp
->lock
, flags
);
1134 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1137 struct rtl8169_private
*tp
= netdev_priv(dev
);
1138 unsigned long flags
;
1140 if (regs
->len
> R8169_REGS_SIZE
)
1141 regs
->len
= R8169_REGS_SIZE
;
1143 spin_lock_irqsave(&tp
->lock
, flags
);
1144 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1145 spin_unlock_irqrestore(&tp
->lock
, flags
);
1148 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1150 struct rtl8169_private
*tp
= netdev_priv(dev
);
1152 return tp
->msg_enable
;
1155 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1157 struct rtl8169_private
*tp
= netdev_priv(dev
);
1159 tp
->msg_enable
= value
;
1162 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1169 "tx_single_collisions",
1170 "tx_multi_collisions",
1178 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1182 return ARRAY_SIZE(rtl8169_gstrings
);
1188 static void rtl8169_update_counters(struct net_device
*dev
)
1190 struct rtl8169_private
*tp
= netdev_priv(dev
);
1191 void __iomem
*ioaddr
= tp
->mmio_addr
;
1192 struct rtl8169_counters
*counters
;
1198 * Some chips are unable to dump tally counters when the receiver
1201 if ((RTL_R8(ChipCmd
) & CmdRxEnb
) == 0)
1204 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1208 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1209 cmd
= (u64
)paddr
& DMA_BIT_MASK(32);
1210 RTL_W32(CounterAddrLow
, cmd
);
1211 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1214 if ((RTL_R32(CounterAddrLow
) & CounterDump
) == 0) {
1215 /* copy updated counters */
1216 memcpy(&tp
->counters
, counters
, sizeof(*counters
));
1222 RTL_W32(CounterAddrLow
, 0);
1223 RTL_W32(CounterAddrHigh
, 0);
1225 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1228 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1229 struct ethtool_stats
*stats
, u64
*data
)
1231 struct rtl8169_private
*tp
= netdev_priv(dev
);
1235 rtl8169_update_counters(dev
);
1237 data
[0] = le64_to_cpu(tp
->counters
.tx_packets
);
1238 data
[1] = le64_to_cpu(tp
->counters
.rx_packets
);
1239 data
[2] = le64_to_cpu(tp
->counters
.tx_errors
);
1240 data
[3] = le32_to_cpu(tp
->counters
.rx_errors
);
1241 data
[4] = le16_to_cpu(tp
->counters
.rx_missed
);
1242 data
[5] = le16_to_cpu(tp
->counters
.align_errors
);
1243 data
[6] = le32_to_cpu(tp
->counters
.tx_one_collision
);
1244 data
[7] = le32_to_cpu(tp
->counters
.tx_multi_collision
);
1245 data
[8] = le64_to_cpu(tp
->counters
.rx_unicast
);
1246 data
[9] = le64_to_cpu(tp
->counters
.rx_broadcast
);
1247 data
[10] = le32_to_cpu(tp
->counters
.rx_multicast
);
1248 data
[11] = le16_to_cpu(tp
->counters
.tx_aborted
);
1249 data
[12] = le16_to_cpu(tp
->counters
.tx_underun
);
1252 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1256 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1261 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1262 .get_drvinfo
= rtl8169_get_drvinfo
,
1263 .get_regs_len
= rtl8169_get_regs_len
,
1264 .get_link
= ethtool_op_get_link
,
1265 .get_settings
= rtl8169_get_settings
,
1266 .set_settings
= rtl8169_set_settings
,
1267 .get_msglevel
= rtl8169_get_msglevel
,
1268 .set_msglevel
= rtl8169_set_msglevel
,
1269 .get_rx_csum
= rtl8169_get_rx_csum
,
1270 .set_rx_csum
= rtl8169_set_rx_csum
,
1271 .set_tx_csum
= ethtool_op_set_tx_csum
,
1272 .set_sg
= ethtool_op_set_sg
,
1273 .set_tso
= ethtool_op_set_tso
,
1274 .get_regs
= rtl8169_get_regs
,
1275 .get_wol
= rtl8169_get_wol
,
1276 .set_wol
= rtl8169_set_wol
,
1277 .get_strings
= rtl8169_get_strings
,
1278 .get_sset_count
= rtl8169_get_sset_count
,
1279 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1282 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1283 void __iomem
*ioaddr
)
1286 * The driver currently handles the 8168Bf and the 8168Be identically
1287 * but they can be identified more specifically through the test below
1290 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1292 * Same thing for the 8101Eb and the 8101Ec:
1294 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1296 static const struct {
1302 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26
},
1303 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25
},
1304 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27
},
1305 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26
},
1308 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1309 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1310 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1311 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1312 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1313 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1314 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1315 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1316 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1319 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1320 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1321 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1322 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1325 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1326 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1327 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1328 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1329 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1330 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1331 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1332 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1333 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1334 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1335 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1336 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1337 /* FIXME: where did these entries come from ? -- FR */
1338 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1339 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1342 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1343 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1344 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1345 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1346 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1347 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1350 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE
}
1354 reg
= RTL_R32(TxConfig
);
1355 while ((reg
& p
->mask
) != p
->val
)
1357 tp
->mac_version
= p
->mac_version
;
1360 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1362 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1370 static void rtl_phy_write(void __iomem
*ioaddr
, const struct phy_reg
*regs
, int len
)
1373 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1378 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1380 static const struct phy_reg phy_reg_init
[] = {
1442 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1445 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1447 static const struct phy_reg phy_reg_init
[] = {
1453 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1456 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private
*tp
,
1457 void __iomem
*ioaddr
)
1459 struct pci_dev
*pdev
= tp
->pci_dev
;
1460 u16 vendor_id
, device_id
;
1462 pci_read_config_word(pdev
, PCI_SUBSYSTEM_VENDOR_ID
, &vendor_id
);
1463 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &device_id
);
1465 if ((vendor_id
!= PCI_VENDOR_ID_GIGABYTE
) || (device_id
!= 0xe000))
1468 mdio_write(ioaddr
, 0x1f, 0x0001);
1469 mdio_write(ioaddr
, 0x10, 0xf01b);
1470 mdio_write(ioaddr
, 0x1f, 0x0000);
1473 static void rtl8169scd_hw_phy_config(struct rtl8169_private
*tp
,
1474 void __iomem
*ioaddr
)
1476 static const struct phy_reg phy_reg_init
[] = {
1516 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1518 rtl8169scd_hw_phy_config_quirk(tp
, ioaddr
);
1521 static void rtl8169sce_hw_phy_config(void __iomem
*ioaddr
)
1523 static const struct phy_reg phy_reg_init
[] = {
1571 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1574 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1576 static const struct phy_reg phy_reg_init
[] = {
1581 mdio_write(ioaddr
, 0x1f, 0x0001);
1582 mdio_patch(ioaddr
, 0x16, 1 << 0);
1584 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1587 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1589 static const struct phy_reg phy_reg_init
[] = {
1595 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1598 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1600 static const struct phy_reg phy_reg_init
[] = {
1608 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1611 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1613 static const struct phy_reg phy_reg_init
[] = {
1619 mdio_write(ioaddr
, 0x1f, 0x0000);
1620 mdio_patch(ioaddr
, 0x14, 1 << 5);
1621 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1623 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1626 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1628 static const struct phy_reg phy_reg_init
[] = {
1648 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1650 mdio_patch(ioaddr
, 0x14, 1 << 5);
1651 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1652 mdio_write(ioaddr
, 0x1f, 0x0000);
1655 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1657 static const struct phy_reg phy_reg_init
[] = {
1675 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1677 mdio_patch(ioaddr
, 0x16, 1 << 0);
1678 mdio_patch(ioaddr
, 0x14, 1 << 5);
1679 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1680 mdio_write(ioaddr
, 0x1f, 0x0000);
1683 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1685 static const struct phy_reg phy_reg_init
[] = {
1697 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1699 mdio_patch(ioaddr
, 0x16, 1 << 0);
1700 mdio_patch(ioaddr
, 0x14, 1 << 5);
1701 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1702 mdio_write(ioaddr
, 0x1f, 0x0000);
1705 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1707 rtl8168c_3_hw_phy_config(ioaddr
);
1710 static void rtl8168d_1_hw_phy_config(void __iomem
*ioaddr
)
1712 static const struct phy_reg phy_reg_init_0
[] = {
1731 static const struct phy_reg phy_reg_init_1
[] = {
1738 static const struct phy_reg phy_reg_init_2
[] = {
2094 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2096 mdio_write(ioaddr
, 0x1f, 0x0002);
2097 mdio_plus_minus(ioaddr
, 0x0b, 0x0010, 0x00ef);
2098 mdio_plus_minus(ioaddr
, 0x0c, 0xa200, 0x5d00);
2100 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2102 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2103 static const struct phy_reg phy_reg_init
[] = {
2113 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2115 val
= mdio_read(ioaddr
, 0x0d);
2117 if ((val
& 0x00ff) != 0x006c) {
2118 static const u32 set
[] = {
2119 0x0065, 0x0066, 0x0067, 0x0068,
2120 0x0069, 0x006a, 0x006b, 0x006c
2124 mdio_write(ioaddr
, 0x1f, 0x0002);
2127 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2128 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2131 static const struct phy_reg phy_reg_init
[] = {
2139 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2142 mdio_write(ioaddr
, 0x1f, 0x0002);
2143 mdio_patch(ioaddr
, 0x0d, 0x0300);
2144 mdio_patch(ioaddr
, 0x0f, 0x0010);
2146 mdio_write(ioaddr
, 0x1f, 0x0002);
2147 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2148 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2150 rtl_phy_write(ioaddr
, phy_reg_init_2
, ARRAY_SIZE(phy_reg_init_2
));
2153 static void rtl8168d_2_hw_phy_config(void __iomem
*ioaddr
)
2155 static const struct phy_reg phy_reg_init_0
[] = {
2180 static const struct phy_reg phy_reg_init_1
[] = {
2493 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
2495 if (rtl8168d_efuse_read(ioaddr
, 0x01) == 0xb1) {
2496 static const struct phy_reg phy_reg_init
[] = {
2507 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2509 val
= mdio_read(ioaddr
, 0x0d);
2510 if ((val
& 0x00ff) != 0x006c) {
2512 0x0065, 0x0066, 0x0067, 0x0068,
2513 0x0069, 0x006a, 0x006b, 0x006c
2517 mdio_write(ioaddr
, 0x1f, 0x0002);
2520 for (i
= 0; i
< ARRAY_SIZE(set
); i
++)
2521 mdio_write(ioaddr
, 0x0d, val
| set
[i
]);
2524 static const struct phy_reg phy_reg_init
[] = {
2532 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2535 mdio_write(ioaddr
, 0x1f, 0x0002);
2536 mdio_plus_minus(ioaddr
, 0x02, 0x0100, 0x0600);
2537 mdio_plus_minus(ioaddr
, 0x03, 0x0000, 0xe000);
2539 mdio_write(ioaddr
, 0x1f, 0x0001);
2540 mdio_write(ioaddr
, 0x17, 0x0cc0);
2542 mdio_write(ioaddr
, 0x1f, 0x0002);
2543 mdio_patch(ioaddr
, 0x0f, 0x0017);
2545 rtl_phy_write(ioaddr
, phy_reg_init_1
, ARRAY_SIZE(phy_reg_init_1
));
2548 static void rtl8168d_3_hw_phy_config(void __iomem
*ioaddr
)
2550 static const struct phy_reg phy_reg_init
[] = {
2606 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2609 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
2611 static const struct phy_reg phy_reg_init
[] = {
2618 mdio_write(ioaddr
, 0x1f, 0x0000);
2619 mdio_patch(ioaddr
, 0x11, 1 << 12);
2620 mdio_patch(ioaddr
, 0x19, 1 << 13);
2621 mdio_patch(ioaddr
, 0x10, 1 << 15);
2623 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
2626 static void rtl_hw_phy_config(struct net_device
*dev
)
2628 struct rtl8169_private
*tp
= netdev_priv(dev
);
2629 void __iomem
*ioaddr
= tp
->mmio_addr
;
2631 rtl8169_print_mac_version(tp
);
2633 switch (tp
->mac_version
) {
2634 case RTL_GIGA_MAC_VER_01
:
2636 case RTL_GIGA_MAC_VER_02
:
2637 case RTL_GIGA_MAC_VER_03
:
2638 rtl8169s_hw_phy_config(ioaddr
);
2640 case RTL_GIGA_MAC_VER_04
:
2641 rtl8169sb_hw_phy_config(ioaddr
);
2643 case RTL_GIGA_MAC_VER_05
:
2644 rtl8169scd_hw_phy_config(tp
, ioaddr
);
2646 case RTL_GIGA_MAC_VER_06
:
2647 rtl8169sce_hw_phy_config(ioaddr
);
2649 case RTL_GIGA_MAC_VER_07
:
2650 case RTL_GIGA_MAC_VER_08
:
2651 case RTL_GIGA_MAC_VER_09
:
2652 rtl8102e_hw_phy_config(ioaddr
);
2654 case RTL_GIGA_MAC_VER_11
:
2655 rtl8168bb_hw_phy_config(ioaddr
);
2657 case RTL_GIGA_MAC_VER_12
:
2658 rtl8168bef_hw_phy_config(ioaddr
);
2660 case RTL_GIGA_MAC_VER_17
:
2661 rtl8168bef_hw_phy_config(ioaddr
);
2663 case RTL_GIGA_MAC_VER_18
:
2664 rtl8168cp_1_hw_phy_config(ioaddr
);
2666 case RTL_GIGA_MAC_VER_19
:
2667 rtl8168c_1_hw_phy_config(ioaddr
);
2669 case RTL_GIGA_MAC_VER_20
:
2670 rtl8168c_2_hw_phy_config(ioaddr
);
2672 case RTL_GIGA_MAC_VER_21
:
2673 rtl8168c_3_hw_phy_config(ioaddr
);
2675 case RTL_GIGA_MAC_VER_22
:
2676 rtl8168c_4_hw_phy_config(ioaddr
);
2678 case RTL_GIGA_MAC_VER_23
:
2679 case RTL_GIGA_MAC_VER_24
:
2680 rtl8168cp_2_hw_phy_config(ioaddr
);
2682 case RTL_GIGA_MAC_VER_25
:
2683 rtl8168d_1_hw_phy_config(ioaddr
);
2685 case RTL_GIGA_MAC_VER_26
:
2686 rtl8168d_2_hw_phy_config(ioaddr
);
2688 case RTL_GIGA_MAC_VER_27
:
2689 rtl8168d_3_hw_phy_config(ioaddr
);
2697 static void rtl8169_phy_timer(unsigned long __opaque
)
2699 struct net_device
*dev
= (struct net_device
*)__opaque
;
2700 struct rtl8169_private
*tp
= netdev_priv(dev
);
2701 struct timer_list
*timer
= &tp
->timer
;
2702 void __iomem
*ioaddr
= tp
->mmio_addr
;
2703 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
2705 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
2707 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
2710 spin_lock_irq(&tp
->lock
);
2712 if (tp
->phy_reset_pending(ioaddr
)) {
2714 * A busy loop could burn quite a few cycles on nowadays CPU.
2715 * Let's delay the execution of the timer for a few ticks.
2721 if (tp
->link_ok(ioaddr
))
2724 if (netif_msg_link(tp
))
2725 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
2727 tp
->phy_reset_enable(ioaddr
);
2730 mod_timer(timer
, jiffies
+ timeout
);
2732 spin_unlock_irq(&tp
->lock
);
2735 static inline void rtl8169_delete_timer(struct net_device
*dev
)
2737 struct rtl8169_private
*tp
= netdev_priv(dev
);
2738 struct timer_list
*timer
= &tp
->timer
;
2740 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2743 del_timer_sync(timer
);
2746 static inline void rtl8169_request_timer(struct net_device
*dev
)
2748 struct rtl8169_private
*tp
= netdev_priv(dev
);
2749 struct timer_list
*timer
= &tp
->timer
;
2751 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
2754 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
2757 #ifdef CONFIG_NET_POLL_CONTROLLER
2759 * Polling 'interrupt' - used by things like netconsole to send skbs
2760 * without having to re-enable interrupts. It's not called while
2761 * the interrupt routine is executing.
2763 static void rtl8169_netpoll(struct net_device
*dev
)
2765 struct rtl8169_private
*tp
= netdev_priv(dev
);
2766 struct pci_dev
*pdev
= tp
->pci_dev
;
2768 disable_irq(pdev
->irq
);
2769 rtl8169_interrupt(pdev
->irq
, dev
);
2770 enable_irq(pdev
->irq
);
2774 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
2775 void __iomem
*ioaddr
)
2778 pci_release_regions(pdev
);
2779 pci_disable_device(pdev
);
2783 static void rtl8169_phy_reset(struct net_device
*dev
,
2784 struct rtl8169_private
*tp
)
2786 void __iomem
*ioaddr
= tp
->mmio_addr
;
2789 tp
->phy_reset_enable(ioaddr
);
2790 for (i
= 0; i
< 100; i
++) {
2791 if (!tp
->phy_reset_pending(ioaddr
))
2795 if (netif_msg_link(tp
))
2796 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
2799 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
2801 void __iomem
*ioaddr
= tp
->mmio_addr
;
2803 rtl_hw_phy_config(dev
);
2805 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
2806 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2810 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
2812 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
2813 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
2815 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
2816 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2818 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2819 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
2822 rtl8169_phy_reset(dev
, tp
);
2825 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2826 * only 8101. Don't panic.
2828 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
2830 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
2831 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
2834 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
2836 void __iomem
*ioaddr
= tp
->mmio_addr
;
2840 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
2841 high
= addr
[4] | (addr
[5] << 8);
2843 spin_lock_irq(&tp
->lock
);
2845 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2847 RTL_W32(MAC4
, high
);
2853 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2855 spin_unlock_irq(&tp
->lock
);
2858 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
2860 struct rtl8169_private
*tp
= netdev_priv(dev
);
2861 struct sockaddr
*addr
= p
;
2863 if (!is_valid_ether_addr(addr
->sa_data
))
2864 return -EADDRNOTAVAIL
;
2866 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
2868 rtl_rar_set(tp
, dev
->dev_addr
);
2873 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2875 struct rtl8169_private
*tp
= netdev_priv(dev
);
2876 struct mii_ioctl_data
*data
= if_mii(ifr
);
2878 return netif_running(dev
) ? tp
->do_ioctl(tp
, data
, cmd
) : -ENODEV
;
2881 static int rtl_xmii_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2885 data
->phy_id
= 32; /* Internal PHY */
2889 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
2893 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
2899 static int rtl_tbi_ioctl(struct rtl8169_private
*tp
, struct mii_ioctl_data
*data
, int cmd
)
2904 static const struct rtl_cfg_info
{
2905 void (*hw_start
)(struct net_device
*);
2906 unsigned int region
;
2912 } rtl_cfg_infos
[] = {
2914 .hw_start
= rtl_hw_start_8169
,
2917 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2918 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2919 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2920 .features
= RTL_FEATURE_GMII
,
2921 .default_ver
= RTL_GIGA_MAC_VER_01
,
2924 .hw_start
= rtl_hw_start_8168
,
2927 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
2928 TxErr
| TxOK
| RxOK
| RxErr
,
2929 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
2930 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
,
2931 .default_ver
= RTL_GIGA_MAC_VER_11
,
2934 .hw_start
= rtl_hw_start_8101
,
2937 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
2938 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
2939 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
2940 .features
= RTL_FEATURE_MSI
,
2941 .default_ver
= RTL_GIGA_MAC_VER_13
,
2945 /* Cfg9346_Unlock assumed. */
2946 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
2947 const struct rtl_cfg_info
*cfg
)
2952 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
2953 if (cfg
->features
& RTL_FEATURE_MSI
) {
2954 if (pci_enable_msi(pdev
)) {
2955 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
2958 msi
= RTL_FEATURE_MSI
;
2961 RTL_W8(Config2
, cfg2
);
2965 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
2967 if (tp
->features
& RTL_FEATURE_MSI
) {
2968 pci_disable_msi(pdev
);
2969 tp
->features
&= ~RTL_FEATURE_MSI
;
2973 static const struct net_device_ops rtl8169_netdev_ops
= {
2974 .ndo_open
= rtl8169_open
,
2975 .ndo_stop
= rtl8169_close
,
2976 .ndo_get_stats
= rtl8169_get_stats
,
2977 .ndo_start_xmit
= rtl8169_start_xmit
,
2978 .ndo_tx_timeout
= rtl8169_tx_timeout
,
2979 .ndo_validate_addr
= eth_validate_addr
,
2980 .ndo_change_mtu
= rtl8169_change_mtu
,
2981 .ndo_set_mac_address
= rtl_set_mac_address
,
2982 .ndo_do_ioctl
= rtl8169_ioctl
,
2983 .ndo_set_multicast_list
= rtl_set_rx_mode
,
2984 #ifdef CONFIG_R8169_VLAN
2985 .ndo_vlan_rx_register
= rtl8169_vlan_rx_register
,
2987 #ifdef CONFIG_NET_POLL_CONTROLLER
2988 .ndo_poll_controller
= rtl8169_netpoll
,
2993 static int __devinit
2994 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2996 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2997 const unsigned int region
= cfg
->region
;
2998 struct rtl8169_private
*tp
;
2999 struct mii_if_info
*mii
;
3000 struct net_device
*dev
;
3001 void __iomem
*ioaddr
;
3005 if (netif_msg_drv(&debug
)) {
3006 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
3007 MODULENAME
, RTL8169_VERSION
);
3010 dev
= alloc_etherdev(sizeof (*tp
));
3012 if (netif_msg_drv(&debug
))
3013 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
3018 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3019 dev
->netdev_ops
= &rtl8169_netdev_ops
;
3020 tp
= netdev_priv(dev
);
3023 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
3027 mii
->mdio_read
= rtl_mdio_read
;
3028 mii
->mdio_write
= rtl_mdio_write
;
3029 mii
->phy_id_mask
= 0x1f;
3030 mii
->reg_num_mask
= 0x1f;
3031 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
3033 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3034 rc
= pci_enable_device(pdev
);
3036 if (netif_msg_probe(tp
))
3037 dev_err(&pdev
->dev
, "enable failure\n");
3038 goto err_out_free_dev_1
;
3041 rc
= pci_set_mwi(pdev
);
3043 goto err_out_disable_2
;
3045 /* make sure PCI base addr 1 is MMIO */
3046 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
3047 if (netif_msg_probe(tp
)) {
3049 "region #%d not an MMIO resource, aborting\n",
3056 /* check for weird/broken PCI region reporting */
3057 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
3058 if (netif_msg_probe(tp
)) {
3060 "Invalid PCI region size(s), aborting\n");
3066 rc
= pci_request_regions(pdev
, MODULENAME
);
3068 if (netif_msg_probe(tp
))
3069 dev_err(&pdev
->dev
, "could not request regions.\n");
3073 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
3075 if ((sizeof(dma_addr_t
) > 4) &&
3076 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) && use_dac
) {
3077 tp
->cp_cmd
|= PCIDAC
;
3078 dev
->features
|= NETIF_F_HIGHDMA
;
3080 rc
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3082 if (netif_msg_probe(tp
)) {
3084 "DMA configuration failed.\n");
3086 goto err_out_free_res_4
;
3090 /* ioremap MMIO region */
3091 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
3093 if (netif_msg_probe(tp
))
3094 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
3096 goto err_out_free_res_4
;
3099 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3100 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
3101 dev_info(&pdev
->dev
, "no PCI Express capability\n");
3103 RTL_W16(IntrMask
, 0x0000);
3105 /* Soft reset the chip. */
3106 RTL_W8(ChipCmd
, CmdReset
);
3108 /* Check that the chip has finished the reset. */
3109 for (i
= 0; i
< 100; i
++) {
3110 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3112 msleep_interruptible(1);
3115 RTL_W16(IntrStatus
, 0xffff);
3117 pci_set_master(pdev
);
3119 /* Identify chip attached to board */
3120 rtl8169_get_mac_version(tp
, ioaddr
);
3122 /* Use appropriate default if unknown */
3123 if (tp
->mac_version
== RTL_GIGA_MAC_NONE
) {
3124 if (netif_msg_probe(tp
)) {
3125 dev_notice(&pdev
->dev
,
3126 "unknown MAC, using family default\n");
3128 tp
->mac_version
= cfg
->default_ver
;
3131 rtl8169_print_mac_version(tp
);
3133 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
3134 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
3137 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
3139 "driver bug, MAC version not found in rtl_chip_info\n");
3144 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3145 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
3146 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
3147 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
3148 tp
->features
|= RTL_FEATURE_WOL
;
3149 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
3150 tp
->features
|= RTL_FEATURE_WOL
;
3151 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
3152 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3154 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
3155 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
3156 tp
->set_speed
= rtl8169_set_speed_tbi
;
3157 tp
->get_settings
= rtl8169_gset_tbi
;
3158 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
3159 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
3160 tp
->link_ok
= rtl8169_tbi_link_ok
;
3161 tp
->do_ioctl
= rtl_tbi_ioctl
;
3163 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
3165 tp
->set_speed
= rtl8169_set_speed_xmii
;
3166 tp
->get_settings
= rtl8169_gset_xmii
;
3167 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
3168 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
3169 tp
->link_ok
= rtl8169_xmii_link_ok
;
3170 tp
->do_ioctl
= rtl_xmii_ioctl
;
3173 spin_lock_init(&tp
->lock
);
3175 tp
->mmio_addr
= ioaddr
;
3177 /* Get MAC address */
3178 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
3179 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
3180 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3182 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
3183 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
3184 dev
->irq
= pdev
->irq
;
3185 dev
->base_addr
= (unsigned long) ioaddr
;
3187 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
3189 #ifdef CONFIG_R8169_VLAN
3190 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3193 tp
->intr_mask
= 0xffff;
3194 tp
->align
= cfg
->align
;
3195 tp
->hw_start
= cfg
->hw_start
;
3196 tp
->intr_event
= cfg
->intr_event
;
3197 tp
->napi_event
= cfg
->napi_event
;
3199 init_timer(&tp
->timer
);
3200 tp
->timer
.data
= (unsigned long) dev
;
3201 tp
->timer
.function
= rtl8169_phy_timer
;
3203 rc
= register_netdev(dev
);
3207 pci_set_drvdata(pdev
, dev
);
3209 if (netif_msg_probe(tp
)) {
3210 u32 xid
= RTL_R32(TxConfig
) & 0x9cf0f8ff;
3212 printk(KERN_INFO
"%s: %s at 0x%lx, "
3213 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
3214 "XID %08x IRQ %d\n",
3216 rtl_chip_info
[tp
->chipset
].name
,
3218 dev
->dev_addr
[0], dev
->dev_addr
[1],
3219 dev
->dev_addr
[2], dev
->dev_addr
[3],
3220 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
3223 rtl8169_init_phy(dev
, tp
);
3226 * Pretend we are using VLANs; This bypasses a nasty bug where
3227 * Interrupts stop flowing on high load on 8110SCd controllers.
3229 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)
3230 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | RxVlan
);
3232 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
3238 rtl_disable_msi(pdev
, tp
);
3241 pci_release_regions(pdev
);
3243 pci_clear_mwi(pdev
);
3245 pci_disable_device(pdev
);
3251 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
3253 struct net_device
*dev
= pci_get_drvdata(pdev
);
3254 struct rtl8169_private
*tp
= netdev_priv(dev
);
3256 flush_scheduled_work();
3258 unregister_netdev(dev
);
3260 /* restore original MAC address */
3261 rtl_rar_set(tp
, dev
->perm_addr
);
3263 rtl_disable_msi(pdev
, tp
);
3264 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
3265 pci_set_drvdata(pdev
, NULL
);
3268 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
3271 unsigned int max_frame
= mtu
+ VLAN_ETH_HLEN
+ ETH_FCS_LEN
;
3273 if (max_frame
!= 16383)
3274 printk(KERN_WARNING PFX
"WARNING! Changing of MTU on this "
3275 "NIC may lead to frame reception errors!\n");
3277 tp
->rx_buf_sz
= (max_frame
> RX_BUF_SIZE
) ? max_frame
: RX_BUF_SIZE
;
3280 static int rtl8169_open(struct net_device
*dev
)
3282 struct rtl8169_private
*tp
= netdev_priv(dev
);
3283 struct pci_dev
*pdev
= tp
->pci_dev
;
3284 int retval
= -ENOMEM
;
3288 * Note that we use a magic value here, its wierd I know
3289 * its done because, some subset of rtl8169 hardware suffers from
3290 * a problem in which frames received that are longer than
3291 * the size set in RxMaxSize register return garbage sizes
3292 * when received. To avoid this we need to turn off filtering,
3293 * which is done by setting a value of 16383 in the RxMaxSize register
3294 * and allocating 16k frames to handle the largest possible rx value
3295 * thats what the magic math below does.
3297 rtl8169_set_rxbufsize(tp
, 16383 - VLAN_ETH_HLEN
- ETH_FCS_LEN
);
3300 * Rx and Tx desscriptors needs 256 bytes alignment.
3301 * pci_alloc_consistent provides more.
3303 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
3305 if (!tp
->TxDescArray
)
3308 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
3310 if (!tp
->RxDescArray
)
3313 retval
= rtl8169_init_ring(dev
);
3317 INIT_DELAYED_WORK(&tp
->task
, NULL
);
3321 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
3322 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
3325 goto err_release_ring_2
;
3327 napi_enable(&tp
->napi
);
3331 rtl8169_request_timer(dev
);
3333 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3338 rtl8169_rx_clear(tp
);
3340 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3343 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3348 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
3350 /* Disable interrupts */
3351 rtl8169_irq_mask_and_ack(ioaddr
);
3353 /* Reset the chipset */
3354 RTL_W8(ChipCmd
, CmdReset
);
3360 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
3362 void __iomem
*ioaddr
= tp
->mmio_addr
;
3363 u32 cfg
= rtl8169_rx_config
;
3365 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3366 RTL_W32(RxConfig
, cfg
);
3368 /* Set DMA burst size and Interframe Gap Time */
3369 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3370 (InterFrameGap
<< TxInterFrameGapShift
));
3373 static void rtl_hw_start(struct net_device
*dev
)
3375 struct rtl8169_private
*tp
= netdev_priv(dev
);
3376 void __iomem
*ioaddr
= tp
->mmio_addr
;
3379 /* Soft reset the chip. */
3380 RTL_W8(ChipCmd
, CmdReset
);
3382 /* Check that the chip has finished the reset. */
3383 for (i
= 0; i
< 100; i
++) {
3384 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
3386 msleep_interruptible(1);
3391 netif_start_queue(dev
);
3395 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
3396 void __iomem
*ioaddr
)
3399 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3400 * register to be written before TxDescAddrLow to work.
3401 * Switching from MMIO to I/O access fixes the issue as well.
3403 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
3404 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_BIT_MASK(32));
3405 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
3406 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_BIT_MASK(32));
3409 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
3413 cmd
= RTL_R16(CPlusCmd
);
3414 RTL_W16(CPlusCmd
, cmd
);
3418 static void rtl_set_rx_max_size(void __iomem
*ioaddr
, unsigned int rx_buf_sz
)
3420 /* Low hurts. Let's disable the filtering. */
3421 RTL_W16(RxMaxSize
, rx_buf_sz
+ 1);
3424 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
3426 static const struct {
3431 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
3432 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
3433 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
3434 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
3439 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
3440 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
3441 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
3442 RTL_W32(0x7c, p
->val
);
3448 static void rtl_hw_start_8169(struct net_device
*dev
)
3450 struct rtl8169_private
*tp
= netdev_priv(dev
);
3451 void __iomem
*ioaddr
= tp
->mmio_addr
;
3452 struct pci_dev
*pdev
= tp
->pci_dev
;
3454 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
3455 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
3456 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
3459 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3460 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3461 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3462 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3463 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3464 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3466 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3468 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3470 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
3471 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3472 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
3473 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
3474 rtl_set_rx_tx_config_registers(tp
);
3476 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3478 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
3479 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
3480 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3481 "Bit-3 and bit-14 MUST be 1\n");
3482 tp
->cp_cmd
|= (1 << 14);
3485 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3487 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
3490 * Undocumented corner. Supposedly:
3491 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3493 RTL_W16(IntrMitigate
, 0x0000);
3495 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3497 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
3498 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
3499 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
3500 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
3501 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3502 rtl_set_rx_tx_config_registers(tp
);
3505 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3507 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3510 RTL_W32(RxMissed
, 0);
3512 rtl_set_rx_mode(dev
);
3514 /* no early-rx interrupts */
3515 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3517 /* Enable all known interrupts by setting the interrupt mask. */
3518 RTL_W16(IntrMask
, tp
->intr_event
);
3521 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
3523 struct net_device
*dev
= pci_get_drvdata(pdev
);
3524 struct rtl8169_private
*tp
= netdev_priv(dev
);
3525 int cap
= tp
->pcie_cap
;
3530 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
3531 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
3532 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
3536 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
3540 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
3541 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
3545 unsigned int offset
;
3550 static void rtl_ephy_init(void __iomem
*ioaddr
, const struct ephy_info
*e
, int len
)
3555 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
3556 rtl_ephy_write(ioaddr
, e
->offset
, w
);
3561 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
3563 struct net_device
*dev
= pci_get_drvdata(pdev
);
3564 struct rtl8169_private
*tp
= netdev_priv(dev
);
3565 int cap
= tp
->pcie_cap
;
3570 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
3571 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
3572 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
3576 #define R8168_CPCMD_QUIRK_MASK (\
3587 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3589 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3591 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3593 rtl_tx_performance_tweak(pdev
,
3594 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
3597 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3599 rtl_hw_start_8168bb(ioaddr
, pdev
);
3601 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3603 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
3606 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3608 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
3610 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3612 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3614 rtl_disable_clock_request(pdev
);
3616 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3619 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3621 static const struct ephy_info e_info_8168cp
[] = {
3622 { 0x01, 0, 0x0001 },
3623 { 0x02, 0x0800, 0x1000 },
3624 { 0x03, 0, 0x0042 },
3625 { 0x06, 0x0080, 0x0000 },
3629 rtl_csi_access_enable(ioaddr
);
3631 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
3633 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3636 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3638 rtl_csi_access_enable(ioaddr
);
3640 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3642 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3644 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3647 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3649 rtl_csi_access_enable(ioaddr
);
3651 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3654 RTL_W8(DBG_REG
, 0x20);
3656 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3658 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3660 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3663 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3665 static const struct ephy_info e_info_8168c_1
[] = {
3666 { 0x02, 0x0800, 0x1000 },
3667 { 0x03, 0, 0x0002 },
3668 { 0x06, 0x0080, 0x0000 }
3671 rtl_csi_access_enable(ioaddr
);
3673 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
3675 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
3677 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3680 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3682 static const struct ephy_info e_info_8168c_2
[] = {
3683 { 0x01, 0, 0x0001 },
3684 { 0x03, 0x0400, 0x0220 }
3687 rtl_csi_access_enable(ioaddr
);
3689 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
3691 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3694 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3696 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3699 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3701 rtl_csi_access_enable(ioaddr
);
3703 __rtl_hw_start_8168cp(ioaddr
, pdev
);
3706 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3708 rtl_csi_access_enable(ioaddr
);
3710 rtl_disable_clock_request(pdev
);
3712 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3714 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3716 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
3719 static void rtl_hw_start_8168(struct net_device
*dev
)
3721 struct rtl8169_private
*tp
= netdev_priv(dev
);
3722 void __iomem
*ioaddr
= tp
->mmio_addr
;
3723 struct pci_dev
*pdev
= tp
->pci_dev
;
3725 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3727 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3729 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3731 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
3733 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3735 RTL_W16(IntrMitigate
, 0x5151);
3737 /* Work around for RxFIFO overflow. */
3738 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
3739 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
3740 tp
->intr_event
&= ~RxOverflow
;
3743 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3745 rtl_set_rx_mode(dev
);
3747 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
3748 (InterFrameGap
<< TxInterFrameGapShift
));
3752 switch (tp
->mac_version
) {
3753 case RTL_GIGA_MAC_VER_11
:
3754 rtl_hw_start_8168bb(ioaddr
, pdev
);
3757 case RTL_GIGA_MAC_VER_12
:
3758 case RTL_GIGA_MAC_VER_17
:
3759 rtl_hw_start_8168bef(ioaddr
, pdev
);
3762 case RTL_GIGA_MAC_VER_18
:
3763 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
3766 case RTL_GIGA_MAC_VER_19
:
3767 rtl_hw_start_8168c_1(ioaddr
, pdev
);
3770 case RTL_GIGA_MAC_VER_20
:
3771 rtl_hw_start_8168c_2(ioaddr
, pdev
);
3774 case RTL_GIGA_MAC_VER_21
:
3775 rtl_hw_start_8168c_3(ioaddr
, pdev
);
3778 case RTL_GIGA_MAC_VER_22
:
3779 rtl_hw_start_8168c_4(ioaddr
, pdev
);
3782 case RTL_GIGA_MAC_VER_23
:
3783 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
3786 case RTL_GIGA_MAC_VER_24
:
3787 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
3790 case RTL_GIGA_MAC_VER_25
:
3791 case RTL_GIGA_MAC_VER_26
:
3792 case RTL_GIGA_MAC_VER_27
:
3793 rtl_hw_start_8168d(ioaddr
, pdev
);
3797 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
3798 dev
->name
, tp
->mac_version
);
3802 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3804 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3806 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
3808 RTL_W16(IntrMask
, tp
->intr_event
);
3811 #define R810X_CPCMD_QUIRK_MASK (\
3823 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3825 static const struct ephy_info e_info_8102e_1
[] = {
3826 { 0x01, 0, 0x6e65 },
3827 { 0x02, 0, 0x091f },
3828 { 0x03, 0, 0xc2f9 },
3829 { 0x06, 0, 0xafb5 },
3830 { 0x07, 0, 0x0e00 },
3831 { 0x19, 0, 0xec80 },
3832 { 0x01, 0, 0x2e65 },
3837 rtl_csi_access_enable(ioaddr
);
3839 RTL_W8(DBG_REG
, FIX_NAK_1
);
3841 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3844 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
3845 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3847 cfg1
= RTL_R8(Config1
);
3848 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
3849 RTL_W8(Config1
, cfg1
& ~LEDS0
);
3851 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3853 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
3856 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3858 rtl_csi_access_enable(ioaddr
);
3860 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
3862 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
3863 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
3865 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
3868 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
3870 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3872 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
3875 static void rtl_hw_start_8101(struct net_device
*dev
)
3877 struct rtl8169_private
*tp
= netdev_priv(dev
);
3878 void __iomem
*ioaddr
= tp
->mmio_addr
;
3879 struct pci_dev
*pdev
= tp
->pci_dev
;
3881 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
3882 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
3883 int cap
= tp
->pcie_cap
;
3886 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
3887 PCI_EXP_DEVCTL_NOSNOOP_EN
);
3891 switch (tp
->mac_version
) {
3892 case RTL_GIGA_MAC_VER_07
:
3893 rtl_hw_start_8102e_1(ioaddr
, pdev
);
3896 case RTL_GIGA_MAC_VER_08
:
3897 rtl_hw_start_8102e_3(ioaddr
, pdev
);
3900 case RTL_GIGA_MAC_VER_09
:
3901 rtl_hw_start_8102e_2(ioaddr
, pdev
);
3905 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
3907 RTL_W8(EarlyTxThres
, EarlyTxThld
);
3909 rtl_set_rx_max_size(ioaddr
, tp
->rx_buf_sz
);
3911 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
3913 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3915 RTL_W16(IntrMitigate
, 0x0000);
3917 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
3919 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3920 rtl_set_rx_tx_config_registers(tp
);
3922 RTL_W8(Cfg9346
, Cfg9346_Lock
);
3926 rtl_set_rx_mode(dev
);
3928 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
3930 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
3932 RTL_W16(IntrMask
, tp
->intr_event
);
3935 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
3937 struct rtl8169_private
*tp
= netdev_priv(dev
);
3940 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
3945 if (!netif_running(dev
))
3950 rtl8169_set_rxbufsize(tp
, dev
->mtu
);
3952 ret
= rtl8169_init_ring(dev
);
3956 napi_enable(&tp
->napi
);
3960 rtl8169_request_timer(dev
);
3966 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
3968 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
3969 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
3972 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
3973 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
3975 struct pci_dev
*pdev
= tp
->pci_dev
;
3977 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
3978 PCI_DMA_FROMDEVICE
);
3979 dev_kfree_skb(*sk_buff
);
3981 rtl8169_make_unusable_by_asic(desc
);
3984 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
3986 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
3988 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
3991 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
3994 desc
->addr
= cpu_to_le64(mapping
);
3996 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
3999 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
4000 struct net_device
*dev
,
4001 struct RxDesc
*desc
, int rx_buf_sz
,
4004 struct sk_buff
*skb
;
4008 pad
= align
? align
: NET_IP_ALIGN
;
4010 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
4014 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
4016 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
4017 PCI_DMA_FROMDEVICE
);
4019 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
4024 rtl8169_make_unusable_by_asic(desc
);
4028 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
4032 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
4033 if (tp
->Rx_skbuff
[i
]) {
4034 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
4035 tp
->RxDescArray
+ i
);
4040 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
4045 for (cur
= start
; end
- cur
!= 0; cur
++) {
4046 struct sk_buff
*skb
;
4047 unsigned int i
= cur
% NUM_RX_DESC
;
4049 WARN_ON((s32
)(end
- cur
) < 0);
4051 if (tp
->Rx_skbuff
[i
])
4054 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
4055 tp
->RxDescArray
+ i
,
4056 tp
->rx_buf_sz
, tp
->align
);
4060 tp
->Rx_skbuff
[i
] = skb
;
4065 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
4067 desc
->opts1
|= cpu_to_le32(RingEnd
);
4070 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
4072 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
4075 static int rtl8169_init_ring(struct net_device
*dev
)
4077 struct rtl8169_private
*tp
= netdev_priv(dev
);
4079 rtl8169_init_ring_indexes(tp
);
4081 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
4082 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
4084 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
4087 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
4092 rtl8169_rx_clear(tp
);
4096 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
4097 struct TxDesc
*desc
)
4099 unsigned int len
= tx_skb
->len
;
4101 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
4108 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
4112 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
4113 unsigned int entry
= i
% NUM_TX_DESC
;
4114 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4115 unsigned int len
= tx_skb
->len
;
4118 struct sk_buff
*skb
= tx_skb
->skb
;
4120 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
4121 tp
->TxDescArray
+ entry
);
4126 tp
->dev
->stats
.tx_dropped
++;
4129 tp
->cur_tx
= tp
->dirty_tx
= 0;
4132 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
4134 struct rtl8169_private
*tp
= netdev_priv(dev
);
4136 PREPARE_DELAYED_WORK(&tp
->task
, task
);
4137 schedule_delayed_work(&tp
->task
, 4);
4140 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
4142 struct rtl8169_private
*tp
= netdev_priv(dev
);
4143 void __iomem
*ioaddr
= tp
->mmio_addr
;
4145 synchronize_irq(dev
->irq
);
4147 /* Wait for any pending NAPI task to complete */
4148 napi_disable(&tp
->napi
);
4150 rtl8169_irq_mask_and_ack(ioaddr
);
4152 tp
->intr_mask
= 0xffff;
4153 RTL_W16(IntrMask
, tp
->intr_event
);
4154 napi_enable(&tp
->napi
);
4157 static void rtl8169_reinit_task(struct work_struct
*work
)
4159 struct rtl8169_private
*tp
=
4160 container_of(work
, struct rtl8169_private
, task
.work
);
4161 struct net_device
*dev
= tp
->dev
;
4166 if (!netif_running(dev
))
4169 rtl8169_wait_for_quiescence(dev
);
4172 ret
= rtl8169_open(dev
);
4173 if (unlikely(ret
< 0)) {
4174 if (net_ratelimit() && netif_msg_drv(tp
)) {
4175 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
4176 " Rescheduling.\n", dev
->name
, ret
);
4178 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4185 static void rtl8169_reset_task(struct work_struct
*work
)
4187 struct rtl8169_private
*tp
=
4188 container_of(work
, struct rtl8169_private
, task
.work
);
4189 struct net_device
*dev
= tp
->dev
;
4193 if (!netif_running(dev
))
4196 rtl8169_wait_for_quiescence(dev
);
4198 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
4199 rtl8169_tx_clear(tp
);
4201 if (tp
->dirty_rx
== tp
->cur_rx
) {
4202 rtl8169_init_ring_indexes(tp
);
4204 netif_wake_queue(dev
);
4205 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
4207 if (net_ratelimit() && netif_msg_intr(tp
)) {
4208 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
4211 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4218 static void rtl8169_tx_timeout(struct net_device
*dev
)
4220 struct rtl8169_private
*tp
= netdev_priv(dev
);
4222 rtl8169_hw_reset(tp
->mmio_addr
);
4224 /* Let's wait a bit while any (async) irq lands on */
4225 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4228 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
4231 struct skb_shared_info
*info
= skb_shinfo(skb
);
4232 unsigned int cur_frag
, entry
;
4233 struct TxDesc
* uninitialized_var(txd
);
4236 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
4237 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
4242 entry
= (entry
+ 1) % NUM_TX_DESC
;
4244 txd
= tp
->TxDescArray
+ entry
;
4246 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
4247 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
4249 /* anti gcc 2.95.3 bugware (sic) */
4250 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4252 txd
->opts1
= cpu_to_le32(status
);
4253 txd
->addr
= cpu_to_le64(mapping
);
4255 tp
->tx_skb
[entry
].len
= len
;
4259 tp
->tx_skb
[entry
].skb
= skb
;
4260 txd
->opts1
|= cpu_to_le32(LastFrag
);
4266 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
4268 if (dev
->features
& NETIF_F_TSO
) {
4269 u32 mss
= skb_shinfo(skb
)->gso_size
;
4272 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
4274 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
4275 const struct iphdr
*ip
= ip_hdr(skb
);
4277 if (ip
->protocol
== IPPROTO_TCP
)
4278 return IPCS
| TCPCS
;
4279 else if (ip
->protocol
== IPPROTO_UDP
)
4280 return IPCS
| UDPCS
;
4281 WARN_ON(1); /* we need a WARN() */
4286 static netdev_tx_t
rtl8169_start_xmit(struct sk_buff
*skb
,
4287 struct net_device
*dev
)
4289 struct rtl8169_private
*tp
= netdev_priv(dev
);
4290 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
4291 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
4292 void __iomem
*ioaddr
= tp
->mmio_addr
;
4297 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
4298 if (netif_msg_drv(tp
)) {
4300 "%s: BUG! Tx Ring full when queue awake!\n",
4306 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
4309 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
4311 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
4313 len
= skb_headlen(skb
);
4317 opts1
|= FirstFrag
| LastFrag
;
4318 tp
->tx_skb
[entry
].skb
= skb
;
4321 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
4323 tp
->tx_skb
[entry
].len
= len
;
4324 txd
->addr
= cpu_to_le64(mapping
);
4325 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
4329 /* anti gcc 2.95.3 bugware (sic) */
4330 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
4331 txd
->opts1
= cpu_to_le32(status
);
4333 tp
->cur_tx
+= frags
+ 1;
4337 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
4339 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
4340 netif_stop_queue(dev
);
4342 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
4343 netif_wake_queue(dev
);
4346 return NETDEV_TX_OK
;
4349 netif_stop_queue(dev
);
4350 dev
->stats
.tx_dropped
++;
4351 return NETDEV_TX_BUSY
;
4354 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
4356 struct rtl8169_private
*tp
= netdev_priv(dev
);
4357 struct pci_dev
*pdev
= tp
->pci_dev
;
4358 void __iomem
*ioaddr
= tp
->mmio_addr
;
4359 u16 pci_status
, pci_cmd
;
4361 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
4362 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
4364 if (netif_msg_intr(tp
)) {
4366 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
4367 dev
->name
, pci_cmd
, pci_status
);
4371 * The recovery sequence below admits a very elaborated explanation:
4372 * - it seems to work;
4373 * - I did not see what else could be done;
4374 * - it makes iop3xx happy.
4376 * Feel free to adjust to your needs.
4378 if (pdev
->broken_parity_status
)
4379 pci_cmd
&= ~PCI_COMMAND_PARITY
;
4381 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
4383 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
4385 pci_write_config_word(pdev
, PCI_STATUS
,
4386 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
4387 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
4388 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
4390 /* The infamous DAC f*ckup only happens at boot time */
4391 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
4392 if (netif_msg_intr(tp
))
4393 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
4394 tp
->cp_cmd
&= ~PCIDAC
;
4395 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
4396 dev
->features
&= ~NETIF_F_HIGHDMA
;
4399 rtl8169_hw_reset(ioaddr
);
4401 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
4404 static void rtl8169_tx_interrupt(struct net_device
*dev
,
4405 struct rtl8169_private
*tp
,
4406 void __iomem
*ioaddr
)
4408 unsigned int dirty_tx
, tx_left
;
4410 dirty_tx
= tp
->dirty_tx
;
4412 tx_left
= tp
->cur_tx
- dirty_tx
;
4414 while (tx_left
> 0) {
4415 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
4416 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
4417 u32 len
= tx_skb
->len
;
4421 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
4422 if (status
& DescOwn
)
4425 dev
->stats
.tx_bytes
+= len
;
4426 dev
->stats
.tx_packets
++;
4428 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
4430 if (status
& LastFrag
) {
4431 dev_kfree_skb(tx_skb
->skb
);
4438 if (tp
->dirty_tx
!= dirty_tx
) {
4439 tp
->dirty_tx
= dirty_tx
;
4441 if (netif_queue_stopped(dev
) &&
4442 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
4443 netif_wake_queue(dev
);
4446 * 8168 hack: TxPoll requests are lost when the Tx packets are
4447 * too close. Let's kick an extra TxPoll request when a burst
4448 * of start_xmit activity is detected (if it is not detected,
4449 * it is slow enough). -- FR
4452 if (tp
->cur_tx
!= dirty_tx
)
4453 RTL_W8(TxPoll
, NPQ
);
4457 static inline int rtl8169_fragmented_frame(u32 status
)
4459 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
4462 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
4464 u32 opts1
= le32_to_cpu(desc
->opts1
);
4465 u32 status
= opts1
& RxProtoMask
;
4467 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
4468 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
4469 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
4470 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
4472 skb
->ip_summed
= CHECKSUM_NONE
;
4475 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
4476 struct rtl8169_private
*tp
, int pkt_size
,
4479 struct sk_buff
*skb
;
4482 if (pkt_size
>= rx_copybreak
)
4485 skb
= netdev_alloc_skb_ip_align(tp
->dev
, pkt_size
);
4489 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
4490 PCI_DMA_FROMDEVICE
);
4491 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
4498 static int rtl8169_rx_interrupt(struct net_device
*dev
,
4499 struct rtl8169_private
*tp
,
4500 void __iomem
*ioaddr
, u32 budget
)
4502 unsigned int cur_rx
, rx_left
;
4503 unsigned int delta
, count
;
4505 cur_rx
= tp
->cur_rx
;
4506 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
4507 rx_left
= min(rx_left
, budget
);
4509 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
4510 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
4511 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
4515 status
= le32_to_cpu(desc
->opts1
);
4517 if (status
& DescOwn
)
4519 if (unlikely(status
& RxRES
)) {
4520 if (netif_msg_rx_err(tp
)) {
4522 "%s: Rx ERROR. status = %08x\n",
4525 dev
->stats
.rx_errors
++;
4526 if (status
& (RxRWT
| RxRUNT
))
4527 dev
->stats
.rx_length_errors
++;
4529 dev
->stats
.rx_crc_errors
++;
4530 if (status
& RxFOVF
) {
4531 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4532 dev
->stats
.rx_fifo_errors
++;
4534 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4536 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
4537 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
4538 int pkt_size
= (status
& 0x00001FFF) - 4;
4539 struct pci_dev
*pdev
= tp
->pci_dev
;
4542 * The driver does not support incoming fragmented
4543 * frames. They are seen as a symptom of over-mtu
4546 if (unlikely(rtl8169_fragmented_frame(status
))) {
4547 dev
->stats
.rx_dropped
++;
4548 dev
->stats
.rx_length_errors
++;
4549 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4553 rtl8169_rx_csum(skb
, desc
);
4555 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
4556 pci_dma_sync_single_for_device(pdev
, addr
,
4557 pkt_size
, PCI_DMA_FROMDEVICE
);
4558 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
4560 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
4561 PCI_DMA_FROMDEVICE
);
4562 tp
->Rx_skbuff
[entry
] = NULL
;
4565 skb_put(skb
, pkt_size
);
4566 skb
->protocol
= eth_type_trans(skb
, dev
);
4568 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
4569 netif_receive_skb(skb
);
4571 dev
->stats
.rx_bytes
+= pkt_size
;
4572 dev
->stats
.rx_packets
++;
4575 /* Work around for AMD plateform. */
4576 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
4577 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
4583 count
= cur_rx
- tp
->cur_rx
;
4584 tp
->cur_rx
= cur_rx
;
4586 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
4587 if (!delta
&& count
&& netif_msg_intr(tp
))
4588 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
4589 tp
->dirty_rx
+= delta
;
4592 * FIXME: until there is periodic timer to try and refill the ring,
4593 * a temporary shortage may definitely kill the Rx process.
4594 * - disable the asic to try and avoid an overflow and kick it again
4596 * - how do others driver handle this condition (Uh oh...).
4598 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
4599 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
4604 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
4606 struct net_device
*dev
= dev_instance
;
4607 struct rtl8169_private
*tp
= netdev_priv(dev
);
4608 void __iomem
*ioaddr
= tp
->mmio_addr
;
4612 /* loop handling interrupts until we have no new ones or
4613 * we hit a invalid/hotplug case.
4615 status
= RTL_R16(IntrStatus
);
4616 while (status
&& status
!= 0xffff) {
4619 /* Handle all of the error cases first. These will reset
4620 * the chip, so just exit the loop.
4622 if (unlikely(!netif_running(dev
))) {
4623 rtl8169_asic_down(ioaddr
);
4627 /* Work around for rx fifo overflow */
4628 if (unlikely(status
& RxFIFOOver
) &&
4629 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
4630 netif_stop_queue(dev
);
4631 rtl8169_tx_timeout(dev
);
4635 if (unlikely(status
& SYSErr
)) {
4636 rtl8169_pcierr_interrupt(dev
);
4640 if (status
& LinkChg
)
4641 rtl8169_check_link_status(dev
, tp
, ioaddr
);
4643 /* We need to see the lastest version of tp->intr_mask to
4644 * avoid ignoring an MSI interrupt and having to wait for
4645 * another event which may never come.
4648 if (status
& tp
->intr_mask
& tp
->napi_event
) {
4649 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
4650 tp
->intr_mask
= ~tp
->napi_event
;
4652 if (likely(napi_schedule_prep(&tp
->napi
)))
4653 __napi_schedule(&tp
->napi
);
4654 else if (netif_msg_intr(tp
)) {
4655 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
4660 /* We only get a new MSI interrupt when all active irq
4661 * sources on the chip have been acknowledged. So, ack
4662 * everything we've seen and check if new sources have become
4663 * active to avoid blocking all interrupts from the chip.
4666 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
4667 status
= RTL_R16(IntrStatus
);
4670 return IRQ_RETVAL(handled
);
4673 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
4675 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
4676 struct net_device
*dev
= tp
->dev
;
4677 void __iomem
*ioaddr
= tp
->mmio_addr
;
4680 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
4681 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
4683 if (work_done
< budget
) {
4684 napi_complete(napi
);
4686 /* We need for force the visibility of tp->intr_mask
4687 * for other CPUs, as we can loose an MSI interrupt
4688 * and potentially wait for a retransmit timeout if we don't.
4689 * The posted write to IntrMask is safe, as it will
4690 * eventually make it to the chip and we won't loose anything
4693 tp
->intr_mask
= 0xffff;
4695 RTL_W16(IntrMask
, tp
->intr_event
);
4701 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
4703 struct rtl8169_private
*tp
= netdev_priv(dev
);
4705 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
4708 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
4709 RTL_W32(RxMissed
, 0);
4712 static void rtl8169_down(struct net_device
*dev
)
4714 struct rtl8169_private
*tp
= netdev_priv(dev
);
4715 void __iomem
*ioaddr
= tp
->mmio_addr
;
4716 unsigned int intrmask
;
4718 rtl8169_delete_timer(dev
);
4720 netif_stop_queue(dev
);
4722 napi_disable(&tp
->napi
);
4725 spin_lock_irq(&tp
->lock
);
4727 rtl8169_asic_down(ioaddr
);
4729 rtl8169_rx_missed(dev
, ioaddr
);
4731 spin_unlock_irq(&tp
->lock
);
4733 synchronize_irq(dev
->irq
);
4735 /* Give a racing hard_start_xmit a few cycles to complete. */
4736 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4739 * And now for the 50k$ question: are IRQ disabled or not ?
4741 * Two paths lead here:
4743 * -> netif_running() is available to sync the current code and the
4744 * IRQ handler. See rtl8169_interrupt for details.
4745 * 2) dev->change_mtu
4746 * -> rtl8169_poll can not be issued again and re-enable the
4747 * interruptions. Let's simply issue the IRQ down sequence again.
4749 * No loop if hotpluged or major error (0xffff).
4751 intrmask
= RTL_R16(IntrMask
);
4752 if (intrmask
&& (intrmask
!= 0xffff))
4755 rtl8169_tx_clear(tp
);
4757 rtl8169_rx_clear(tp
);
4760 static int rtl8169_close(struct net_device
*dev
)
4762 struct rtl8169_private
*tp
= netdev_priv(dev
);
4763 struct pci_dev
*pdev
= tp
->pci_dev
;
4765 /* update counters before going down */
4766 rtl8169_update_counters(dev
);
4770 free_irq(dev
->irq
, dev
);
4772 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
4774 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
4776 tp
->TxDescArray
= NULL
;
4777 tp
->RxDescArray
= NULL
;
4782 static void rtl_set_rx_mode(struct net_device
*dev
)
4784 struct rtl8169_private
*tp
= netdev_priv(dev
);
4785 void __iomem
*ioaddr
= tp
->mmio_addr
;
4786 unsigned long flags
;
4787 u32 mc_filter
[2]; /* Multicast hash filter */
4791 if (dev
->flags
& IFF_PROMISC
) {
4792 /* Unconditionally log net taps. */
4793 if (netif_msg_link(tp
)) {
4794 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
4798 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
4800 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4801 } else if ((dev
->mc_count
> multicast_filter_limit
) ||
4802 (dev
->flags
& IFF_ALLMULTI
)) {
4803 /* Too many to filter perfectly -- accept all multicasts. */
4804 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
4805 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
4807 struct dev_mc_list
*mclist
;
4810 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
4811 mc_filter
[1] = mc_filter
[0] = 0;
4812 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
4813 i
++, mclist
= mclist
->next
) {
4814 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
4815 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
4816 rx_mode
|= AcceptMulticast
;
4820 spin_lock_irqsave(&tp
->lock
, flags
);
4822 tmp
= rtl8169_rx_config
| rx_mode
|
4823 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
4825 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
4826 u32 data
= mc_filter
[0];
4828 mc_filter
[0] = swab32(mc_filter
[1]);
4829 mc_filter
[1] = swab32(data
);
4832 RTL_W32(MAR0
+ 4, mc_filter
[1]);
4833 RTL_W32(MAR0
+ 0, mc_filter
[0]);
4835 RTL_W32(RxConfig
, tmp
);
4837 spin_unlock_irqrestore(&tp
->lock
, flags
);
4841 * rtl8169_get_stats - Get rtl8169 read/write statistics
4842 * @dev: The Ethernet Device to get statistics for
4844 * Get TX/RX statistics for rtl8169
4846 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
4848 struct rtl8169_private
*tp
= netdev_priv(dev
);
4849 void __iomem
*ioaddr
= tp
->mmio_addr
;
4850 unsigned long flags
;
4852 if (netif_running(dev
)) {
4853 spin_lock_irqsave(&tp
->lock
, flags
);
4854 rtl8169_rx_missed(dev
, ioaddr
);
4855 spin_unlock_irqrestore(&tp
->lock
, flags
);
4861 static void rtl8169_net_suspend(struct net_device
*dev
)
4863 if (!netif_running(dev
))
4866 netif_device_detach(dev
);
4867 netif_stop_queue(dev
);
4872 static int rtl8169_suspend(struct device
*device
)
4874 struct pci_dev
*pdev
= to_pci_dev(device
);
4875 struct net_device
*dev
= pci_get_drvdata(pdev
);
4877 rtl8169_net_suspend(dev
);
4882 static int rtl8169_resume(struct device
*device
)
4884 struct pci_dev
*pdev
= to_pci_dev(device
);
4885 struct net_device
*dev
= pci_get_drvdata(pdev
);
4887 if (!netif_running(dev
))
4890 netif_device_attach(dev
);
4892 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
4897 static const struct dev_pm_ops rtl8169_pm_ops
= {
4898 .suspend
= rtl8169_suspend
,
4899 .resume
= rtl8169_resume
,
4900 .freeze
= rtl8169_suspend
,
4901 .thaw
= rtl8169_resume
,
4902 .poweroff
= rtl8169_suspend
,
4903 .restore
= rtl8169_resume
,
4906 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4908 #else /* !CONFIG_PM */
4910 #define RTL8169_PM_OPS NULL
4912 #endif /* !CONFIG_PM */
4914 static void rtl_shutdown(struct pci_dev
*pdev
)
4916 struct net_device
*dev
= pci_get_drvdata(pdev
);
4917 struct rtl8169_private
*tp
= netdev_priv(dev
);
4918 void __iomem
*ioaddr
= tp
->mmio_addr
;
4920 rtl8169_net_suspend(dev
);
4922 /* restore original MAC address */
4923 rtl_rar_set(tp
, dev
->perm_addr
);
4925 spin_lock_irq(&tp
->lock
);
4927 rtl8169_asic_down(ioaddr
);
4929 spin_unlock_irq(&tp
->lock
);
4931 if (system_state
== SYSTEM_POWER_OFF
) {
4932 /* WoL fails with some 8168 when the receiver is disabled. */
4933 if (tp
->features
& RTL_FEATURE_WOL
) {
4934 pci_clear_master(pdev
);
4936 RTL_W8(ChipCmd
, CmdRxEnb
);
4941 pci_wake_from_d3(pdev
, true);
4942 pci_set_power_state(pdev
, PCI_D3hot
);
4946 static struct pci_driver rtl8169_pci_driver
= {
4948 .id_table
= rtl8169_pci_tbl
,
4949 .probe
= rtl8169_init_one
,
4950 .remove
= __devexit_p(rtl8169_remove_one
),
4951 .shutdown
= rtl_shutdown
,
4952 .driver
.pm
= RTL8169_PM_OPS
,
4955 static int __init
rtl8169_init_module(void)
4957 return pci_register_driver(&rtl8169_pci_driver
);
4960 static void __exit
rtl8169_cleanup_module(void)
4962 pci_unregister_driver(&rtl8169_pci_driver
);
4965 module_init(rtl8169_init_module
);
4966 module_exit(rtl8169_cleanup_module
);