include/asm-mips/jmr3927/txx927.h

   1 /*
   2  * Common definitions for TX3927/TX4927
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Toshiba Corporation
   9  */
  10 #ifndef __ASM_TXX927_H
  11 #define __ASM_TXX927_H
  12
  13 struct txx927_sio_reg {
  14         volatile unsigned long lcr;
  15         volatile unsigned long dicr;
  16         volatile unsigned long disr;
  17         volatile unsigned long cisr;
  18         volatile unsigned long fcr;
  19         volatile unsigned long flcr;
  20         volatile unsigned long bgr;
  21         volatile unsigned long tfifo;
  22         volatile unsigned long rfifo;
  23 };
  24
  25 struct txx927_pio_reg {
  26         volatile unsigned long dout;
  27         volatile unsigned long din;
  28         volatile unsigned long dir;
  29         volatile unsigned long od;
  30         volatile unsigned long flag[2];
  31         volatile unsigned long pol;
  32         volatile unsigned long intc;
  33         volatile unsigned long maskcpu;
  34         volatile unsigned long maskext;
  35 };
  36
  37 /*
  38  * SIO
  39  */
  40 /* SILCR : Line Control */
  41 #define TXx927_SILCR_SCS_MASK   0x00000060
  42 #define TXx927_SILCR_SCS_IMCLK  0x00000000
  43 #define TXx927_SILCR_SCS_IMCLK_BG       0x00000020
  44 #define TXx927_SILCR_SCS_SCLK   0x00000040
  45 #define TXx927_SILCR_SCS_SCLK_BG        0x00000060
  46 #define TXx927_SILCR_UEPS       0x00000010
  47 #define TXx927_SILCR_UPEN       0x00000008
  48 #define TXx927_SILCR_USBL_MASK  0x00000004
  49 #define TXx927_SILCR_USBL_1BIT  0x00000004
  50 #define TXx927_SILCR_USBL_2BIT  0x00000000
  51 #define TXx927_SILCR_UMODE_MASK 0x00000003
  52 #define TXx927_SILCR_UMODE_8BIT 0x00000000
  53 #define TXx927_SILCR_UMODE_7BIT 0x00000001
  54
  55 /* SIDICR : DMA/Int. Control */
  56 #define TXx927_SIDICR_TDE       0x00008000
  57 #define TXx927_SIDICR_RDE       0x00004000
  58 #define TXx927_SIDICR_TIE       0x00002000
  59 #define TXx927_SIDICR_RIE       0x00001000
  60 #define TXx927_SIDICR_SPIE      0x00000800
  61 #define TXx927_SIDICR_CTSAC     0x00000600
  62 #define TXx927_SIDICR_STIE_MASK 0x0000003f
  63 #define TXx927_SIDICR_STIE_OERS         0x00000020
  64 #define TXx927_SIDICR_STIE_CTSS         0x00000010
  65 #define TXx927_SIDICR_STIE_RBRKD        0x00000008
  66 #define TXx927_SIDICR_STIE_TRDY         0x00000004
  67 #define TXx927_SIDICR_STIE_TXALS        0x00000002
  68 #define TXx927_SIDICR_STIE_UBRKD        0x00000001
  69
  70 /* SIDISR : DMA/Int. Status */
  71 #define TXx927_SIDISR_UBRK      0x00008000
  72 #define TXx927_SIDISR_UVALID    0x00004000
  73 #define TXx927_SIDISR_UFER      0x00002000
  74 #define TXx927_SIDISR_UPER      0x00001000
  75 #define TXx927_SIDISR_UOER      0x00000800
  76 #define TXx927_SIDISR_ERI       0x00000400
  77 #define TXx927_SIDISR_TOUT      0x00000200
  78 #define TXx927_SIDISR_TDIS      0x00000100
  79 #define TXx927_SIDISR_RDIS      0x00000080
  80 #define TXx927_SIDISR_STIS      0x00000040
  81 #define TXx927_SIDISR_RFDN_MASK 0x0000001f
  82
  83 /* SICISR : Change Int. Status */
  84 #define TXx927_SICISR_OERS      0x00000020
  85 #define TXx927_SICISR_CTSS      0x00000010
  86 #define TXx927_SICISR_RBRKD     0x00000008
  87 #define TXx927_SICISR_TRDY      0x00000004
  88 #define TXx927_SICISR_TXALS     0x00000002
  89 #define TXx927_SICISR_UBRKD     0x00000001
  90
  91 /* SIFCR : FIFO Control */
  92 #define TXx927_SIFCR_SWRST      0x00008000
  93 #define TXx927_SIFCR_RDIL_MASK  0x00000180
  94 #define TXx927_SIFCR_RDIL_1     0x00000000
  95 #define TXx927_SIFCR_RDIL_4     0x00000080
  96 #define TXx927_SIFCR_RDIL_8     0x00000100
  97 #define TXx927_SIFCR_RDIL_12    0x00000180
  98 #define TXx927_SIFCR_RDIL_MAX   0x00000180
  99 #define TXx927_SIFCR_TDIL_MASK  0x00000018
 100 #define TXx927_SIFCR_TDIL_MASK  0x00000018
 101 #define TXx927_SIFCR_TDIL_1     0x00000000
 102 #define TXx927_SIFCR_TDIL_4     0x00000001
 103 #define TXx927_SIFCR_TDIL_8     0x00000010
 104 #define TXx927_SIFCR_TDIL_MAX   0x00000010
 105 #define TXx927_SIFCR_TFRST      0x00000004
 106 #define TXx927_SIFCR_RFRST      0x00000002
 107 #define TXx927_SIFCR_FRSTE      0x00000001
 108 #define TXx927_SIO_TX_FIFO      8
 109 #define TXx927_SIO_RX_FIFO      16
 110
 111 /* SIFLCR : Flow Control */
 112 #define TXx927_SIFLCR_RCS       0x00001000
 113 #define TXx927_SIFLCR_TES       0x00000800
 114 #define TXx927_SIFLCR_RTSSC     0x00000200
 115 #define TXx927_SIFLCR_RSDE      0x00000100
 116 #define TXx927_SIFLCR_TSDE      0x00000080
 117 #define TXx927_SIFLCR_RTSTL_MASK        0x0000001e
 118 #define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
 119 #define TXx927_SIFLCR_TBRK      0x00000001
 120
 121 /* SIBGR : Baudrate Control */
 122 #define TXx927_SIBGR_BCLK_MASK  0x00000300
 123 #define TXx927_SIBGR_BCLK_T0    0x00000000
 124 #define TXx927_SIBGR_BCLK_T2    0x00000100
 125 #define TXx927_SIBGR_BCLK_T4    0x00000200
 126 #define TXx927_SIBGR_BCLK_T6    0x00000300
 127 #define TXx927_SIBGR_BRD_MASK   0x000000ff
 128
 129 /*
 130  * PIO
 131  */
 132
 133 #endif /* __ASM_TXX927_H */