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intel-gtt: introduce drm/intel-gtt.h
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
blob47228cb169013808b4bd74cc05ae1da51effa76b
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/pci.h>
38 #include <linux/vgaarb.h>
39 #include <linux/acpi.h>
40 #include <linux/pnp.h>
41 #include <linux/vga_switcheroo.h>
42 #include <linux/slab.h>
43 #include <acpi/video.h>
44
45 /**
46 * Sets up the hardware status page for devices that need a physical address
47 * in the register.
48 */
49 static int i915_init_phys_hws(struct drm_device *dev)
50 {
51 drm_i915_private_t *dev_priv = dev->dev_private;
52 /* Program Hardware Status Page */
53 dev_priv->status_page_dmah =
54 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
55
56 if (!dev_priv->status_page_dmah) {
57 DRM_ERROR("Can not allocate hardware status page\n");
58 return -ENOMEM;
59 }
60 dev_priv->render_ring.status_page.page_addr
61 = dev_priv->status_page_dmah->vaddr;
62 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
63
64 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
65
66 if (IS_I965G(dev))
67 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
68 0xf0;
69
70 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
71 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
72 return 0;
73 }
74
75 /**
76 * Frees the hardware status page, whether it's a physical address or a virtual
77 * address set up by the X Server.
78 */
79 static void i915_free_hws(struct drm_device *dev)
80 {
81 drm_i915_private_t *dev_priv = dev->dev_private;
82 if (dev_priv->status_page_dmah) {
83 drm_pci_free(dev, dev_priv->status_page_dmah);
84 dev_priv->status_page_dmah = NULL;
85 }
86
87 if (dev_priv->render_ring.status_page.gfx_addr) {
88 dev_priv->render_ring.status_page.gfx_addr = 0;
89 drm_core_ioremapfree(&dev_priv->hws_map, dev);
90 }
91
92 /* Need to rewrite hardware status page */
93 I915_WRITE(HWS_PGA, 0x1ffff000);
94 }
95
96 void i915_kernel_lost_context(struct drm_device * dev)
97 {
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 struct drm_i915_master_private *master_priv;
100 struct intel_ring_buffer *ring = &dev_priv->render_ring;
101
102 /*
103 * We should never lose context on the ring with modesetting
104 * as we don't expose it to userspace
105 */
106 if (drm_core_check_feature(dev, DRIVER_MODESET))
107 return;
108
109 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
110 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
111 ring->space = ring->head - (ring->tail + 8);
112 if (ring->space < 0)
113 ring->space += ring->size;
114
115 if (!dev->primary->master)
116 return;
117
118 master_priv = dev->primary->master->driver_priv;
119 if (ring->head == ring->tail && master_priv->sarea_priv)
120 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
121 }
122
123 static int i915_dma_cleanup(struct drm_device * dev)
124 {
125 drm_i915_private_t *dev_priv = dev->dev_private;
126 /* Make sure interrupts are disabled here because the uninstall ioctl
127 * may not have been called from userspace and after dev_private
128 * is freed, it's too late.
129 */
130 if (dev->irq_enabled)
131 drm_irq_uninstall(dev);
132
133 mutex_lock(&dev->struct_mutex);
134 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
135 if (HAS_BSD(dev))
136 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
137 mutex_unlock(&dev->struct_mutex);
138
139 /* Clear the HWS virtual address at teardown */
140 if (I915_NEED_GFX_HWS(dev))
141 i915_free_hws(dev);
142
143 return 0;
144 }
145
146 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
147 {
148 drm_i915_private_t *dev_priv = dev->dev_private;
149 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
150
151 master_priv->sarea = drm_getsarea(dev);
152 if (master_priv->sarea) {
153 master_priv->sarea_priv = (drm_i915_sarea_t *)
154 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
155 } else {
156 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
157 }
158
159 if (init->ring_size != 0) {
160 if (dev_priv->render_ring.gem_object != NULL) {
161 i915_dma_cleanup(dev);
162 DRM_ERROR("Client tried to initialize ringbuffer in "
163 "GEM mode\n");
164 return -EINVAL;
165 }
166
167 dev_priv->render_ring.size = init->ring_size;
168
169 dev_priv->render_ring.map.offset = init->ring_start;
170 dev_priv->render_ring.map.size = init->ring_size;
171 dev_priv->render_ring.map.type = 0;
172 dev_priv->render_ring.map.flags = 0;
173 dev_priv->render_ring.map.mtrr = 0;
174
175 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
176
177 if (dev_priv->render_ring.map.handle == NULL) {
178 i915_dma_cleanup(dev);
179 DRM_ERROR("can not ioremap virtual address for"
180 " ring buffer\n");
181 return -ENOMEM;
182 }
183 }
184
185 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
186
187 dev_priv->cpp = init->cpp;
188 dev_priv->back_offset = init->back_offset;
189 dev_priv->front_offset = init->front_offset;
190 dev_priv->current_page = 0;
191 if (master_priv->sarea_priv)
192 master_priv->sarea_priv->pf_current_page = 0;
193
194 /* Allow hardware batchbuffers unless told otherwise.
195 */
196 dev_priv->allow_batchbuffer = 1;
197
198 return 0;
199 }
200
201 static int i915_dma_resume(struct drm_device * dev)
202 {
203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
204
205 struct intel_ring_buffer *ring;
206 DRM_DEBUG_DRIVER("%s\n", __func__);
207
208 ring = &dev_priv->render_ring;
209
210 if (ring->map.handle == NULL) {
211 DRM_ERROR("can not ioremap virtual address for"
212 " ring buffer\n");
213 return -ENOMEM;
214 }
215
216 /* Program Hardware Status Page */
217 if (!ring->status_page.page_addr) {
218 DRM_ERROR("Can not find hardware status page\n");
219 return -EINVAL;
220 }
221 DRM_DEBUG_DRIVER("hw status page @ %p\n",
222 ring->status_page.page_addr);
223 if (ring->status_page.gfx_addr != 0)
224 ring->setup_status_page(dev, ring);
225 else
226 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
227
228 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
229
230 return 0;
231 }
232
233 static int i915_dma_init(struct drm_device *dev, void *data,
234 struct drm_file *file_priv)
235 {
236 drm_i915_init_t *init = data;
237 int retcode = 0;
238
239 switch (init->func) {
240 case I915_INIT_DMA:
241 retcode = i915_initialize(dev, init);
242 break;
243 case I915_CLEANUP_DMA:
244 retcode = i915_dma_cleanup(dev);
245 break;
246 case I915_RESUME_DMA:
247 retcode = i915_dma_resume(dev);
248 break;
249 default:
250 retcode = -EINVAL;
251 break;
252 }
253
254 return retcode;
255 }
256
257 /* Implement basically the same security restrictions as hardware does
258 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
259 *
260 * Most of the calculations below involve calculating the size of a
261 * particular instruction. It's important to get the size right as
262 * that tells us where the next instruction to check is. Any illegal
263 * instruction detected will be given a size of zero, which is a
264 * signal to abort the rest of the buffer.
265 */
266 static int do_validate_cmd(int cmd)
267 {
268 switch (((cmd >> 29) & 0x7)) {
269 case 0x0:
270 switch ((cmd >> 23) & 0x3f) {
271 case 0x0:
272 return 1; /* MI_NOOP */
273 case 0x4:
274 return 1; /* MI_FLUSH */
275 default:
276 return 0; /* disallow everything else */
277 }
278 break;
279 case 0x1:
280 return 0; /* reserved */
281 case 0x2:
282 return (cmd & 0xff) + 2; /* 2d commands */
283 case 0x3:
284 if (((cmd >> 24) & 0x1f) <= 0x18)
285 return 1;
286
287 switch ((cmd >> 24) & 0x1f) {
288 case 0x1c:
289 return 1;
290 case 0x1d:
291 switch ((cmd >> 16) & 0xff) {
292 case 0x3:
293 return (cmd & 0x1f) + 2;
294 case 0x4:
295 return (cmd & 0xf) + 2;
296 default:
297 return (cmd & 0xffff) + 2;
298 }
299 case 0x1e:
300 if (cmd & (1 << 23))
301 return (cmd & 0xffff) + 1;
302 else
303 return 1;
304 case 0x1f:
305 if ((cmd & (1 << 23)) == 0) /* inline vertices */
306 return (cmd & 0x1ffff) + 2;
307 else if (cmd & (1 << 17)) /* indirect random */
308 if ((cmd & 0xffff) == 0)
309 return 0; /* unknown length, too hard */
310 else
311 return (((cmd & 0xffff) + 1) / 2) + 1;
312 else
313 return 2; /* indirect sequential */
314 default:
315 return 0;
316 }
317 default:
318 return 0;
319 }
320
321 return 0;
322 }
323
324 static int validate_cmd(int cmd)
325 {
326 int ret = do_validate_cmd(cmd);
327
328 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
329
330 return ret;
331 }
332
333 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
334 {
335 drm_i915_private_t *dev_priv = dev->dev_private;
336 int i;
337
338 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
339 return -EINVAL;
340
341 BEGIN_LP_RING((dwords+1)&~1);
342
343 for (i = 0; i < dwords;) {
344 int cmd, sz;
345
346 cmd = buffer[i];
347
348 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
349 return -EINVAL;
350
351 OUT_RING(cmd);
352
353 while (++i, --sz) {
354 OUT_RING(buffer[i]);
355 }
356 }
357
358 if (dwords & 1)
359 OUT_RING(0);
360
361 ADVANCE_LP_RING();
362
363 return 0;
364 }
365
366 int
367 i915_emit_box(struct drm_device *dev,
368 struct drm_clip_rect *boxes,
369 int i, int DR1, int DR4)
370 {
371 struct drm_clip_rect box = boxes[i];
372
373 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
374 DRM_ERROR("Bad box %d,%d..%d,%d\n",
375 box.x1, box.y1, box.x2, box.y2);
376 return -EINVAL;
377 }
378
379 if (IS_I965G(dev)) {
380 BEGIN_LP_RING(4);
381 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
382 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
383 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
384 OUT_RING(DR4);
385 ADVANCE_LP_RING();
386 } else {
387 BEGIN_LP_RING(6);
388 OUT_RING(GFX_OP_DRAWRECT_INFO);
389 OUT_RING(DR1);
390 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
391 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
392 OUT_RING(DR4);
393 OUT_RING(0);
394 ADVANCE_LP_RING();
395 }
396
397 return 0;
398 }
399
400 /* XXX: Emitting the counter should really be moved to part of the IRQ
401 * emit. For now, do it in both places:
402 */
403
404 static void i915_emit_breadcrumb(struct drm_device *dev)
405 {
406 drm_i915_private_t *dev_priv = dev->dev_private;
407 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
408
409 dev_priv->counter++;
410 if (dev_priv->counter > 0x7FFFFFFFUL)
411 dev_priv->counter = 0;
412 if (master_priv->sarea_priv)
413 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
414
415 BEGIN_LP_RING(4);
416 OUT_RING(MI_STORE_DWORD_INDEX);
417 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
418 OUT_RING(dev_priv->counter);
419 OUT_RING(0);
420 ADVANCE_LP_RING();
421 }
422
423 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
424 drm_i915_cmdbuffer_t *cmd,
425 struct drm_clip_rect *cliprects,
426 void *cmdbuf)
427 {
428 int nbox = cmd->num_cliprects;
429 int i = 0, count, ret;
430
431 if (cmd->sz & 0x3) {
432 DRM_ERROR("alignment");
433 return -EINVAL;
434 }
435
436 i915_kernel_lost_context(dev);
437
438 count = nbox ? nbox : 1;
439
440 for (i = 0; i < count; i++) {
441 if (i < nbox) {
442 ret = i915_emit_box(dev, cliprects, i,
443 cmd->DR1, cmd->DR4);
444 if (ret)
445 return ret;
446 }
447
448 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
449 if (ret)
450 return ret;
451 }
452
453 i915_emit_breadcrumb(dev);
454 return 0;
455 }
456
457 static int i915_dispatch_batchbuffer(struct drm_device * dev,
458 drm_i915_batchbuffer_t * batch,
459 struct drm_clip_rect *cliprects)
460 {
461 int nbox = batch->num_cliprects;
462 int i = 0, count;
463
464 if ((batch->start | batch->used) & 0x7) {
465 DRM_ERROR("alignment");
466 return -EINVAL;
467 }
468
469 i915_kernel_lost_context(dev);
470
471 count = nbox ? nbox : 1;
472
473 for (i = 0; i < count; i++) {
474 if (i < nbox) {
475 int ret = i915_emit_box(dev, cliprects, i,
476 batch->DR1, batch->DR4);
477 if (ret)
478 return ret;
479 }
480
481 if (!IS_I830(dev) && !IS_845G(dev)) {
482 BEGIN_LP_RING(2);
483 if (IS_I965G(dev)) {
484 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
485 OUT_RING(batch->start);
486 } else {
487 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
488 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
489 }
490 ADVANCE_LP_RING();
491 } else {
492 BEGIN_LP_RING(4);
493 OUT_RING(MI_BATCH_BUFFER);
494 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
495 OUT_RING(batch->start + batch->used - 4);
496 OUT_RING(0);
497 ADVANCE_LP_RING();
498 }
499 }
500
501
502 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
503 BEGIN_LP_RING(2);
504 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
505 OUT_RING(MI_NOOP);
506 ADVANCE_LP_RING();
507 }
508 i915_emit_breadcrumb(dev);
509
510 return 0;
511 }
512
513 static int i915_dispatch_flip(struct drm_device * dev)
514 {
515 drm_i915_private_t *dev_priv = dev->dev_private;
516 struct drm_i915_master_private *master_priv =
517 dev->primary->master->driver_priv;
518
519 if (!master_priv->sarea_priv)
520 return -EINVAL;
521
522 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
523 __func__,
524 dev_priv->current_page,
525 master_priv->sarea_priv->pf_current_page);
526
527 i915_kernel_lost_context(dev);
528
529 BEGIN_LP_RING(2);
530 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
531 OUT_RING(0);
532 ADVANCE_LP_RING();
533
534 BEGIN_LP_RING(6);
535 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
536 OUT_RING(0);
537 if (dev_priv->current_page == 0) {
538 OUT_RING(dev_priv->back_offset);
539 dev_priv->current_page = 1;
540 } else {
541 OUT_RING(dev_priv->front_offset);
542 dev_priv->current_page = 0;
543 }
544 OUT_RING(0);
545 ADVANCE_LP_RING();
546
547 BEGIN_LP_RING(2);
548 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
549 OUT_RING(0);
550 ADVANCE_LP_RING();
551
552 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
553
554 BEGIN_LP_RING(4);
555 OUT_RING(MI_STORE_DWORD_INDEX);
556 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
557 OUT_RING(dev_priv->counter);
558 OUT_RING(0);
559 ADVANCE_LP_RING();
560
561 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
562 return 0;
563 }
564
565 static int i915_quiescent(struct drm_device * dev)
566 {
567 drm_i915_private_t *dev_priv = dev->dev_private;
568
569 i915_kernel_lost_context(dev);
570 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
571 dev_priv->render_ring.size - 8);
572 }
573
574 static int i915_flush_ioctl(struct drm_device *dev, void *data,
575 struct drm_file *file_priv)
576 {
577 int ret;
578
579 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
580
581 mutex_lock(&dev->struct_mutex);
582 ret = i915_quiescent(dev);
583 mutex_unlock(&dev->struct_mutex);
584
585 return ret;
586 }
587
588 static int i915_batchbuffer(struct drm_device *dev, void *data,
589 struct drm_file *file_priv)
590 {
591 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
592 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
593 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
594 master_priv->sarea_priv;
595 drm_i915_batchbuffer_t *batch = data;
596 int ret;
597 struct drm_clip_rect *cliprects = NULL;
598
599 if (!dev_priv->allow_batchbuffer) {
600 DRM_ERROR("Batchbuffer ioctl disabled\n");
601 return -EINVAL;
602 }
603
604 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
605 batch->start, batch->used, batch->num_cliprects);
606
607 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
608
609 if (batch->num_cliprects < 0)
610 return -EINVAL;
611
612 if (batch->num_cliprects) {
613 cliprects = kcalloc(batch->num_cliprects,
614 sizeof(struct drm_clip_rect),
615 GFP_KERNEL);
616 if (cliprects == NULL)
617 return -ENOMEM;
618
619 ret = copy_from_user(cliprects, batch->cliprects,
620 batch->num_cliprects *
621 sizeof(struct drm_clip_rect));
622 if (ret != 0) {
623 ret = -EFAULT;
624 goto fail_free;
625 }
626 }
627
628 mutex_lock(&dev->struct_mutex);
629 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
630 mutex_unlock(&dev->struct_mutex);
631
632 if (sarea_priv)
633 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
634
635 fail_free:
636 kfree(cliprects);
637
638 return ret;
639 }
640
641 static int i915_cmdbuffer(struct drm_device *dev, void *data,
642 struct drm_file *file_priv)
643 {
644 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
645 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
646 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
647 master_priv->sarea_priv;
648 drm_i915_cmdbuffer_t *cmdbuf = data;
649 struct drm_clip_rect *cliprects = NULL;
650 void *batch_data;
651 int ret;
652
653 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
654 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
655
656 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
657
658 if (cmdbuf->num_cliprects < 0)
659 return -EINVAL;
660
661 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
662 if (batch_data == NULL)
663 return -ENOMEM;
664
665 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
666 if (ret != 0) {
667 ret = -EFAULT;
668 goto fail_batch_free;
669 }
670
671 if (cmdbuf->num_cliprects) {
672 cliprects = kcalloc(cmdbuf->num_cliprects,
673 sizeof(struct drm_clip_rect), GFP_KERNEL);
674 if (cliprects == NULL) {
675 ret = -ENOMEM;
676 goto fail_batch_free;
677 }
678
679 ret = copy_from_user(cliprects, cmdbuf->cliprects,
680 cmdbuf->num_cliprects *
681 sizeof(struct drm_clip_rect));
682 if (ret != 0) {
683 ret = -EFAULT;
684 goto fail_clip_free;
685 }
686 }
687
688 mutex_lock(&dev->struct_mutex);
689 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
690 mutex_unlock(&dev->struct_mutex);
691 if (ret) {
692 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
693 goto fail_clip_free;
694 }
695
696 if (sarea_priv)
697 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
698
699 fail_clip_free:
700 kfree(cliprects);
701 fail_batch_free:
702 kfree(batch_data);
703
704 return ret;
705 }
706
707 static int i915_flip_bufs(struct drm_device *dev, void *data,
708 struct drm_file *file_priv)
709 {
710 int ret;
711
712 DRM_DEBUG_DRIVER("%s\n", __func__);
713
714 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
715
716 mutex_lock(&dev->struct_mutex);
717 ret = i915_dispatch_flip(dev);
718 mutex_unlock(&dev->struct_mutex);
719
720 return ret;
721 }
722
723 static int i915_getparam(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
725 {
726 drm_i915_private_t *dev_priv = dev->dev_private;
727 drm_i915_getparam_t *param = data;
728 int value;
729
730 if (!dev_priv) {
731 DRM_ERROR("called with no initialization\n");
732 return -EINVAL;
733 }
734
735 switch (param->param) {
736 case I915_PARAM_IRQ_ACTIVE:
737 value = dev->pdev->irq ? 1 : 0;
738 break;
739 case I915_PARAM_ALLOW_BATCHBUFFER:
740 value = dev_priv->allow_batchbuffer ? 1 : 0;
741 break;
742 case I915_PARAM_LAST_DISPATCH:
743 value = READ_BREADCRUMB(dev_priv);
744 break;
745 case I915_PARAM_CHIPSET_ID:
746 value = dev->pci_device;
747 break;
748 case I915_PARAM_HAS_GEM:
749 value = dev_priv->has_gem;
750 break;
751 case I915_PARAM_NUM_FENCES_AVAIL:
752 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
753 break;
754 case I915_PARAM_HAS_OVERLAY:
755 value = dev_priv->overlay ? 1 : 0;
756 break;
757 case I915_PARAM_HAS_PAGEFLIPPING:
758 value = 1;
759 break;
760 case I915_PARAM_HAS_EXECBUF2:
761 /* depends on GEM */
762 value = dev_priv->has_gem;
763 break;
764 case I915_PARAM_HAS_BSD:
765 value = HAS_BSD(dev);
766 break;
767 default:
768 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
769 param->param);
770 return -EINVAL;
771 }
772
773 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
774 DRM_ERROR("DRM_COPY_TO_USER failed\n");
775 return -EFAULT;
776 }
777
778 return 0;
779 }
780
781 static int i915_setparam(struct drm_device *dev, void *data,
782 struct drm_file *file_priv)
783 {
784 drm_i915_private_t *dev_priv = dev->dev_private;
785 drm_i915_setparam_t *param = data;
786
787 if (!dev_priv) {
788 DRM_ERROR("called with no initialization\n");
789 return -EINVAL;
790 }
791
792 switch (param->param) {
793 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
794 break;
795 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
796 dev_priv->tex_lru_log_granularity = param->value;
797 break;
798 case I915_SETPARAM_ALLOW_BATCHBUFFER:
799 dev_priv->allow_batchbuffer = param->value;
800 break;
801 case I915_SETPARAM_NUM_USED_FENCES:
802 if (param->value > dev_priv->num_fence_regs ||
803 param->value < 0)
804 return -EINVAL;
805 /* Userspace can use first N regs */
806 dev_priv->fence_reg_start = param->value;
807 break;
808 default:
809 DRM_DEBUG_DRIVER("unknown parameter %d\n",
810 param->param);
811 return -EINVAL;
812 }
813
814 return 0;
815 }
816
817 static int i915_set_status_page(struct drm_device *dev, void *data,
818 struct drm_file *file_priv)
819 {
820 drm_i915_private_t *dev_priv = dev->dev_private;
821 drm_i915_hws_addr_t *hws = data;
822 struct intel_ring_buffer *ring = &dev_priv->render_ring;
823
824 if (!I915_NEED_GFX_HWS(dev))
825 return -EINVAL;
826
827 if (!dev_priv) {
828 DRM_ERROR("called with no initialization\n");
829 return -EINVAL;
830 }
831
832 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
833 WARN(1, "tried to set status page when mode setting active\n");
834 return 0;
835 }
836
837 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
838
839 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
840
841 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
842 dev_priv->hws_map.size = 4*1024;
843 dev_priv->hws_map.type = 0;
844 dev_priv->hws_map.flags = 0;
845 dev_priv->hws_map.mtrr = 0;
846
847 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
848 if (dev_priv->hws_map.handle == NULL) {
849 i915_dma_cleanup(dev);
850 ring->status_page.gfx_addr = 0;
851 DRM_ERROR("can not ioremap virtual address for"
852 " G33 hw status page\n");
853 return -ENOMEM;
854 }
855 ring->status_page.page_addr = dev_priv->hws_map.handle;
856 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
857 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
858
859 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
860 ring->status_page.gfx_addr);
861 DRM_DEBUG_DRIVER("load hws at %p\n",
862 ring->status_page.page_addr);
863 return 0;
864 }
865
866 static int i915_get_bridge_dev(struct drm_device *dev)
867 {
868 struct drm_i915_private *dev_priv = dev->dev_private;
869
870 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
871 if (!dev_priv->bridge_dev) {
872 DRM_ERROR("bridge device not found\n");
873 return -1;
874 }
875 return 0;
876 }
877
878 #define MCHBAR_I915 0x44
879 #define MCHBAR_I965 0x48
880 #define MCHBAR_SIZE (4*4096)
881
882 #define DEVEN_REG 0x54
883 #define DEVEN_MCHBAR_EN (1 << 28)
884
885 /* Allocate space for the MCH regs if needed, return nonzero on error */
886 static int
887 intel_alloc_mchbar_resource(struct drm_device *dev)
888 {
889 drm_i915_private_t *dev_priv = dev->dev_private;
890 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
891 u32 temp_lo, temp_hi = 0;
892 u64 mchbar_addr;
893 int ret;
894
895 if (IS_I965G(dev))
896 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
897 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
898 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
899
900 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
901 #ifdef CONFIG_PNP
902 if (mchbar_addr &&
903 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
904 return 0;
905 #endif
906
907 /* Get some space for it */
908 dev_priv->mch_res.name = "i915 MCHBAR";
909 dev_priv->mch_res.flags = IORESOURCE_MEM;
910 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
911 &dev_priv->mch_res,
912 MCHBAR_SIZE, MCHBAR_SIZE,
913 PCIBIOS_MIN_MEM,
914 0, pcibios_align_resource,
915 dev_priv->bridge_dev);
916 if (ret) {
917 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
918 dev_priv->mch_res.start = 0;
919 return ret;
920 }
921
922 if (IS_I965G(dev))
923 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
924 upper_32_bits(dev_priv->mch_res.start));
925
926 pci_write_config_dword(dev_priv->bridge_dev, reg,
927 lower_32_bits(dev_priv->mch_res.start));
928 return 0;
929 }
930
931 /* Setup MCHBAR if possible, return true if we should disable it again */
932 static void
933 intel_setup_mchbar(struct drm_device *dev)
934 {
935 drm_i915_private_t *dev_priv = dev->dev_private;
936 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
937 u32 temp;
938 bool enabled;
939
940 dev_priv->mchbar_need_disable = false;
941
942 if (IS_I915G(dev) || IS_I915GM(dev)) {
943 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
944 enabled = !!(temp & DEVEN_MCHBAR_EN);
945 } else {
946 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
947 enabled = temp & 1;
948 }
949
950 /* If it's already enabled, don't have to do anything */
951 if (enabled)
952 return;
953
954 if (intel_alloc_mchbar_resource(dev))
955 return;
956
957 dev_priv->mchbar_need_disable = true;
958
959 /* Space is allocated or reserved, so enable it. */
960 if (IS_I915G(dev) || IS_I915GM(dev)) {
961 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
962 temp | DEVEN_MCHBAR_EN);
963 } else {
964 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
965 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
966 }
967 }
968
969 static void
970 intel_teardown_mchbar(struct drm_device *dev)
971 {
972 drm_i915_private_t *dev_priv = dev->dev_private;
973 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
974 u32 temp;
975
976 if (dev_priv->mchbar_need_disable) {
977 if (IS_I915G(dev) || IS_I915GM(dev)) {
978 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
979 temp &= ~DEVEN_MCHBAR_EN;
980 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
981 } else {
982 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
983 temp &= ~1;
984 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
985 }
986 }
987
988 if (dev_priv->mch_res.start)
989 release_resource(&dev_priv->mch_res);
990 }
991
992 /**
993 * i915_probe_agp - get AGP bootup configuration
994 * @pdev: PCI device
995 * @aperture_size: returns AGP aperture configured size
996 * @preallocated_size: returns size of BIOS preallocated AGP space
997 *
998 * Since Intel integrated graphics are UMA, the BIOS has to set aside
999 * some RAM for the framebuffer at early boot. This code figures out
1000 * how much was set aside so we can use it for our own purposes.
1001 */
1002 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1003 uint32_t *preallocated_size,
1004 uint32_t *start)
1005 {
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1007 u16 tmp = 0;
1008 unsigned long overhead;
1009 unsigned long stolen;
1010
1011 /* Get the fb aperture size and "stolen" memory amount. */
1012 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1013
1014 *aperture_size = 1024 * 1024;
1015 *preallocated_size = 1024 * 1024;
1016
1017 switch (dev->pdev->device) {
1018 case PCI_DEVICE_ID_INTEL_82830_CGC:
1019 case PCI_DEVICE_ID_INTEL_82845G_IG:
1020 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1021 case PCI_DEVICE_ID_INTEL_82865_IG:
1022 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1023 *aperture_size *= 64;
1024 else
1025 *aperture_size *= 128;
1026 break;
1027 default:
1028 /* 9xx supports large sizes, just look at the length */
1029 *aperture_size = pci_resource_len(dev->pdev, 2);
1030 break;
1031 }
1032
1033 /*
1034 * Some of the preallocated space is taken by the GTT
1035 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1036 */
1037 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1038 overhead = 4096;
1039 else
1040 overhead = (*aperture_size / 1024) + 4096;
1041
1042 if (IS_GEN6(dev)) {
1043 /* SNB has memory control reg at 0x50.w */
1044 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1045
1046 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1047 case INTEL_855_GMCH_GMS_DISABLED:
1048 DRM_ERROR("video memory is disabled\n");
1049 return -1;
1050 case SNB_GMCH_GMS_STOLEN_32M:
1051 stolen = 32 * 1024 * 1024;
1052 break;
1053 case SNB_GMCH_GMS_STOLEN_64M:
1054 stolen = 64 * 1024 * 1024;
1055 break;
1056 case SNB_GMCH_GMS_STOLEN_96M:
1057 stolen = 96 * 1024 * 1024;
1058 break;
1059 case SNB_GMCH_GMS_STOLEN_128M:
1060 stolen = 128 * 1024 * 1024;
1061 break;
1062 case SNB_GMCH_GMS_STOLEN_160M:
1063 stolen = 160 * 1024 * 1024;
1064 break;
1065 case SNB_GMCH_GMS_STOLEN_192M:
1066 stolen = 192 * 1024 * 1024;
1067 break;
1068 case SNB_GMCH_GMS_STOLEN_224M:
1069 stolen = 224 * 1024 * 1024;
1070 break;
1071 case SNB_GMCH_GMS_STOLEN_256M:
1072 stolen = 256 * 1024 * 1024;
1073 break;
1074 case SNB_GMCH_GMS_STOLEN_288M:
1075 stolen = 288 * 1024 * 1024;
1076 break;
1077 case SNB_GMCH_GMS_STOLEN_320M:
1078 stolen = 320 * 1024 * 1024;
1079 break;
1080 case SNB_GMCH_GMS_STOLEN_352M:
1081 stolen = 352 * 1024 * 1024;
1082 break;
1083 case SNB_GMCH_GMS_STOLEN_384M:
1084 stolen = 384 * 1024 * 1024;
1085 break;
1086 case SNB_GMCH_GMS_STOLEN_416M:
1087 stolen = 416 * 1024 * 1024;
1088 break;
1089 case SNB_GMCH_GMS_STOLEN_448M:
1090 stolen = 448 * 1024 * 1024;
1091 break;
1092 case SNB_GMCH_GMS_STOLEN_480M:
1093 stolen = 480 * 1024 * 1024;
1094 break;
1095 case SNB_GMCH_GMS_STOLEN_512M:
1096 stolen = 512 * 1024 * 1024;
1097 break;
1098 default:
1099 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1100 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1101 return -1;
1102 }
1103 } else {
1104 switch (tmp & INTEL_GMCH_GMS_MASK) {
1105 case INTEL_855_GMCH_GMS_DISABLED:
1106 DRM_ERROR("video memory is disabled\n");
1107 return -1;
1108 case INTEL_855_GMCH_GMS_STOLEN_1M:
1109 stolen = 1 * 1024 * 1024;
1110 break;
1111 case INTEL_855_GMCH_GMS_STOLEN_4M:
1112 stolen = 4 * 1024 * 1024;
1113 break;
1114 case INTEL_855_GMCH_GMS_STOLEN_8M:
1115 stolen = 8 * 1024 * 1024;
1116 break;
1117 case INTEL_855_GMCH_GMS_STOLEN_16M:
1118 stolen = 16 * 1024 * 1024;
1119 break;
1120 case INTEL_855_GMCH_GMS_STOLEN_32M:
1121 stolen = 32 * 1024 * 1024;
1122 break;
1123 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1124 stolen = 48 * 1024 * 1024;
1125 break;
1126 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1127 stolen = 64 * 1024 * 1024;
1128 break;
1129 case INTEL_GMCH_GMS_STOLEN_128M:
1130 stolen = 128 * 1024 * 1024;
1131 break;
1132 case INTEL_GMCH_GMS_STOLEN_256M:
1133 stolen = 256 * 1024 * 1024;
1134 break;
1135 case INTEL_GMCH_GMS_STOLEN_96M:
1136 stolen = 96 * 1024 * 1024;
1137 break;
1138 case INTEL_GMCH_GMS_STOLEN_160M:
1139 stolen = 160 * 1024 * 1024;
1140 break;
1141 case INTEL_GMCH_GMS_STOLEN_224M:
1142 stolen = 224 * 1024 * 1024;
1143 break;
1144 case INTEL_GMCH_GMS_STOLEN_352M:
1145 stolen = 352 * 1024 * 1024;
1146 break;
1147 default:
1148 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1149 tmp & INTEL_GMCH_GMS_MASK);
1150 return -1;
1151 }
1152 }
1153
1154 *preallocated_size = stolen - overhead;
1155 *start = overhead;
1156
1157 return 0;
1158 }
1159
1160 #define PTE_ADDRESS_MASK 0xfffff000
1161 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1162 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1163 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1164 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1165 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1166 #define PTE_VALID (1 << 0)
1167
1168 /**
1169 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1170 * @dev: drm device
1171 * @gtt_addr: address to translate
1172 *
1173 * Some chip functions require allocations from stolen space but need the
1174 * physical address of the memory in question. We use this routine
1175 * to get a physical address suitable for register programming from a given
1176 * GTT address.
1177 */
1178 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1179 unsigned long gtt_addr)
1180 {
1181 unsigned long *gtt;
1182 unsigned long entry, phys;
1183 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1184 int gtt_offset, gtt_size;
1185
1186 if (IS_I965G(dev)) {
1187 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1188 gtt_offset = 2*1024*1024;
1189 gtt_size = 2*1024*1024;
1190 } else {
1191 gtt_offset = 512*1024;
1192 gtt_size = 512*1024;
1193 }
1194 } else {
1195 gtt_bar = 3;
1196 gtt_offset = 0;
1197 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1198 }
1199
1200 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1201 gtt_size);
1202 if (!gtt) {
1203 DRM_ERROR("ioremap of GTT failed\n");
1204 return 0;
1205 }
1206
1207 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1208
1209 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1210
1211 /* Mask out these reserved bits on this hardware. */
1212 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1213 IS_I945G(dev) || IS_I945GM(dev)) {
1214 entry &= ~PTE_ADDRESS_MASK_HIGH;
1215 }
1216
1217 /* If it's not a mapping type we know, then bail. */
1218 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1219 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1220 iounmap(gtt);
1221 return 0;
1222 }
1223
1224 if (!(entry & PTE_VALID)) {
1225 DRM_ERROR("bad GTT entry in stolen space\n");
1226 iounmap(gtt);
1227 return 0;
1228 }
1229
1230 iounmap(gtt);
1231
1232 phys =(entry & PTE_ADDRESS_MASK) |
1233 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1234
1235 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1236
1237 return phys;
1238 }
1239
1240 static void i915_warn_stolen(struct drm_device *dev)
1241 {
1242 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1243 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1244 }
1245
1246 static void i915_setup_compression(struct drm_device *dev, int size)
1247 {
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1250 unsigned long cfb_base;
1251 unsigned long ll_base = 0;
1252
1253 /* Leave 1M for line length buffer & misc. */
1254 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1255 if (!compressed_fb) {
1256 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1257 i915_warn_stolen(dev);
1258 return;
1259 }
1260
1261 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1262 if (!compressed_fb) {
1263 i915_warn_stolen(dev);
1264 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1265 return;
1266 }
1267
1268 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1269 if (!cfb_base) {
1270 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1271 drm_mm_put_block(compressed_fb);
1272 }
1273
1274 if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1275 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1276 4096, 0);
1277 if (!compressed_llb) {
1278 i915_warn_stolen(dev);
1279 return;
1280 }
1281
1282 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1283 if (!compressed_llb) {
1284 i915_warn_stolen(dev);
1285 return;
1286 }
1287
1288 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1289 if (!ll_base) {
1290 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1291 drm_mm_put_block(compressed_fb);
1292 drm_mm_put_block(compressed_llb);
1293 }
1294 }
1295
1296 dev_priv->cfb_size = size;
1297
1298 intel_disable_fbc(dev);
1299 dev_priv->compressed_fb = compressed_fb;
1300 if (IS_IRONLAKE_M(dev))
1301 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1302 else if (IS_GM45(dev)) {
1303 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1304 } else {
1305 I915_WRITE(FBC_CFB_BASE, cfb_base);
1306 I915_WRITE(FBC_LL_BASE, ll_base);
1307 dev_priv->compressed_llb = compressed_llb;
1308 }
1309
1310 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1311 ll_base, size >> 20);
1312 }
1313
1314 static void i915_cleanup_compression(struct drm_device *dev)
1315 {
1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317
1318 drm_mm_put_block(dev_priv->compressed_fb);
1319 if (dev_priv->compressed_llb)
1320 drm_mm_put_block(dev_priv->compressed_llb);
1321 }
1322
1323 /* true = enable decode, false = disable decoder */
1324 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1325 {
1326 struct drm_device *dev = cookie;
1327
1328 intel_modeset_vga_set_state(dev, state);
1329 if (state)
1330 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1331 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1332 else
1333 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1334 }
1335
1336 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1337 {
1338 struct drm_device *dev = pci_get_drvdata(pdev);
1339 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1340 if (state == VGA_SWITCHEROO_ON) {
1341 printk(KERN_INFO "i915: switched on\n");
1342 /* i915 resume handler doesn't set to D0 */
1343 pci_set_power_state(dev->pdev, PCI_D0);
1344 i915_resume(dev);
1345 drm_kms_helper_poll_enable(dev);
1346 } else {
1347 printk(KERN_ERR "i915: switched off\n");
1348 drm_kms_helper_poll_disable(dev);
1349 i915_suspend(dev, pmm);
1350 }
1351 }
1352
1353 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1354 {
1355 struct drm_device *dev = pci_get_drvdata(pdev);
1356 bool can_switch;
1357
1358 spin_lock(&dev->count_lock);
1359 can_switch = (dev->open_count == 0);
1360 spin_unlock(&dev->count_lock);
1361 return can_switch;
1362 }
1363
1364 static int i915_load_modeset_init(struct drm_device *dev,
1365 unsigned long prealloc_start,
1366 unsigned long prealloc_size,
1367 unsigned long agp_size)
1368 {
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int ret = 0;
1371
1372 /* Basic memrange allocator for stolen space (aka vram) */
1373 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1374 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1375
1376 /* We're off and running w/KMS */
1377 dev_priv->mm.suspended = 0;
1378
1379 /* Let GEM Manage from end of prealloc space to end of aperture.
1380 *
1381 * However, leave one page at the end still bound to the scratch page.
1382 * There are a number of places where the hardware apparently
1383 * prefetches past the end of the object, and we've seen multiple
1384 * hangs with the GPU head pointer stuck in a batchbuffer bound
1385 * at the last page of the aperture. One page should be enough to
1386 * keep any prefetching inside of the aperture.
1387 */
1388 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1389
1390 mutex_lock(&dev->struct_mutex);
1391 ret = i915_gem_init_ringbuffer(dev);
1392 mutex_unlock(&dev->struct_mutex);
1393 if (ret)
1394 goto out;
1395
1396 /* Try to set up FBC with a reasonable compressed buffer size */
1397 if (I915_HAS_FBC(dev) && i915_powersave) {
1398 int cfb_size;
1399
1400 /* Try to get an 8M buffer... */
1401 if (prealloc_size > (9*1024*1024))
1402 cfb_size = 8*1024*1024;
1403 else /* fall back to 7/8 of the stolen space */
1404 cfb_size = prealloc_size * 7 / 8;
1405 i915_setup_compression(dev, cfb_size);
1406 }
1407
1408 /* Allow hardware batchbuffers unless told otherwise.
1409 */
1410 dev_priv->allow_batchbuffer = 1;
1411
1412 ret = intel_init_bios(dev);
1413 if (ret)
1414 DRM_INFO("failed to find VBIOS tables\n");
1415
1416 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1417 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1418 if (ret)
1419 goto cleanup_ringbuffer;
1420
1421 ret = vga_switcheroo_register_client(dev->pdev,
1422 i915_switcheroo_set_state,
1423 i915_switcheroo_can_switch);
1424 if (ret)
1425 goto cleanup_vga_client;
1426
1427 /* IIR "flip pending" bit means done if this bit is set */
1428 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1429 dev_priv->flip_pending_is_done = true;
1430
1431 intel_modeset_init(dev);
1432
1433 ret = drm_irq_install(dev);
1434 if (ret)
1435 goto cleanup_vga_switcheroo;
1436
1437 /* Always safe in the mode setting case. */
1438 /* FIXME: do pre/post-mode set stuff in core KMS code */
1439 dev->vblank_disable_allowed = 1;
1440
1441 ret = intel_fbdev_init(dev);
1442 if (ret)
1443 goto cleanup_irq;
1444
1445 drm_kms_helper_poll_init(dev);
1446 return 0;
1447
1448 cleanup_irq:
1449 drm_irq_uninstall(dev);
1450 cleanup_vga_switcheroo:
1451 vga_switcheroo_unregister_client(dev->pdev);
1452 cleanup_vga_client:
1453 vga_client_register(dev->pdev, NULL, NULL, NULL);
1454 cleanup_ringbuffer:
1455 mutex_lock(&dev->struct_mutex);
1456 i915_gem_cleanup_ringbuffer(dev);
1457 mutex_unlock(&dev->struct_mutex);
1458 out:
1459 return ret;
1460 }
1461
1462 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1463 {
1464 struct drm_i915_master_private *master_priv;
1465
1466 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1467 if (!master_priv)
1468 return -ENOMEM;
1469
1470 master->driver_priv = master_priv;
1471 return 0;
1472 }
1473
1474 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1475 {
1476 struct drm_i915_master_private *master_priv = master->driver_priv;
1477
1478 if (!master_priv)
1479 return;
1480
1481 kfree(master_priv);
1482
1483 master->driver_priv = NULL;
1484 }
1485
1486 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1487 {
1488 drm_i915_private_t *dev_priv = dev->dev_private;
1489 u32 tmp;
1490
1491 tmp = I915_READ(CLKCFG);
1492
1493 switch (tmp & CLKCFG_FSB_MASK) {
1494 case CLKCFG_FSB_533:
1495 dev_priv->fsb_freq = 533; /* 133*4 */
1496 break;
1497 case CLKCFG_FSB_800:
1498 dev_priv->fsb_freq = 800; /* 200*4 */
1499 break;
1500 case CLKCFG_FSB_667:
1501 dev_priv->fsb_freq = 667; /* 167*4 */
1502 break;
1503 case CLKCFG_FSB_400:
1504 dev_priv->fsb_freq = 400; /* 100*4 */
1505 break;
1506 }
1507
1508 switch (tmp & CLKCFG_MEM_MASK) {
1509 case CLKCFG_MEM_533:
1510 dev_priv->mem_freq = 533;
1511 break;
1512 case CLKCFG_MEM_667:
1513 dev_priv->mem_freq = 667;
1514 break;
1515 case CLKCFG_MEM_800:
1516 dev_priv->mem_freq = 800;
1517 break;
1518 }
1519
1520 /* detect pineview DDR3 setting */
1521 tmp = I915_READ(CSHRDDR3CTL);
1522 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1523 }
1524
1525 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1526 {
1527 drm_i915_private_t *dev_priv = dev->dev_private;
1528 u16 ddrpll, csipll;
1529
1530 ddrpll = I915_READ16(DDRMPLL1);
1531 csipll = I915_READ16(CSIPLL0);
1532
1533 switch (ddrpll & 0xff) {
1534 case 0xc:
1535 dev_priv->mem_freq = 800;
1536 break;
1537 case 0x10:
1538 dev_priv->mem_freq = 1066;
1539 break;
1540 case 0x14:
1541 dev_priv->mem_freq = 1333;
1542 break;
1543 case 0x18:
1544 dev_priv->mem_freq = 1600;
1545 break;
1546 default:
1547 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1548 ddrpll & 0xff);
1549 dev_priv->mem_freq = 0;
1550 break;
1551 }
1552
1553 dev_priv->r_t = dev_priv->mem_freq;
1554
1555 switch (csipll & 0x3ff) {
1556 case 0x00c:
1557 dev_priv->fsb_freq = 3200;
1558 break;
1559 case 0x00e:
1560 dev_priv->fsb_freq = 3733;
1561 break;
1562 case 0x010:
1563 dev_priv->fsb_freq = 4266;
1564 break;
1565 case 0x012:
1566 dev_priv->fsb_freq = 4800;
1567 break;
1568 case 0x014:
1569 dev_priv->fsb_freq = 5333;
1570 break;
1571 case 0x016:
1572 dev_priv->fsb_freq = 5866;
1573 break;
1574 case 0x018:
1575 dev_priv->fsb_freq = 6400;
1576 break;
1577 default:
1578 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1579 csipll & 0x3ff);
1580 dev_priv->fsb_freq = 0;
1581 break;
1582 }
1583
1584 if (dev_priv->fsb_freq == 3200) {
1585 dev_priv->c_m = 0;
1586 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1587 dev_priv->c_m = 1;
1588 } else {
1589 dev_priv->c_m = 2;
1590 }
1591 }
1592
1593 struct v_table {
1594 u8 vid;
1595 unsigned long vd; /* in .1 mil */
1596 unsigned long vm; /* in .1 mil */
1597 u8 pvid;
1598 };
1599
1600 static struct v_table v_table[] = {
1601 { 0, 16125, 15000, 0x7f, },
1602 { 1, 16000, 14875, 0x7e, },
1603 { 2, 15875, 14750, 0x7d, },
1604 { 3, 15750, 14625, 0x7c, },
1605 { 4, 15625, 14500, 0x7b, },
1606 { 5, 15500, 14375, 0x7a, },
1607 { 6, 15375, 14250, 0x79, },
1608 { 7, 15250, 14125, 0x78, },
1609 { 8, 15125, 14000, 0x77, },
1610 { 9, 15000, 13875, 0x76, },
1611 { 10, 14875, 13750, 0x75, },
1612 { 11, 14750, 13625, 0x74, },
1613 { 12, 14625, 13500, 0x73, },
1614 { 13, 14500, 13375, 0x72, },
1615 { 14, 14375, 13250, 0x71, },
1616 { 15, 14250, 13125, 0x70, },
1617 { 16, 14125, 13000, 0x6f, },
1618 { 17, 14000, 12875, 0x6e, },
1619 { 18, 13875, 12750, 0x6d, },
1620 { 19, 13750, 12625, 0x6c, },
1621 { 20, 13625, 12500, 0x6b, },
1622 { 21, 13500, 12375, 0x6a, },
1623 { 22, 13375, 12250, 0x69, },
1624 { 23, 13250, 12125, 0x68, },
1625 { 24, 13125, 12000, 0x67, },
1626 { 25, 13000, 11875, 0x66, },
1627 { 26, 12875, 11750, 0x65, },
1628 { 27, 12750, 11625, 0x64, },
1629 { 28, 12625, 11500, 0x63, },
1630 { 29, 12500, 11375, 0x62, },
1631 { 30, 12375, 11250, 0x61, },
1632 { 31, 12250, 11125, 0x60, },
1633 { 32, 12125, 11000, 0x5f, },
1634 { 33, 12000, 10875, 0x5e, },
1635 { 34, 11875, 10750, 0x5d, },
1636 { 35, 11750, 10625, 0x5c, },
1637 { 36, 11625, 10500, 0x5b, },
1638 { 37, 11500, 10375, 0x5a, },
1639 { 38, 11375, 10250, 0x59, },
1640 { 39, 11250, 10125, 0x58, },
1641 { 40, 11125, 10000, 0x57, },
1642 { 41, 11000, 9875, 0x56, },
1643 { 42, 10875, 9750, 0x55, },
1644 { 43, 10750, 9625, 0x54, },
1645 { 44, 10625, 9500, 0x53, },
1646 { 45, 10500, 9375, 0x52, },
1647 { 46, 10375, 9250, 0x51, },
1648 { 47, 10250, 9125, 0x50, },
1649 { 48, 10125, 9000, 0x4f, },
1650 { 49, 10000, 8875, 0x4e, },
1651 { 50, 9875, 8750, 0x4d, },
1652 { 51, 9750, 8625, 0x4c, },
1653 { 52, 9625, 8500, 0x4b, },
1654 { 53, 9500, 8375, 0x4a, },
1655 { 54, 9375, 8250, 0x49, },
1656 { 55, 9250, 8125, 0x48, },
1657 { 56, 9125, 8000, 0x47, },
1658 { 57, 9000, 7875, 0x46, },
1659 { 58, 8875, 7750, 0x45, },
1660 { 59, 8750, 7625, 0x44, },
1661 { 60, 8625, 7500, 0x43, },
1662 { 61, 8500, 7375, 0x42, },
1663 { 62, 8375, 7250, 0x41, },
1664 { 63, 8250, 7125, 0x40, },
1665 { 64, 8125, 7000, 0x3f, },
1666 { 65, 8000, 6875, 0x3e, },
1667 { 66, 7875, 6750, 0x3d, },
1668 { 67, 7750, 6625, 0x3c, },
1669 { 68, 7625, 6500, 0x3b, },
1670 { 69, 7500, 6375, 0x3a, },
1671 { 70, 7375, 6250, 0x39, },
1672 { 71, 7250, 6125, 0x38, },
1673 { 72, 7125, 6000, 0x37, },
1674 { 73, 7000, 5875, 0x36, },
1675 { 74, 6875, 5750, 0x35, },
1676 { 75, 6750, 5625, 0x34, },
1677 { 76, 6625, 5500, 0x33, },
1678 { 77, 6500, 5375, 0x32, },
1679 { 78, 6375, 5250, 0x31, },
1680 { 79, 6250, 5125, 0x30, },
1681 { 80, 6125, 5000, 0x2f, },
1682 { 81, 6000, 4875, 0x2e, },
1683 { 82, 5875, 4750, 0x2d, },
1684 { 83, 5750, 4625, 0x2c, },
1685 { 84, 5625, 4500, 0x2b, },
1686 { 85, 5500, 4375, 0x2a, },
1687 { 86, 5375, 4250, 0x29, },
1688 { 87, 5250, 4125, 0x28, },
1689 { 88, 5125, 4000, 0x27, },
1690 { 89, 5000, 3875, 0x26, },
1691 { 90, 4875, 3750, 0x25, },
1692 { 91, 4750, 3625, 0x24, },
1693 { 92, 4625, 3500, 0x23, },
1694 { 93, 4500, 3375, 0x22, },
1695 { 94, 4375, 3250, 0x21, },
1696 { 95, 4250, 3125, 0x20, },
1697 { 96, 4125, 3000, 0x1f, },
1698 { 97, 4125, 3000, 0x1e, },
1699 { 98, 4125, 3000, 0x1d, },
1700 { 99, 4125, 3000, 0x1c, },
1701 { 100, 4125, 3000, 0x1b, },
1702 { 101, 4125, 3000, 0x1a, },
1703 { 102, 4125, 3000, 0x19, },
1704 { 103, 4125, 3000, 0x18, },
1705 { 104, 4125, 3000, 0x17, },
1706 { 105, 4125, 3000, 0x16, },
1707 { 106, 4125, 3000, 0x15, },
1708 { 107, 4125, 3000, 0x14, },
1709 { 108, 4125, 3000, 0x13, },
1710 { 109, 4125, 3000, 0x12, },
1711 { 110, 4125, 3000, 0x11, },
1712 { 111, 4125, 3000, 0x10, },
1713 { 112, 4125, 3000, 0x0f, },
1714 { 113, 4125, 3000, 0x0e, },
1715 { 114, 4125, 3000, 0x0d, },
1716 { 115, 4125, 3000, 0x0c, },
1717 { 116, 4125, 3000, 0x0b, },
1718 { 117, 4125, 3000, 0x0a, },
1719 { 118, 4125, 3000, 0x09, },
1720 { 119, 4125, 3000, 0x08, },
1721 { 120, 1125, 0, 0x07, },
1722 { 121, 1000, 0, 0x06, },
1723 { 122, 875, 0, 0x05, },
1724 { 123, 750, 0, 0x04, },
1725 { 124, 625, 0, 0x03, },
1726 { 125, 500, 0, 0x02, },
1727 { 126, 375, 0, 0x01, },
1728 { 127, 0, 0, 0x00, },
1729 };
1730
1731 struct cparams {
1732 int i;
1733 int t;
1734 int m;
1735 int c;
1736 };
1737
1738 static struct cparams cparams[] = {
1739 { 1, 1333, 301, 28664 },
1740 { 1, 1066, 294, 24460 },
1741 { 1, 800, 294, 25192 },
1742 { 0, 1333, 276, 27605 },
1743 { 0, 1066, 276, 27605 },
1744 { 0, 800, 231, 23784 },
1745 };
1746
1747 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1748 {
1749 u64 total_count, diff, ret;
1750 u32 count1, count2, count3, m = 0, c = 0;
1751 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1752 int i;
1753
1754 diff1 = now - dev_priv->last_time1;
1755
1756 count1 = I915_READ(DMIEC);
1757 count2 = I915_READ(DDREC);
1758 count3 = I915_READ(CSIEC);
1759
1760 total_count = count1 + count2 + count3;
1761
1762 /* FIXME: handle per-counter overflow */
1763 if (total_count < dev_priv->last_count1) {
1764 diff = ~0UL - dev_priv->last_count1;
1765 diff += total_count;
1766 } else {
1767 diff = total_count - dev_priv->last_count1;
1768 }
1769
1770 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1771 if (cparams[i].i == dev_priv->c_m &&
1772 cparams[i].t == dev_priv->r_t) {
1773 m = cparams[i].m;
1774 c = cparams[i].c;
1775 break;
1776 }
1777 }
1778
1779 div_u64(diff, diff1);
1780 ret = ((m * diff) + c);
1781 div_u64(ret, 10);
1782
1783 dev_priv->last_count1 = total_count;
1784 dev_priv->last_time1 = now;
1785
1786 return ret;
1787 }
1788
1789 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1790 {
1791 unsigned long m, x, b;
1792 u32 tsfs;
1793
1794 tsfs = I915_READ(TSFS);
1795
1796 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1797 x = I915_READ8(TR1);
1798
1799 b = tsfs & TSFS_INTR_MASK;
1800
1801 return ((m * x) / 127) - b;
1802 }
1803
1804 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1805 {
1806 unsigned long val = 0;
1807 int i;
1808
1809 for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1810 if (v_table[i].pvid == pxvid) {
1811 if (IS_MOBILE(dev_priv->dev))
1812 val = v_table[i].vm;
1813 else
1814 val = v_table[i].vd;
1815 }
1816 }
1817
1818 return val;
1819 }
1820
1821 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1822 {
1823 struct timespec now, diff1;
1824 u64 diff;
1825 unsigned long diffms;
1826 u32 count;
1827
1828 getrawmonotonic(&now);
1829 diff1 = timespec_sub(now, dev_priv->last_time2);
1830
1831 /* Don't divide by 0 */
1832 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1833 if (!diffms)
1834 return;
1835
1836 count = I915_READ(GFXEC);
1837
1838 if (count < dev_priv->last_count2) {
1839 diff = ~0UL - dev_priv->last_count2;
1840 diff += count;
1841 } else {
1842 diff = count - dev_priv->last_count2;
1843 }
1844
1845 dev_priv->last_count2 = count;
1846 dev_priv->last_time2 = now;
1847
1848 /* More magic constants... */
1849 diff = diff * 1181;
1850 div_u64(diff, diffms * 10);
1851 dev_priv->gfx_power = diff;
1852 }
1853
1854 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1855 {
1856 unsigned long t, corr, state1, corr2, state2;
1857 u32 pxvid, ext_v;
1858
1859 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1860 pxvid = (pxvid >> 24) & 0x7f;
1861 ext_v = pvid_to_extvid(dev_priv, pxvid);
1862
1863 state1 = ext_v;
1864
1865 t = i915_mch_val(dev_priv);
1866
1867 /* Revel in the empirically derived constants */
1868
1869 /* Correction factor in 1/100000 units */
1870 if (t > 80)
1871 corr = ((t * 2349) + 135940);
1872 else if (t >= 50)
1873 corr = ((t * 964) + 29317);
1874 else /* < 50 */
1875 corr = ((t * 301) + 1004);
1876
1877 corr = corr * ((150142 * state1) / 10000 - 78642);
1878 corr /= 100000;
1879 corr2 = (corr * dev_priv->corr);
1880
1881 state2 = (corr2 * state1) / 10000;
1882 state2 /= 100; /* convert to mW */
1883
1884 i915_update_gfx_val(dev_priv);
1885
1886 return dev_priv->gfx_power + state2;
1887 }
1888
1889 /* Global for IPS driver to get at the current i915 device */
1890 static struct drm_i915_private *i915_mch_dev;
1891 /*
1892 * Lock protecting IPS related data structures
1893 * - i915_mch_dev
1894 * - dev_priv->max_delay
1895 * - dev_priv->min_delay
1896 * - dev_priv->fmax
1897 * - dev_priv->gpu_busy
1898 */
1899 static DEFINE_SPINLOCK(mchdev_lock);
1900
1901 /**
1902 * i915_read_mch_val - return value for IPS use
1903 *
1904 * Calculate and return a value for the IPS driver to use when deciding whether
1905 * we have thermal and power headroom to increase CPU or GPU power budget.
1906 */
1907 unsigned long i915_read_mch_val(void)
1908 {
1909 struct drm_i915_private *dev_priv;
1910 unsigned long chipset_val, graphics_val, ret = 0;
1911
1912 spin_lock(&mchdev_lock);
1913 if (!i915_mch_dev)
1914 goto out_unlock;
1915 dev_priv = i915_mch_dev;
1916
1917 chipset_val = i915_chipset_val(dev_priv);
1918 graphics_val = i915_gfx_val(dev_priv);
1919
1920 ret = chipset_val + graphics_val;
1921
1922 out_unlock:
1923 spin_unlock(&mchdev_lock);
1924
1925 return ret;
1926 }
1927 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1928
1929 /**
1930 * i915_gpu_raise - raise GPU frequency limit
1931 *
1932 * Raise the limit; IPS indicates we have thermal headroom.
1933 */
1934 bool i915_gpu_raise(void)
1935 {
1936 struct drm_i915_private *dev_priv;
1937 bool ret = true;
1938
1939 spin_lock(&mchdev_lock);
1940 if (!i915_mch_dev) {
1941 ret = false;
1942 goto out_unlock;
1943 }
1944 dev_priv = i915_mch_dev;
1945
1946 if (dev_priv->max_delay > dev_priv->fmax)
1947 dev_priv->max_delay--;
1948
1949 out_unlock:
1950 spin_unlock(&mchdev_lock);
1951
1952 return ret;
1953 }
1954 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1955
1956 /**
1957 * i915_gpu_lower - lower GPU frequency limit
1958 *
1959 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1960 * frequency maximum.
1961 */
1962 bool i915_gpu_lower(void)
1963 {
1964 struct drm_i915_private *dev_priv;
1965 bool ret = true;
1966
1967 spin_lock(&mchdev_lock);
1968 if (!i915_mch_dev) {
1969 ret = false;
1970 goto out_unlock;
1971 }
1972 dev_priv = i915_mch_dev;
1973
1974 if (dev_priv->max_delay < dev_priv->min_delay)
1975 dev_priv->max_delay++;
1976
1977 out_unlock:
1978 spin_unlock(&mchdev_lock);
1979
1980 return ret;
1981 }
1982 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1983
1984 /**
1985 * i915_gpu_busy - indicate GPU business to IPS
1986 *
1987 * Tell the IPS driver whether or not the GPU is busy.
1988 */
1989 bool i915_gpu_busy(void)
1990 {
1991 struct drm_i915_private *dev_priv;
1992 bool ret = false;
1993
1994 spin_lock(&mchdev_lock);
1995 if (!i915_mch_dev)
1996 goto out_unlock;
1997 dev_priv = i915_mch_dev;
1998
1999 ret = dev_priv->busy;
2000
2001 out_unlock:
2002 spin_unlock(&mchdev_lock);
2003
2004 return ret;
2005 }
2006 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2007
2008 /**
2009 * i915_gpu_turbo_disable - disable graphics turbo
2010 *
2011 * Disable graphics turbo by resetting the max frequency and setting the
2012 * current frequency to the default.
2013 */
2014 bool i915_gpu_turbo_disable(void)
2015 {
2016 struct drm_i915_private *dev_priv;
2017 bool ret = true;
2018
2019 spin_lock(&mchdev_lock);
2020 if (!i915_mch_dev) {
2021 ret = false;
2022 goto out_unlock;
2023 }
2024 dev_priv = i915_mch_dev;
2025
2026 dev_priv->max_delay = dev_priv->fstart;
2027
2028 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2029 ret = false;
2030
2031 out_unlock:
2032 spin_unlock(&mchdev_lock);
2033
2034 return ret;
2035 }
2036 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2037
2038 /**
2039 * i915_driver_load - setup chip and create an initial config
2040 * @dev: DRM device
2041 * @flags: startup flags
2042 *
2043 * The driver load routine has to do several things:
2044 * - drive output discovery via intel_modeset_init()
2045 * - initialize the memory manager
2046 * - allocate initial config memory
2047 * - setup the DRM framebuffer with the allocated memory
2048 */
2049 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2050 {
2051 struct drm_i915_private *dev_priv;
2052 resource_size_t base, size;
2053 int ret = 0, mmio_bar;
2054 uint32_t agp_size, prealloc_size, prealloc_start;
2055 /* i915 has 4 more counters */
2056 dev->counters += 4;
2057 dev->types[6] = _DRM_STAT_IRQ;
2058 dev->types[7] = _DRM_STAT_PRIMARY;
2059 dev->types[8] = _DRM_STAT_SECONDARY;
2060 dev->types[9] = _DRM_STAT_DMA;
2061
2062 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2063 if (dev_priv == NULL)
2064 return -ENOMEM;
2065
2066 dev->dev_private = (void *)dev_priv;
2067 dev_priv->dev = dev;
2068 dev_priv->info = (struct intel_device_info *) flags;
2069
2070 /* Add register map (needed for suspend/resume) */
2071 mmio_bar = IS_I9XX(dev) ? 0 : 1;
2072 base = pci_resource_start(dev->pdev, mmio_bar);
2073 size = pci_resource_len(dev->pdev, mmio_bar);
2074
2075 if (i915_get_bridge_dev(dev)) {
2076 ret = -EIO;
2077 goto free_priv;
2078 }
2079
2080 /* overlay on gen2 is broken and can't address above 1G */
2081 if (IS_GEN2(dev))
2082 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2083
2084 dev_priv->regs = ioremap(base, size);
2085 if (!dev_priv->regs) {
2086 DRM_ERROR("failed to map registers\n");
2087 ret = -EIO;
2088 goto put_bridge;
2089 }
2090
2091 dev_priv->mm.gtt_mapping =
2092 io_mapping_create_wc(dev->agp->base,
2093 dev->agp->agp_info.aper_size * 1024*1024);
2094 if (dev_priv->mm.gtt_mapping == NULL) {
2095 ret = -EIO;
2096 goto out_rmmap;
2097 }
2098
2099 /* Set up a WC MTRR for non-PAT systems. This is more common than
2100 * one would think, because the kernel disables PAT on first
2101 * generation Core chips because WC PAT gets overridden by a UC
2102 * MTRR if present. Even if a UC MTRR isn't present.
2103 */
2104 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2105 dev->agp->agp_info.aper_size *
2106 1024 * 1024,
2107 MTRR_TYPE_WRCOMB, 1);
2108 if (dev_priv->mm.gtt_mtrr < 0) {
2109 DRM_INFO("MTRR allocation failed. Graphics "
2110 "performance may suffer.\n");
2111 }
2112
2113 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2114 if (ret)
2115 goto out_iomapfree;
2116
2117 if (prealloc_size > intel_max_stolen) {
2118 DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
2119 prealloc_size >> 20, intel_max_stolen >> 20);
2120 prealloc_size = intel_max_stolen;
2121 }
2122
2123 dev_priv->wq = create_singlethread_workqueue("i915");
2124 if (dev_priv->wq == NULL) {
2125 DRM_ERROR("Failed to create our workqueue.\n");
2126 ret = -ENOMEM;
2127 goto out_iomapfree;
2128 }
2129
2130 /* enable GEM by default */
2131 dev_priv->has_gem = 1;
2132
2133 if (prealloc_size > agp_size * 3 / 4) {
2134 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2135 "memory stolen.\n",
2136 prealloc_size / 1024, agp_size / 1024);
2137 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2138 "updating the BIOS to fix).\n");
2139 dev_priv->has_gem = 0;
2140 }
2141
2142 if (dev_priv->has_gem == 0 &&
2143 drm_core_check_feature(dev, DRIVER_MODESET)) {
2144 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2145 ret = -ENODEV;
2146 goto out_iomapfree;
2147 }
2148
2149 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2150 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2151 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2152 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2153 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2154 }
2155
2156 /* Try to make sure MCHBAR is enabled before poking at it */
2157 intel_setup_mchbar(dev);
2158 intel_opregion_setup(dev);
2159
2160 i915_gem_load(dev);
2161
2162 /* Init HWS */
2163 if (!I915_NEED_GFX_HWS(dev)) {
2164 ret = i915_init_phys_hws(dev);
2165 if (ret != 0)
2166 goto out_workqueue_free;
2167 }
2168
2169 if (IS_PINEVIEW(dev))
2170 i915_pineview_get_mem_freq(dev);
2171 else if (IS_IRONLAKE(dev))
2172 i915_ironlake_get_mem_freq(dev);
2173
2174 /* On the 945G/GM, the chipset reports the MSI capability on the
2175 * integrated graphics even though the support isn't actually there
2176 * according to the published specs. It doesn't appear to function
2177 * correctly in testing on 945G.
2178 * This may be a side effect of MSI having been made available for PEG
2179 * and the registers being closely associated.
2180 *
2181 * According to chipset errata, on the 965GM, MSI interrupts may
2182 * be lost or delayed, but we use them anyways to avoid
2183 * stuck interrupts on some machines.
2184 */
2185 if (!IS_I945G(dev) && !IS_I945GM(dev))
2186 pci_enable_msi(dev->pdev);
2187
2188 spin_lock_init(&dev_priv->user_irq_lock);
2189 spin_lock_init(&dev_priv->error_lock);
2190 dev_priv->trace_irq_seqno = 0;
2191
2192 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2193
2194 if (ret) {
2195 (void) i915_driver_unload(dev);
2196 return ret;
2197 }
2198
2199 /* Start out suspended */
2200 dev_priv->mm.suspended = 1;
2201
2202 intel_detect_pch(dev);
2203
2204 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2205 ret = i915_load_modeset_init(dev, prealloc_start,
2206 prealloc_size, agp_size);
2207 if (ret < 0) {
2208 DRM_ERROR("failed to init modeset\n");
2209 goto out_workqueue_free;
2210 }
2211 }
2212
2213 /* Must be done after probing outputs */
2214 intel_opregion_init(dev);
2215 acpi_video_register();
2216
2217 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2218 (unsigned long) dev);
2219
2220 spin_lock(&mchdev_lock);
2221 i915_mch_dev = dev_priv;
2222 dev_priv->mchdev_lock = &mchdev_lock;
2223 spin_unlock(&mchdev_lock);
2224
2225 return 0;
2226
2227 out_workqueue_free:
2228 destroy_workqueue(dev_priv->wq);
2229 out_iomapfree:
2230 io_mapping_free(dev_priv->mm.gtt_mapping);
2231 out_rmmap:
2232 iounmap(dev_priv->regs);
2233 put_bridge:
2234 pci_dev_put(dev_priv->bridge_dev);
2235 free_priv:
2236 kfree(dev_priv);
2237 return ret;
2238 }
2239
2240 int i915_driver_unload(struct drm_device *dev)
2241 {
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 int ret;
2244
2245 spin_lock(&mchdev_lock);
2246 i915_mch_dev = NULL;
2247 spin_unlock(&mchdev_lock);
2248
2249 mutex_lock(&dev->struct_mutex);
2250 ret = i915_gpu_idle(dev);
2251 if (ret)
2252 DRM_ERROR("failed to idle hardware: %d\n", ret);
2253 mutex_unlock(&dev->struct_mutex);
2254
2255 /* Cancel the retire work handler, which should be idle now. */
2256 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2257
2258 io_mapping_free(dev_priv->mm.gtt_mapping);
2259 if (dev_priv->mm.gtt_mtrr >= 0) {
2260 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2261 dev->agp->agp_info.aper_size * 1024 * 1024);
2262 dev_priv->mm.gtt_mtrr = -1;
2263 }
2264
2265 acpi_video_unregister();
2266
2267 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2268 intel_modeset_cleanup(dev);
2269
2270 /*
2271 * free the memory space allocated for the child device
2272 * config parsed from VBT
2273 */
2274 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2275 kfree(dev_priv->child_dev);
2276 dev_priv->child_dev = NULL;
2277 dev_priv->child_dev_num = 0;
2278 }
2279
2280 vga_switcheroo_unregister_client(dev->pdev);
2281 vga_client_register(dev->pdev, NULL, NULL, NULL);
2282 }
2283
2284 /* Free error state after interrupts are fully disabled. */
2285 del_timer_sync(&dev_priv->hangcheck_timer);
2286 cancel_work_sync(&dev_priv->error_work);
2287 i915_destroy_error_state(dev);
2288
2289 if (dev->pdev->msi_enabled)
2290 pci_disable_msi(dev->pdev);
2291
2292 if (dev_priv->regs != NULL)
2293 iounmap(dev_priv->regs);
2294
2295 intel_opregion_fini(dev);
2296
2297 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2298 /* Flush any outstanding unpin_work. */
2299 flush_workqueue(dev_priv->wq);
2300
2301 i915_gem_free_all_phys_object(dev);
2302
2303 mutex_lock(&dev->struct_mutex);
2304 i915_gem_cleanup_ringbuffer(dev);
2305 mutex_unlock(&dev->struct_mutex);
2306 if (I915_HAS_FBC(dev) && i915_powersave)
2307 i915_cleanup_compression(dev);
2308 drm_mm_takedown(&dev_priv->vram);
2309
2310 intel_cleanup_overlay(dev);
2311 }
2312
2313 intel_teardown_mchbar(dev);
2314
2315 destroy_workqueue(dev_priv->wq);
2316
2317 pci_dev_put(dev_priv->bridge_dev);
2318 kfree(dev->dev_private);
2319
2320 return 0;
2321 }
2322
2323 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2324 {
2325 struct drm_i915_file_private *i915_file_priv;
2326
2327 DRM_DEBUG_DRIVER("\n");
2328 i915_file_priv = (struct drm_i915_file_private *)
2329 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2330
2331 if (!i915_file_priv)
2332 return -ENOMEM;
2333
2334 file_priv->driver_priv = i915_file_priv;
2335
2336 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2337
2338 return 0;
2339 }
2340
2341 /**
2342 * i915_driver_lastclose - clean up after all DRM clients have exited
2343 * @dev: DRM device
2344 *
2345 * Take care of cleaning up after all DRM clients have exited. In the
2346 * mode setting case, we want to restore the kernel's initial mode (just
2347 * in case the last client left us in a bad state).
2348 *
2349 * Additionally, in the non-mode setting case, we'll tear down the AGP
2350 * and DMA structures, since the kernel won't be using them, and clea
2351 * up any GEM state.
2352 */
2353 void i915_driver_lastclose(struct drm_device * dev)
2354 {
2355 drm_i915_private_t *dev_priv = dev->dev_private;
2356
2357 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2358 drm_fb_helper_restore();
2359 vga_switcheroo_process_delayed_switch();
2360 return;
2361 }
2362
2363 i915_gem_lastclose(dev);
2364
2365 if (dev_priv->agp_heap)
2366 i915_mem_takedown(&(dev_priv->agp_heap));
2367
2368 i915_dma_cleanup(dev);
2369 }
2370
2371 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2372 {
2373 drm_i915_private_t *dev_priv = dev->dev_private;
2374 i915_gem_release(dev, file_priv);
2375 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2376 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2377 }
2378
2379 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2380 {
2381 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2382
2383 kfree(i915_file_priv);
2384 }
2385
2386 struct drm_ioctl_desc i915_ioctls[] = {
2387 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2388 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2389 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2390 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2391 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2392 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2393 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2394 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2395 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2396 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2397 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2398 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2399 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2400 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2401 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2402 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2403 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2404 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2405 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2406 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2407 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2408 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2409 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2410 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2411 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2412 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2413 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2414 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2415 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2416 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2417 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2418 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2419 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2420 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2421 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2422 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2423 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2424 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2425 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2426 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2427 };
2428
2429 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2430
2431 /**
2432 * Determine if the device really is AGP or not.
2433 *
2434 * All Intel graphics chipsets are treated as AGP, even if they are really
2435 * PCI-e.
2436 *
2437 * \param dev The device to be tested.
2438 *
2439 * \returns
2440 * A value of 1 is always retured to indictate every i9x5 is AGP.
2441 */
2442 int i915_driver_device_is_agp(struct drm_device * dev)
2443 {
2444 return 1;
2445 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree