sdhci: Add support for bus-specific IO memory accessors
commit4e4141a526dd7f5ac3ce1458ae79ea6e5a515b06
authorAnton Vorontsov <avorontsov@ru.mvista.com>
Mon, 16 Mar 2009 21:13:46 +0000 (17 00:13 +0300)
committerPierre Ossman <drzeus@drzeus.cx>
Tue, 24 Mar 2009 20:30:07 +0000 (24 21:30 +0100)
tree06f374b2e3a7a22eb66261d79d3374b1d23e5350
parentf079a8fc61e3dc35830f6abc58c21ae815ab4297
sdhci: Add support for bus-specific IO memory accessors

Currently the SDHCI driver works with PCI accessors (write{l,b,w} and
read{l,b,w}).

With this patch drivers may change memory accessors, so that we can
support hosts with "weird" IO memory access requirments.

For example, in "FSL eSDHC" SDHCI hardware all registers are 32 bit
width, with big-endian addressing. That is, readb(0x2f) should turn
into readb(0x2c), and readw(0x2c) should be translated to
le16_to_cpu(readw(0x2e)).

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
drivers/mmc/host/Kconfig
drivers/mmc/host/sdhci.c
drivers/mmc/host/sdhci.h