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CGroup API files: drop mem_cgroup_force_empty()
[linux-2.6/linux-2.6-openrd.git] / drivers / video / tridentfb.c
blobbd54cd0de39af13fc4170665878ed63ac1af4acb
1 /*
2 * Frame buffer driver for Trident Blade and Image series
3 *
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 *
6 *
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
13 * code, suggestions
14 * TODO:
15 * timing value tweaking so it looks good on every monitor in every mode
16 * TGUI acceleration
17 */
18
19 #include <linux/module.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23
24 #include <linux/delay.h>
25 #include <video/trident.h>
26
27 #define VERSION "0.7.8-NEWAPI"
28
29 struct tridentfb_par {
30 int vclk; /* in MHz */
31 void __iomem *io_virt; /* iospace virtual memory address */
32 };
33
34 static unsigned char eng_oper; /* engine operation... */
35 static struct fb_ops tridentfb_ops;
36
37 static struct tridentfb_par default_par;
38
39 /* FIXME:kmalloc these 3 instead */
40 static struct fb_info fb_info;
41 static u32 pseudo_pal[16];
42
43 static struct fb_var_screeninfo default_var;
44
45 static struct fb_fix_screeninfo tridentfb_fix = {
46 .id = "Trident",
47 .type = FB_TYPE_PACKED_PIXELS,
48 .ypanstep = 1,
49 .visual = FB_VISUAL_PSEUDOCOLOR,
50 .accel = FB_ACCEL_NONE,
51 };
52
53 static int chip_id;
54
55 static int defaultaccel;
56 static int displaytype;
57
58 /* defaults which are normally overriden by user values */
59
60 /* video mode */
61 static char *mode_option __devinitdata = "640x480";
62 static int bpp = 8;
63
64 static int noaccel;
65
66 static int center;
67 static int stretch;
68
69 static int fp;
70 static int crt;
71
72 static int memsize;
73 static int memdiff;
74 static int nativex;
75
76 module_param(mode_option, charp, 0);
77 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
78 module_param_named(mode, mode_option, charp, 0);
79 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
80 module_param(bpp, int, 0);
81 module_param(center, int, 0);
82 module_param(stretch, int, 0);
83 module_param(noaccel, int, 0);
84 module_param(memsize, int, 0);
85 module_param(memdiff, int, 0);
86 module_param(nativex, int, 0);
87 module_param(fp, int, 0);
88 module_param(crt, int, 0);
89
90 static int chip3D;
91 static int chipcyber;
92
93 static int is3Dchip(int id)
94 {
95 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
96 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
97 (id == CYBER9397) || (id == CYBER9397DVD) ||
98 (id == CYBER9520) || (id == CYBER9525DVD) ||
99 (id == IMAGE975) || (id == IMAGE985) ||
100 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
101 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
102 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
103 (id == CYBERBLADEXPAi1));
104 }
105
106 static int iscyber(int id)
107 {
108 switch (id) {
109 case CYBER9388:
110 case CYBER9382:
111 case CYBER9385:
112 case CYBER9397:
113 case CYBER9397DVD:
114 case CYBER9520:
115 case CYBER9525DVD:
116 case CYBERBLADEE4:
117 case CYBERBLADEi7D:
118 case CYBERBLADEi1:
119 case CYBERBLADEi1D:
120 case CYBERBLADEAi1:
121 case CYBERBLADEAi1D:
122 case CYBERBLADEXPAi1:
123 return 1;
124
125 case CYBER9320:
126 case TGUI9660:
127 case IMAGE975:
128 case IMAGE985:
129 case BLADE3D:
130 case CYBERBLADEi7: /* VIA MPV4 integrated version */
131
132 default:
133 /* case CYBERBLDAEXPm8: Strange */
134 /* case CYBERBLDAEXPm16: Strange */
135 return 0;
136 }
137 }
138
139 #define CRT 0x3D0 /* CRTC registers offset for color display */
140
141 #ifndef TRIDENT_MMIO
142 #define TRIDENT_MMIO 1
143 #endif
144
145 #if TRIDENT_MMIO
146 #define t_outb(val, reg) writeb(val,((struct tridentfb_par *)(fb_info.par))->io_virt + reg)
147 #define t_inb(reg) readb(((struct tridentfb_par*)(fb_info.par))->io_virt + reg)
148 #else
149 #define t_outb(val, reg) outb(val, reg)
150 #define t_inb(reg) inb(reg)
151 #endif
152
153
154 static struct accel_switch {
155 void (*init_accel) (int, int);
156 void (*wait_engine) (void);
157 void (*fill_rect) (u32, u32, u32, u32, u32, u32);
158 void (*copy_rect) (u32, u32, u32, u32, u32, u32);
159 } *acc;
160
161 #define writemmr(r, v) writel(v, ((struct tridentfb_par *)fb_info.par)->io_virt + r)
162 #define readmmr(r) readl(((struct tridentfb_par *)fb_info.par)->io_virt + r)
163
164 /*
165 * Blade specific acceleration.
166 */
167
168 #define point(x, y) ((y) << 16 | (x))
169 #define STA 0x2120
170 #define CMD 0x2144
171 #define ROP 0x2148
172 #define CLR 0x2160
173 #define SR1 0x2100
174 #define SR2 0x2104
175 #define DR1 0x2108
176 #define DR2 0x210C
177
178 #define ROP_S 0xCC
179
180 static void blade_init_accel(int pitch, int bpp)
181 {
182 int v1 = (pitch >> 3) << 20;
183 int tmp = 0, v2;
184 switch (bpp) {
185 case 8:
186 tmp = 0;
187 break;
188 case 15:
189 tmp = 5;
190 break;
191 case 16:
192 tmp = 1;
193 break;
194 case 24:
195 case 32:
196 tmp = 2;
197 break;
198 }
199 v2 = v1 | (tmp << 29);
200 writemmr(0x21C0, v2);
201 writemmr(0x21C4, v2);
202 writemmr(0x21B8, v2);
203 writemmr(0x21BC, v2);
204 writemmr(0x21D0, v1);
205 writemmr(0x21D4, v1);
206 writemmr(0x21C8, v1);
207 writemmr(0x21CC, v1);
208 writemmr(0x216C, 0);
209 }
210
211 static void blade_wait_engine(void)
212 {
213 while (readmmr(STA) & 0xFA800000) ;
214 }
215
216 static void blade_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
217 {
218 writemmr(CLR, c);
219 writemmr(ROP, rop ? 0x66 : ROP_S);
220 writemmr(CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
221
222 writemmr(DR1, point(x, y));
223 writemmr(DR2, point(x + w - 1, y + h - 1));
224 }
225
226 static void blade_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
227 {
228 u32 s1, s2, d1, d2;
229 int direction = 2;
230 s1 = point(x1, y1);
231 s2 = point(x1 + w - 1, y1 + h - 1);
232 d1 = point(x2, y2);
233 d2 = point(x2 + w - 1, y2 + h - 1);
234
235 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
236 direction = 0;
237
238 writemmr(ROP, ROP_S);
239 writemmr(CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
240
241 writemmr(SR1, direction ? s2 : s1);
242 writemmr(SR2, direction ? s1 : s2);
243 writemmr(DR1, direction ? d2 : d1);
244 writemmr(DR2, direction ? d1 : d2);
245 }
246
247 static struct accel_switch accel_blade = {
248 blade_init_accel,
249 blade_wait_engine,
250 blade_fill_rect,
251 blade_copy_rect,
252 };
253
254 /*
255 * BladeXP specific acceleration functions
256 */
257
258 #define ROP_P 0xF0
259 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
260
261 static void xp_init_accel(int pitch, int bpp)
262 {
263 int tmp = 0, v1;
264 unsigned char x = 0;
265
266 switch (bpp) {
267 case 8:
268 x = 0;
269 break;
270 case 16:
271 x = 1;
272 break;
273 case 24:
274 x = 3;
275 break;
276 case 32:
277 x = 2;
278 break;
279 }
280
281 switch (pitch << (bpp >> 3)) {
282 case 8192:
283 case 512:
284 x |= 0x00;
285 break;
286 case 1024:
287 x |= 0x04;
288 break;
289 case 2048:
290 x |= 0x08;
291 break;
292 case 4096:
293 x |= 0x0C;
294 break;
295 }
296
297 t_outb(x, 0x2125);
298
299 eng_oper = x | 0x40;
300
301 switch (bpp) {
302 case 8:
303 tmp = 18;
304 break;
305 case 15:
306 case 16:
307 tmp = 19;
308 break;
309 case 24:
310 case 32:
311 tmp = 20;
312 break;
313 }
314
315 v1 = pitch << tmp;
316
317 writemmr(0x2154, v1);
318 writemmr(0x2150, v1);
319 t_outb(3, 0x2126);
320 }
321
322 static void xp_wait_engine(void)
323 {
324 int busy;
325 int count, timeout;
326
327 count = 0;
328 timeout = 0;
329 for (;;) {
330 busy = t_inb(STA) & 0x80;
331 if (busy != 0x80)
332 return;
333 count++;
334 if (count == 10000000) {
335 /* Timeout */
336 count = 9990000;
337 timeout++;
338 if (timeout == 8) {
339 /* Reset engine */
340 t_outb(0x00, 0x2120);
341 return;
342 }
343 }
344 }
345 }
346
347 static void xp_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
348 {
349 writemmr(0x2127, ROP_P);
350 writemmr(0x2158, c);
351 writemmr(0x2128, 0x4000);
352 writemmr(0x2140, masked_point(h, w));
353 writemmr(0x2138, masked_point(y, x));
354 t_outb(0x01, 0x2124);
355 t_outb(eng_oper, 0x2125);
356 }
357
358 static void xp_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
359 {
360 int direction;
361 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
362
363 direction = 0x0004;
364
365 if ((x1 < x2) && (y1 == y2)) {
366 direction |= 0x0200;
367 x1_tmp = x1 + w - 1;
368 x2_tmp = x2 + w - 1;
369 } else {
370 x1_tmp = x1;
371 x2_tmp = x2;
372 }
373
374 if (y1 < y2) {
375 direction |= 0x0100;
376 y1_tmp = y1 + h - 1;
377 y2_tmp = y2 + h - 1;
378 } else {
379 y1_tmp = y1;
380 y2_tmp = y2;
381 }
382
383 writemmr(0x2128, direction);
384 t_outb(ROP_S, 0x2127);
385 writemmr(0x213C, masked_point(y1_tmp, x1_tmp));
386 writemmr(0x2138, masked_point(y2_tmp, x2_tmp));
387 writemmr(0x2140, masked_point(h, w));
388 t_outb(0x01, 0x2124);
389 }
390
391 static struct accel_switch accel_xp = {
392 xp_init_accel,
393 xp_wait_engine,
394 xp_fill_rect,
395 xp_copy_rect,
396 };
397
398 /*
399 * Image specific acceleration functions
400 */
401 static void image_init_accel(int pitch, int bpp)
402 {
403 int tmp = 0;
404 switch (bpp) {
405 case 8:
406 tmp = 0;
407 break;
408 case 15:
409 tmp = 5;
410 break;
411 case 16:
412 tmp = 1;
413 break;
414 case 24:
415 case 32:
416 tmp = 2;
417 break;
418 }
419 writemmr(0x2120, 0xF0000000);
420 writemmr(0x2120, 0x40000000 | tmp);
421 writemmr(0x2120, 0x80000000);
422 writemmr(0x2144, 0x00000000);
423 writemmr(0x2148, 0x00000000);
424 writemmr(0x2150, 0x00000000);
425 writemmr(0x2154, 0x00000000);
426 writemmr(0x2120, 0x60000000 | (pitch << 16) | pitch);
427 writemmr(0x216C, 0x00000000);
428 writemmr(0x2170, 0x00000000);
429 writemmr(0x217C, 0x00000000);
430 writemmr(0x2120, 0x10000000);
431 writemmr(0x2130, (2047 << 16) | 2047);
432 }
433
434 static void image_wait_engine(void)
435 {
436 while (readmmr(0x2164) & 0xF0000000) ;
437 }
438
439 static void image_fill_rect(u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
440 {
441 writemmr(0x2120, 0x80000000);
442 writemmr(0x2120, 0x90000000 | ROP_S);
443
444 writemmr(0x2144, c);
445
446 writemmr(DR1, point(x, y));
447 writemmr(DR2, point(x + w - 1, y + h - 1));
448
449 writemmr(0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
450 }
451
452 static void image_copy_rect(u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
453 {
454 u32 s1, s2, d1, d2;
455 int direction = 2;
456 s1 = point(x1, y1);
457 s2 = point(x1 + w - 1, y1 + h - 1);
458 d1 = point(x2, y2);
459 d2 = point(x2 + w - 1, y2 + h - 1);
460
461 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
462 direction = 0;
463
464 writemmr(0x2120, 0x80000000);
465 writemmr(0x2120, 0x90000000 | ROP_S);
466
467 writemmr(SR1, direction ? s2 : s1);
468 writemmr(SR2, direction ? s1 : s2);
469 writemmr(DR1, direction ? d2 : d1);
470 writemmr(DR2, direction ? d1 : d2);
471 writemmr(0x2124, 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
472 }
473
474 static struct accel_switch accel_image = {
475 image_init_accel,
476 image_wait_engine,
477 image_fill_rect,
478 image_copy_rect,
479 };
480
481 /*
482 * Accel functions called by the upper layers
483 */
484 #ifdef CONFIG_FB_TRIDENT_ACCEL
485 static void tridentfb_fillrect(struct fb_info *info,
486 const struct fb_fillrect *fr)
487 {
488 int bpp = info->var.bits_per_pixel;
489 int col = 0;
490
491 switch (bpp) {
492 default:
493 case 8:
494 col |= fr->color;
495 col |= col << 8;
496 col |= col << 16;
497 break;
498 case 16:
499 col = ((u32 *)(info->pseudo_palette))[fr->color];
500 break;
501 case 32:
502 col = ((u32 *)(info->pseudo_palette))[fr->color];
503 break;
504 }
505
506 acc->fill_rect(fr->dx, fr->dy, fr->width, fr->height, col, fr->rop);
507 acc->wait_engine();
508 }
509 static void tridentfb_copyarea(struct fb_info *info,
510 const struct fb_copyarea *ca)
511 {
512 acc->copy_rect(ca->sx, ca->sy, ca->dx, ca->dy, ca->width, ca->height);
513 acc->wait_engine();
514 }
515 #else /* !CONFIG_FB_TRIDENT_ACCEL */
516 #define tridentfb_fillrect cfb_fillrect
517 #define tridentfb_copyarea cfb_copyarea
518 #endif /* CONFIG_FB_TRIDENT_ACCEL */
519
520
521 /*
522 * Hardware access functions
523 */
524
525 static inline unsigned char read3X4(int reg)
526 {
527 struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par;
528 writeb(reg, par->io_virt + CRT + 4);
529 return readb(par->io_virt + CRT + 5);
530 }
531
532 static inline void write3X4(int reg, unsigned char val)
533 {
534 struct tridentfb_par *par = (struct tridentfb_par *)fb_info.par;
535 writeb(reg, par->io_virt + CRT + 4);
536 writeb(val, par->io_virt + CRT + 5);
537 }
538
539 static inline unsigned char read3C4(int reg)
540 {
541 t_outb(reg, 0x3C4);
542 return t_inb(0x3C5);
543 }
544
545 static inline void write3C4(int reg, unsigned char val)
546 {
547 t_outb(reg, 0x3C4);
548 t_outb(val, 0x3C5);
549 }
550
551 static inline unsigned char read3CE(int reg)
552 {
553 t_outb(reg, 0x3CE);
554 return t_inb(0x3CF);
555 }
556
557 static inline void writeAttr(int reg, unsigned char val)
558 {
559 readb(((struct tridentfb_par *)fb_info.par)->io_virt + CRT + 0x0A); /* flip-flop to index */
560 t_outb(reg, 0x3C0);
561 t_outb(val, 0x3C0);
562 }
563
564 static inline void write3CE(int reg, unsigned char val)
565 {
566 t_outb(reg, 0x3CE);
567 t_outb(val, 0x3CF);
568 }
569
570 static void enable_mmio(void)
571 {
572 /* Goto New Mode */
573 outb(0x0B, 0x3C4);
574 inb(0x3C5);
575
576 /* Unprotect registers */
577 outb(NewMode1, 0x3C4);
578 outb(0x80, 0x3C5);
579
580 /* Enable MMIO */
581 outb(PCIReg, 0x3D4);
582 outb(inb(0x3D5) | 0x01, 0x3D5);
583 }
584
585 static void disable_mmio(void)
586 {
587 /* Goto New Mode */
588 t_outb(0x0B, 0x3C4);
589 t_inb(0x3C5);
590
591 /* Unprotect registers */
592 t_outb(NewMode1, 0x3C4);
593 t_outb(0x80, 0x3C5);
594
595 /* Disable MMIO */
596 t_outb(PCIReg, 0x3D4);
597 t_outb(t_inb(0x3D5) & ~0x01, 0x3D5);
598 }
599
600 #define crtc_unlock() write3X4(CRTVSyncEnd, read3X4(CRTVSyncEnd) & 0x7F)
601
602 /* Return flat panel's maximum x resolution */
603 static int __devinit get_nativex(void)
604 {
605 int x, y, tmp;
606
607 if (nativex)
608 return nativex;
609
610 tmp = (read3CE(VertStretch) >> 4) & 3;
611
612 switch (tmp) {
613 case 0:
614 x = 1280; y = 1024;
615 break;
616 case 2:
617 x = 1024; y = 768;
618 break;
619 case 3:
620 x = 800; y = 600;
621 break;
622 case 4:
623 x = 1400; y = 1050;
624 break;
625 case 1:
626 default:
627 x = 640; y = 480;
628 break;
629 }
630
631 output("%dx%d flat panel found\n", x, y);
632 return x;
633 }
634
635 /* Set pitch */
636 static void set_lwidth(int width)
637 {
638 write3X4(Offset, width & 0xFF);
639 write3X4(AddColReg,
640 (read3X4(AddColReg) & 0xCF) | ((width & 0x300) >> 4));
641 }
642
643 /* For resolutions smaller than FP resolution stretch */
644 static void screen_stretch(void)
645 {
646 if (chip_id != CYBERBLADEXPAi1)
647 write3CE(BiosReg, 0);
648 else
649 write3CE(BiosReg, 8);
650 write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 1);
651 write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 1);
652 }
653
654 /* For resolutions smaller than FP resolution center */
655 static void screen_center(void)
656 {
657 write3CE(VertStretch, (read3CE(VertStretch) & 0x7C) | 0x80);
658 write3CE(HorStretch, (read3CE(HorStretch) & 0x7C) | 0x80);
659 }
660
661 /* Address of first shown pixel in display memory */
662 static void set_screen_start(int base)
663 {
664 write3X4(StartAddrLow, base & 0xFF);
665 write3X4(StartAddrHigh, (base & 0xFF00) >> 8);
666 write3X4(CRTCModuleTest,
667 (read3X4(CRTCModuleTest) & 0xDF) | ((base & 0x10000) >> 11));
668 write3X4(CRTHiOrd,
669 (read3X4(CRTHiOrd) & 0xF8) | ((base & 0xE0000) >> 17));
670 }
671
672 /* Use 20.12 fixed-point for NTSC value and frequency calculation */
673 #define calc_freq(n, m, k) ( ((unsigned long)0xE517 * (n + 8) / ((m + 2) * (1 << k))) >> 12 )
674
675 /* Set dotclock frequency */
676 static void set_vclk(int freq)
677 {
678 int m, n, k;
679 int f, fi, d, di;
680 unsigned char lo = 0, hi = 0;
681
682 d = 20;
683 for (k = 2; k >= 0; k--)
684 for (m = 0; m < 63; m++)
685 for (n = 0; n < 128; n++) {
686 fi = calc_freq(n, m, k);
687 if ((di = abs(fi - freq)) < d) {
688 d = di;
689 f = fi;
690 lo = n;
691 hi = (k << 6) | m;
692 }
693 }
694 if (chip3D) {
695 write3C4(ClockHigh, hi);
696 write3C4(ClockLow, lo);
697 } else {
698 outb(lo, 0x43C8);
699 outb(hi, 0x43C9);
700 }
701 debug("VCLK = %X %X\n", hi, lo);
702 }
703
704 /* Set number of lines for flat panels*/
705 static void set_number_of_lines(int lines)
706 {
707 int tmp = read3CE(CyberEnhance) & 0x8F;
708 if (lines > 1024)
709 tmp |= 0x50;
710 else if (lines > 768)
711 tmp |= 0x30;
712 else if (lines > 600)
713 tmp |= 0x20;
714 else if (lines > 480)
715 tmp |= 0x10;
716 write3CE(CyberEnhance, tmp);
717 }
718
719 /*
720 * If we see that FP is active we assume we have one.
721 * Otherwise we have a CRT display.User can override.
722 */
723 static unsigned int __devinit get_displaytype(void)
724 {
725 if (fp)
726 return DISPLAY_FP;
727 if (crt || !chipcyber)
728 return DISPLAY_CRT;
729 return (read3CE(FPConfig) & 0x10) ? DISPLAY_FP : DISPLAY_CRT;
730 }
731
732 /* Try detecting the video memory size */
733 static unsigned int __devinit get_memsize(void)
734 {
735 unsigned char tmp, tmp2;
736 unsigned int k;
737
738 /* If memory size provided by user */
739 if (memsize)
740 k = memsize * Kb;
741 else
742 switch (chip_id) {
743 case CYBER9525DVD:
744 k = 2560 * Kb;
745 break;
746 default:
747 tmp = read3X4(SPR) & 0x0F;
748 switch (tmp) {
749
750 case 0x01:
751 k = 512 * Kb;
752 break;
753 case 0x02:
754 k = 6 * Mb; /* XP */
755 break;
756 case 0x03:
757 k = 1 * Mb;
758 break;
759 case 0x04:
760 k = 8 * Mb;
761 break;
762 case 0x06:
763 k = 10 * Mb; /* XP */
764 break;
765 case 0x07:
766 k = 2 * Mb;
767 break;
768 case 0x08:
769 k = 12 * Mb; /* XP */
770 break;
771 case 0x0A:
772 k = 14 * Mb; /* XP */
773 break;
774 case 0x0C:
775 k = 16 * Mb; /* XP */
776 break;
777 case 0x0E: /* XP */
778
779 tmp2 = read3C4(0xC1);
780 switch (tmp2) {
781 case 0x00:
782 k = 20 * Mb;
783 break;
784 case 0x01:
785 k = 24 * Mb;
786 break;
787 case 0x10:
788 k = 28 * Mb;
789 break;
790 case 0x11:
791 k = 32 * Mb;
792 break;
793 default:
794 k = 1 * Mb;
795 break;
796 }
797 break;
798
799 case 0x0F:
800 k = 4 * Mb;
801 break;
802 default:
803 k = 1 * Mb;
804 break;
805 }
806 }
807
808 k -= memdiff * Kb;
809 output("framebuffer size = %d Kb\n", k / Kb);
810 return k;
811 }
812
813 /* See if we can handle the video mode described in var */
814 static int tridentfb_check_var(struct fb_var_screeninfo *var,
815 struct fb_info *info)
816 {
817 int bpp = var->bits_per_pixel;
818 debug("enter\n");
819
820 /* check color depth */
821 if (bpp == 24)
822 bpp = var->bits_per_pixel = 32;
823 /* check whether resolution fits on panel and in memory */
824 if (flatpanel && nativex && var->xres > nativex)
825 return -EINVAL;
826 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
827 return -EINVAL;
828
829 switch (bpp) {
830 case 8:
831 var->red.offset = 0;
832 var->green.offset = 0;
833 var->blue.offset = 0;
834 var->red.length = 6;
835 var->green.length = 6;
836 var->blue.length = 6;
837 break;
838 case 16:
839 var->red.offset = 11;
840 var->green.offset = 5;
841 var->blue.offset = 0;
842 var->red.length = 5;
843 var->green.length = 6;
844 var->blue.length = 5;
845 break;
846 case 32:
847 var->red.offset = 16;
848 var->green.offset = 8;
849 var->blue.offset = 0;
850 var->red.length = 8;
851 var->green.length = 8;
852 var->blue.length = 8;
853 break;
854 default:
855 return -EINVAL;
856 }
857 debug("exit\n");
858
859 return 0;
860
861 }
862
863 /* Pan the display */
864 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
865 struct fb_info *info)
866 {
867 unsigned int offset;
868
869 debug("enter\n");
870 offset = (var->xoffset + (var->yoffset * var->xres))
871 * var->bits_per_pixel / 32;
872 info->var.xoffset = var->xoffset;
873 info->var.yoffset = var->yoffset;
874 set_screen_start(offset);
875 debug("exit\n");
876 return 0;
877 }
878
879 #define shadowmode_on() write3CE(CyberControl, read3CE(CyberControl) | 0x81)
880 #define shadowmode_off() write3CE(CyberControl, read3CE(CyberControl) & 0x7E)
881
882 /* Set the hardware to the requested video mode */
883 static int tridentfb_set_par(struct fb_info *info)
884 {
885 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
886 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
887 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
888 struct fb_var_screeninfo *var = &info->var;
889 int bpp = var->bits_per_pixel;
890 unsigned char tmp;
891 debug("enter\n");
892 hdispend = var->xres / 8 - 1;
893 hsyncstart = (var->xres + var->right_margin) / 8;
894 hsyncend = var->hsync_len / 8;
895 htotal =
896 (var->xres + var->left_margin + var->right_margin +
897 var->hsync_len) / 8 - 10;
898 hblankstart = hdispend + 1;
899 hblankend = htotal + 5;
900
901 vdispend = var->yres - 1;
902 vsyncstart = var->yres + var->lower_margin;
903 vsyncend = var->vsync_len;
904 vtotal = var->upper_margin + vsyncstart + vsyncend - 2;
905 vblankstart = var->yres;
906 vblankend = vtotal + 2;
907
908 enable_mmio();
909 crtc_unlock();
910 write3CE(CyberControl, 8);
911
912 if (flatpanel && var->xres < nativex) {
913 /*
914 * on flat panels with native size larger
915 * than requested resolution decide whether
916 * we stretch or center
917 */
918 t_outb(0xEB, 0x3C2);
919
920 shadowmode_on();
921
922 if (center)
923 screen_center();
924 else if (stretch)
925 screen_stretch();
926
927 } else {
928 t_outb(0x2B, 0x3C2);
929 write3CE(CyberControl, 8);
930 }
931
932 /* vertical timing values */
933 write3X4(CRTVTotal, vtotal & 0xFF);
934 write3X4(CRTVDispEnd, vdispend & 0xFF);
935 write3X4(CRTVSyncStart, vsyncstart & 0xFF);
936 write3X4(CRTVSyncEnd, (vsyncend & 0x0F));
937 write3X4(CRTVBlankStart, vblankstart & 0xFF);
938 write3X4(CRTVBlankEnd, 0 /* p->vblankend & 0xFF */ );
939
940 /* horizontal timing values */
941 write3X4(CRTHTotal, htotal & 0xFF);
942 write3X4(CRTHDispEnd, hdispend & 0xFF);
943 write3X4(CRTHSyncStart, hsyncstart & 0xFF);
944 write3X4(CRTHSyncEnd, (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
945 write3X4(CRTHBlankStart, hblankstart & 0xFF);
946 write3X4(CRTHBlankEnd, 0 /* (p->hblankend & 0x1F) */ );
947
948 /* higher bits of vertical timing values */
949 tmp = 0x10;
950 if (vtotal & 0x100) tmp |= 0x01;
951 if (vdispend & 0x100) tmp |= 0x02;
952 if (vsyncstart & 0x100) tmp |= 0x04;
953 if (vblankstart & 0x100) tmp |= 0x08;
954
955 if (vtotal & 0x200) tmp |= 0x20;
956 if (vdispend & 0x200) tmp |= 0x40;
957 if (vsyncstart & 0x200) tmp |= 0x80;
958 write3X4(CRTOverflow, tmp);
959
960 tmp = read3X4(CRTHiOrd) | 0x08; /* line compare bit 10 */
961 if (vtotal & 0x400) tmp |= 0x80;
962 if (vblankstart & 0x400) tmp |= 0x40;
963 if (vsyncstart & 0x400) tmp |= 0x20;
964 if (vdispend & 0x400) tmp |= 0x10;
965 write3X4(CRTHiOrd, tmp);
966
967 tmp = 0;
968 if (htotal & 0x800) tmp |= 0x800 >> 11;
969 if (hblankstart & 0x800) tmp |= 0x800 >> 7;
970 write3X4(HorizOverflow, tmp);
971
972 tmp = 0x40;
973 if (vblankstart & 0x200) tmp |= 0x20;
974 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
975 write3X4(CRTMaxScanLine, tmp);
976
977 write3X4(CRTLineCompare, 0xFF);
978 write3X4(CRTPRowScan, 0);
979 write3X4(CRTModeControl, 0xC3);
980
981 write3X4(LinearAddReg, 0x20); /* enable linear addressing */
982
983 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
984 write3X4(CRTCModuleTest, tmp); /* enable access extended memory */
985
986 write3X4(GraphEngReg, 0x80); /* enable GE for text acceleration */
987
988 #ifdef CONFIG_FB_TRIDENT_ACCEL
989 acc->init_accel(info->var.xres, bpp);
990 #endif
991
992 switch (bpp) {
993 case 8:
994 tmp = 0x00;
995 break;
996 case 16:
997 tmp = 0x05;
998 break;
999 case 24:
1000 tmp = 0x29;
1001 break;
1002 case 32:
1003 tmp = 0x09;
1004 break;
1005 }
1006
1007 write3X4(PixelBusReg, tmp);
1008
1009 tmp = 0x10;
1010 if (chipcyber)
1011 tmp |= 0x20;
1012 write3X4(DRAMControl, tmp); /* both IO, linear enable */
1013
1014 write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
1015 write3X4(Performance, 0x92);
1016 write3X4(PCIReg, 0x07); /* MMIO & PCI read and write burst enable */
1017
1018 /* convert from picoseconds to MHz */
1019 par->vclk = 1000000 / info->var.pixclock;
1020 if (bpp == 32)
1021 par->vclk *= 2;
1022 set_vclk(par->vclk);
1023
1024 write3C4(0, 3);
1025 write3C4(1, 1); /* set char clock 8 dots wide */
1026 write3C4(2, 0x0F); /* enable 4 maps because needed in chain4 mode */
1027 write3C4(3, 0);
1028 write3C4(4, 0x0E); /* memory mode enable bitmaps ?? */
1029
1030 write3CE(MiscExtFunc, (bpp == 32) ? 0x1A : 0x12); /* divide clock by 2 if 32bpp */
1031 /* chain4 mode display and CPU path */
1032 write3CE(0x5, 0x40); /* no CGA compat, allow 256 col */
1033 write3CE(0x6, 0x05); /* graphics mode */
1034 write3CE(0x7, 0x0F); /* planes? */
1035
1036 if (chip_id == CYBERBLADEXPAi1) {
1037 /* This fixes snow-effect in 32 bpp */
1038 write3X4(CRTHSyncStart, 0x84);
1039 }
1040
1041 writeAttr(0x10, 0x41); /* graphics mode and support 256 color modes */
1042 writeAttr(0x12, 0x0F); /* planes */
1043 writeAttr(0x13, 0); /* horizontal pel panning */
1044
1045 /* colors */
1046 for (tmp = 0; tmp < 0x10; tmp++)
1047 writeAttr(tmp, tmp);
1048 readb(par->io_virt + CRT + 0x0A); /* flip-flop to index */
1049 t_outb(0x20, 0x3C0); /* enable attr */
1050
1051 switch (bpp) {
1052 case 8:
1053 tmp = 0;
1054 break;
1055 case 15:
1056 tmp = 0x10;
1057 break;
1058 case 16:
1059 tmp = 0x30;
1060 break;
1061 case 24:
1062 case 32:
1063 tmp = 0xD0;
1064 break;
1065 }
1066
1067 t_inb(0x3C8);
1068 t_inb(0x3C6);
1069 t_inb(0x3C6);
1070 t_inb(0x3C6);
1071 t_inb(0x3C6);
1072 t_outb(tmp, 0x3C6);
1073 t_inb(0x3C8);
1074
1075 if (flatpanel)
1076 set_number_of_lines(info->var.yres);
1077 set_lwidth(info->var.xres * bpp / (4 * 16));
1078 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1079 info->fix.line_length = info->var.xres * (bpp >> 3);
1080 info->cmap.len = (bpp == 8) ? 256 : 16;
1081 debug("exit\n");
1082 return 0;
1083 }
1084
1085 /* Set one color register */
1086 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1087 unsigned blue, unsigned transp,
1088 struct fb_info *info)
1089 {
1090 int bpp = info->var.bits_per_pixel;
1091
1092 if (regno >= info->cmap.len)
1093 return 1;
1094
1095 if (bpp == 8) {
1096 t_outb(0xFF, 0x3C6);
1097 t_outb(regno, 0x3C8);
1098
1099 t_outb(red >> 10, 0x3C9);
1100 t_outb(green >> 10, 0x3C9);
1101 t_outb(blue >> 10, 0x3C9);
1102
1103 } else if (regno < 16) {
1104 if (bpp == 16) { /* RGB 565 */
1105 u32 col;
1106
1107 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1108 ((blue & 0xF800) >> 11);
1109 col |= col << 16;
1110 ((u32 *)(info->pseudo_palette))[regno] = col;
1111 } else if (bpp == 32) /* ARGB 8888 */
1112 ((u32*)info->pseudo_palette)[regno] =
1113 ((transp & 0xFF00) << 16) |
1114 ((red & 0xFF00) << 8) |
1115 ((green & 0xFF00)) |
1116 ((blue & 0xFF00) >> 8);
1117 }
1118
1119 /* debug("exit\n"); */
1120 return 0;
1121 }
1122
1123 /* Try blanking the screen.For flat panels it does nothing */
1124 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1125 {
1126 unsigned char PMCont, DPMSCont;
1127
1128 debug("enter\n");
1129 if (flatpanel)
1130 return 0;
1131 t_outb(0x04, 0x83C8); /* Read DPMS Control */
1132 PMCont = t_inb(0x83C6) & 0xFC;
1133 DPMSCont = read3CE(PowerStatus) & 0xFC;
1134 switch (blank_mode) {
1135 case FB_BLANK_UNBLANK:
1136 /* Screen: On, HSync: On, VSync: On */
1137 case FB_BLANK_NORMAL:
1138 /* Screen: Off, HSync: On, VSync: On */
1139 PMCont |= 0x03;
1140 DPMSCont |= 0x00;
1141 break;
1142 case FB_BLANK_HSYNC_SUSPEND:
1143 /* Screen: Off, HSync: Off, VSync: On */
1144 PMCont |= 0x02;
1145 DPMSCont |= 0x01;
1146 break;
1147 case FB_BLANK_VSYNC_SUSPEND:
1148 /* Screen: Off, HSync: On, VSync: Off */
1149 PMCont |= 0x02;
1150 DPMSCont |= 0x02;
1151 break;
1152 case FB_BLANK_POWERDOWN:
1153 /* Screen: Off, HSync: Off, VSync: Off */
1154 PMCont |= 0x00;
1155 DPMSCont |= 0x03;
1156 break;
1157 }
1158
1159 write3CE(PowerStatus, DPMSCont);
1160 t_outb(4, 0x83C8);
1161 t_outb(PMCont, 0x83C6);
1162
1163 debug("exit\n");
1164
1165 /* let fbcon do a softblank for us */
1166 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1167 }
1168
1169 static struct fb_ops tridentfb_ops = {
1170 .owner = THIS_MODULE,
1171 .fb_setcolreg = tridentfb_setcolreg,
1172 .fb_pan_display = tridentfb_pan_display,
1173 .fb_blank = tridentfb_blank,
1174 .fb_check_var = tridentfb_check_var,
1175 .fb_set_par = tridentfb_set_par,
1176 .fb_fillrect = tridentfb_fillrect,
1177 .fb_copyarea = tridentfb_copyarea,
1178 .fb_imageblit = cfb_imageblit,
1179 };
1180
1181 static int __devinit trident_pci_probe(struct pci_dev * dev,
1182 const struct pci_device_id * id)
1183 {
1184 int err;
1185 unsigned char revision;
1186
1187 err = pci_enable_device(dev);
1188 if (err)
1189 return err;
1190
1191 chip_id = id->device;
1192
1193 if (chip_id == CYBERBLADEi1)
1194 output("*** Please do use cyblafb, Cyberblade/i1 support "
1195 "will soon be removed from tridentfb!\n");
1196
1197
1198 /* If PCI id is 0x9660 then further detect chip type */
1199
1200 if (chip_id == TGUI9660) {
1201 outb(RevisionID, 0x3C4);
1202 revision = inb(0x3C5);
1203
1204 switch (revision) {
1205 case 0x22:
1206 case 0x23:
1207 chip_id = CYBER9397;
1208 break;
1209 case 0x2A:
1210 chip_id = CYBER9397DVD;
1211 break;
1212 case 0x30:
1213 case 0x33:
1214 case 0x34:
1215 case 0x35:
1216 case 0x38:
1217 case 0x3A:
1218 case 0xB3:
1219 chip_id = CYBER9385;
1220 break;
1221 case 0x40 ... 0x43:
1222 chip_id = CYBER9382;
1223 break;
1224 case 0x4A:
1225 chip_id = CYBER9388;
1226 break;
1227 default:
1228 break;
1229 }
1230 }
1231
1232 chip3D = is3Dchip(chip_id);
1233 chipcyber = iscyber(chip_id);
1234
1235 if (is_xp(chip_id)) {
1236 acc = &accel_xp;
1237 } else if (is_blade(chip_id)) {
1238 acc = &accel_blade;
1239 } else {
1240 acc = &accel_image;
1241 }
1242
1243 /* acceleration is on by default for 3D chips */
1244 defaultaccel = chip3D && !noaccel;
1245
1246 fb_info.par = &default_par;
1247
1248 /* setup MMIO region */
1249 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1250 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1251
1252 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1253 debug("request_region failed!\n");
1254 return -1;
1255 }
1256
1257 default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1258
1259 if (!default_par.io_virt) {
1260 debug("ioremap failed\n");
1261 err = -1;
1262 goto out_unmap1;
1263 }
1264
1265 enable_mmio();
1266
1267 /* setup framebuffer memory */
1268 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1269 tridentfb_fix.smem_len = get_memsize();
1270
1271 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1272 debug("request_mem_region failed!\n");
1273 disable_mmio();
1274 err = -1;
1275 goto out_unmap1;
1276 }
1277
1278 fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1279 tridentfb_fix.smem_len);
1280
1281 if (!fb_info.screen_base) {
1282 debug("ioremap failed\n");
1283 err = -1;
1284 goto out_unmap2;
1285 }
1286
1287 output("%s board found\n", pci_name(dev));
1288 displaytype = get_displaytype();
1289
1290 if (flatpanel)
1291 nativex = get_nativex();
1292
1293 fb_info.fix = tridentfb_fix;
1294 fb_info.fbops = &tridentfb_ops;
1295
1296
1297 fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1298 #ifdef CONFIG_FB_TRIDENT_ACCEL
1299 fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1300 #endif
1301 fb_info.pseudo_palette = pseudo_pal;
1302
1303 if (!fb_find_mode(&default_var, &fb_info,
1304 mode_option, NULL, 0, NULL, bpp)) {
1305 err = -EINVAL;
1306 goto out_unmap2;
1307 }
1308 err = fb_alloc_cmap(&fb_info.cmap, 256, 0);
1309 if (err < 0)
1310 goto out_unmap2;
1311
1312 if (defaultaccel && acc)
1313 default_var.accel_flags |= FB_ACCELF_TEXT;
1314 else
1315 default_var.accel_flags &= ~FB_ACCELF_TEXT;
1316 default_var.activate |= FB_ACTIVATE_NOW;
1317 fb_info.var = default_var;
1318 fb_info.device = &dev->dev;
1319 if (register_framebuffer(&fb_info) < 0) {
1320 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1321 fb_dealloc_cmap(&fb_info.cmap);
1322 err = -EINVAL;
1323 goto out_unmap2;
1324 }
1325 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1326 fb_info.node, fb_info.fix.id, default_var.xres,
1327 default_var.yres, default_var.bits_per_pixel);
1328 return 0;
1329
1330 out_unmap2:
1331 if (fb_info.screen_base)
1332 iounmap(fb_info.screen_base);
1333 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1334 disable_mmio();
1335 out_unmap1:
1336 if (default_par.io_virt)
1337 iounmap(default_par.io_virt);
1338 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1339 return err;
1340 }
1341
1342 static void __devexit trident_pci_remove(struct pci_dev *dev)
1343 {
1344 struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par;
1345 unregister_framebuffer(&fb_info);
1346 iounmap(par->io_virt);
1347 iounmap(fb_info.screen_base);
1348 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1349 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1350 }
1351
1352 /* List of boards that we are trying to support */
1353 static struct pci_device_id trident_devices[] = {
1354 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1355 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1356 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1357 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1358 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1359 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1360 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1361 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1362 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1363 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1364 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1365 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1366 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1367 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1368 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1369 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1370 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1371 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1372 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1373 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1374 {0,}
1375 };
1376
1377 MODULE_DEVICE_TABLE(pci, trident_devices);
1378
1379 static struct pci_driver tridentfb_pci_driver = {
1380 .name = "tridentfb",
1381 .id_table = trident_devices,
1382 .probe = trident_pci_probe,
1383 .remove = __devexit_p(trident_pci_remove)
1384 };
1385
1386 /*
1387 * Parse user specified options (`video=trident:')
1388 * example:
1389 * video=trident:800x600,bpp=16,noaccel
1390 */
1391 #ifndef MODULE
1392 static int __init tridentfb_setup(char *options)
1393 {
1394 char *opt;
1395 if (!options || !*options)
1396 return 0;
1397 while ((opt = strsep(&options, ",")) != NULL) {
1398 if (!*opt)
1399 continue;
1400 if (!strncmp(opt, "noaccel", 7))
1401 noaccel = 1;
1402 else if (!strncmp(opt, "fp", 2))
1403 displaytype = DISPLAY_FP;
1404 else if (!strncmp(opt, "crt", 3))
1405 displaytype = DISPLAY_CRT;
1406 else if (!strncmp(opt, "bpp=", 4))
1407 bpp = simple_strtoul(opt + 4, NULL, 0);
1408 else if (!strncmp(opt, "center", 6))
1409 center = 1;
1410 else if (!strncmp(opt, "stretch", 7))
1411 stretch = 1;
1412 else if (!strncmp(opt, "memsize=", 8))
1413 memsize = simple_strtoul(opt + 8, NULL, 0);
1414 else if (!strncmp(opt, "memdiff=", 8))
1415 memdiff = simple_strtoul(opt + 8, NULL, 0);
1416 else if (!strncmp(opt, "nativex=", 8))
1417 nativex = simple_strtoul(opt + 8, NULL, 0);
1418 else
1419 mode_option = opt;
1420 }
1421 return 0;
1422 }
1423 #endif
1424
1425 static int __init tridentfb_init(void)
1426 {
1427 #ifndef MODULE
1428 char *option = NULL;
1429
1430 if (fb_get_options("tridentfb", &option))
1431 return -ENODEV;
1432 tridentfb_setup(option);
1433 #endif
1434 output("Trident framebuffer %s initializing\n", VERSION);
1435 return pci_register_driver(&tridentfb_pci_driver);
1436 }
1437
1438 static void __exit tridentfb_exit(void)
1439 {
1440 pci_unregister_driver(&tridentfb_pci_driver);
1441 }
1442
1443 module_init(tridentfb_init);
1444 module_exit(tridentfb_exit);
1445
1446 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1447 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1448 MODULE_LICENSE("GPL");
1449
linux 2.6 git repository for openrd