drivers/net/sfc/net_driver.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 /* Common definitions for all Efx net driver code */
  12
  13 #ifndef EFX_NET_DRIVER_H
  14 #define EFX_NET_DRIVER_H
  15
  16 #include <linux/version.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/timer.h>
  22 #include <linux/mdio.h>
  23 #include <linux/list.h>
  24 #include <linux/pci.h>
  25 #include <linux/device.h>
  26 #include <linux/highmem.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/i2c.h>
  29
  30 #include "enum.h"
  31 #include "bitfield.h"
  32
  33 /**************************************************************************
  34  *
  35  * Build definitions
  36  *
  37  **************************************************************************/
  38 #ifndef EFX_DRIVER_NAME
  39 #define EFX_DRIVER_NAME "sfc"
  40 #endif
  41 #define EFX_DRIVER_VERSION      "2.3"
  42
  43 #ifdef EFX_ENABLE_DEBUG
  44 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  45 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  46 #else
  47 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  48 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  49 #endif
  50
  51 /* Un-rate-limited logging */
  52 #define EFX_ERR(efx, fmt, args...) \
  53 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
  54
  55 #define EFX_INFO(efx, fmt, args...) \
  56 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
  57
  58 #ifdef EFX_ENABLE_DEBUG
  59 #define EFX_LOG(efx, fmt, args...) \
  60 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
  61 #else
  62 #define EFX_LOG(efx, fmt, args...) \
  63 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
  64 #endif
  65
  66 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
  67
  68 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
  69
  70 /* Rate-limited logging */
  71 #define EFX_ERR_RL(efx, fmt, args...) \
  72 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
  73
  74 #define EFX_INFO_RL(efx, fmt, args...) \
  75 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
  76
  77 #define EFX_LOG_RL(efx, fmt, args...) \
  78 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
  79
  80 /**************************************************************************
  81  *
  82  * Efx data structures
  83  *
  84  **************************************************************************/
  85
  86 #define EFX_MAX_CHANNELS 32
  87 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
  88
  89 #define EFX_TX_QUEUE_OFFLOAD_CSUM       0
  90 #define EFX_TX_QUEUE_NO_CSUM            1
  91 #define EFX_TX_QUEUE_COUNT              2
  92
  93 /**
  94  * struct efx_special_buffer - An Efx special buffer
  95  * @addr: CPU base address of the buffer
  96  * @dma_addr: DMA base address of the buffer
  97  * @len: Buffer length, in bytes
  98  * @index: Buffer index within controller;s buffer table
  99  * @entries: Number of buffer table entries
 100  *
 101  * Special buffers are used for the event queues and the TX and RX
 102  * descriptor queues for each channel.  They are *not* used for the
 103  * actual transmit and receive buffers.
 104  *
 105  * Note that for Falcon, TX and RX descriptor queues live in host memory.
 106  * Allocation and freeing procedures must take this into account.
 107  */
 108 struct efx_special_buffer {
 109         void *addr;
 110         dma_addr_t dma_addr;
 111         unsigned int len;
 112         int index;
 113         int entries;
 114 };
 115
 116 enum efx_flush_state {
 117         FLUSH_NONE,
 118         FLUSH_PENDING,
 119         FLUSH_FAILED,
 120         FLUSH_DONE,
 121 };
 122
 123 /**
 124  * struct efx_tx_buffer - An Efx TX buffer
 125  * @skb: The associated socket buffer.
 126  *      Set only on the final fragment of a packet; %NULL for all other
 127  *      fragments.  When this fragment completes, then we can free this
 128  *      skb.
 129  * @tsoh: The associated TSO header structure, or %NULL if this
 130  *      buffer is not a TSO header.
 131  * @dma_addr: DMA address of the fragment.
 132  * @len: Length of this fragment.
 133  *      This field is zero when the queue slot is empty.
 134  * @continuation: True if this fragment is not the end of a packet.
 135  * @unmap_single: True if pci_unmap_single should be used.
 136  * @unmap_len: Length of this fragment to unmap
 137  */
 138 struct efx_tx_buffer {
 139         const struct sk_buff *skb;
 140         struct efx_tso_header *tsoh;
 141         dma_addr_t dma_addr;
 142         unsigned short len;
 143         bool continuation;
 144         bool unmap_single;
 145         unsigned short unmap_len;
 146 };
 147
 148 /**
 149  * struct efx_tx_queue - An Efx TX queue
 150  *
 151  * This is a ring buffer of TX fragments.
 152  * Since the TX completion path always executes on the same
 153  * CPU and the xmit path can operate on different CPUs,
 154  * performance is increased by ensuring that the completion
 155  * path and the xmit path operate on different cache lines.
 156  * This is particularly important if the xmit path is always
 157  * executing on one CPU which is different from the completion
 158  * path.  There is also a cache line for members which are
 159  * read but not written on the fast path.
 160  *
 161  * @efx: The associated Efx NIC
 162  * @queue: DMA queue number
 163  * @channel: The associated channel
 164  * @buffer: The software buffer ring
 165  * @txd: The hardware descriptor ring
 166  * @flushed: Used when handling queue flushing
 167  * @read_count: Current read pointer.
 168  *      This is the number of buffers that have been removed from both rings.
 169  * @stopped: Stopped count.
 170  *      Set if this TX queue is currently stopping its port.
 171  * @insert_count: Current insert pointer
 172  *      This is the number of buffers that have been added to the
 173  *      software ring.
 174  * @write_count: Current write pointer
 175  *      This is the number of buffers that have been added to the
 176  *      hardware ring.
 177  * @old_read_count: The value of read_count when last checked.
 178  *      This is here for performance reasons.  The xmit path will
 179  *      only get the up-to-date value of read_count if this
 180  *      variable indicates that the queue is full.  This is to
 181  *      avoid cache-line ping-pong between the xmit path and the
 182  *      completion path.
 183  * @tso_headers_free: A list of TSO headers allocated for this TX queue
 184  *      that are not in use, and so available for new TSO sends. The list
 185  *      is protected by the TX queue lock.
 186  * @tso_bursts: Number of times TSO xmit invoked by kernel
 187  * @tso_long_headers: Number of packets with headers too long for standard
 188  *      blocks
 189  * @tso_packets: Number of packets via the TSO xmit path
 190  */
 191 struct efx_tx_queue {
 192         /* Members which don't change on the fast path */
 193         struct efx_nic *efx ____cacheline_aligned_in_smp;
 194         int queue;
 195         struct efx_channel *channel;
 196         struct efx_nic *nic;
 197         struct efx_tx_buffer *buffer;
 198         struct efx_special_buffer txd;
 199         enum efx_flush_state flushed;
 200
 201         /* Members used mainly on the completion path */
 202         unsigned int read_count ____cacheline_aligned_in_smp;
 203         int stopped;
 204
 205         /* Members used only on the xmit path */
 206         unsigned int insert_count ____cacheline_aligned_in_smp;
 207         unsigned int write_count;
 208         unsigned int old_read_count;
 209         struct efx_tso_header *tso_headers_free;
 210         unsigned int tso_bursts;
 211         unsigned int tso_long_headers;
 212         unsigned int tso_packets;
 213 };
 214
 215 /**
 216  * struct efx_rx_buffer - An Efx RX data buffer
 217  * @dma_addr: DMA base address of the buffer
 218  * @skb: The associated socket buffer, if any.
 219  *      If both this and page are %NULL, the buffer slot is currently free.
 220  * @page: The associated page buffer, if any.
 221  *      If both this and skb are %NULL, the buffer slot is currently free.
 222  * @data: Pointer to ethernet header
 223  * @len: Buffer length, in bytes.
 224  * @unmap_addr: DMA address to unmap
 225  */
 226 struct efx_rx_buffer {
 227         dma_addr_t dma_addr;
 228         struct sk_buff *skb;
 229         struct page *page;
 230         char *data;
 231         unsigned int len;
 232         dma_addr_t unmap_addr;
 233 };
 234
 235 /**
 236  * struct efx_rx_queue - An Efx RX queue
 237  * @efx: The associated Efx NIC
 238  * @queue: DMA queue number
 239  * @channel: The associated channel
 240  * @buffer: The software buffer ring
 241  * @rxd: The hardware descriptor ring
 242  * @added_count: Number of buffers added to the receive queue.
 243  * @notified_count: Number of buffers given to NIC (<= @added_count).
 244  * @removed_count: Number of buffers removed from the receive queue.
 245  * @add_lock: Receive queue descriptor add spin lock.
 246  *      This lock must be held in order to add buffers to the RX
 247  *      descriptor ring (rxd and buffer) and to update added_count (but
 248  *      not removed_count).
 249  * @max_fill: RX descriptor maximum fill level (<= ring size)
 250  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
 251  *      (<= @max_fill)
 252  * @fast_fill_limit: The level to which a fast fill will fill
 253  *      (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
 254  * @min_fill: RX descriptor minimum non-zero fill level.
 255  *      This records the minimum fill level observed when a ring
 256  *      refill was triggered.
 257  * @min_overfill: RX descriptor minimum overflow fill level.
 258  *      This records the minimum fill level at which RX queue
 259  *      overflow was observed.  It should never be set.
 260  * @alloc_page_count: RX allocation strategy counter.
 261  * @alloc_skb_count: RX allocation strategy counter.
 262  * @work: Descriptor push work thread
 263  * @buf_page: Page for next RX buffer.
 264  *      We can use a single page for multiple RX buffers. This tracks
 265  *      the remaining space in the allocation.
 266  * @buf_dma_addr: Page's DMA address.
 267  * @buf_data: Page's host address.
 268  * @flushed: Use when handling queue flushing
 269  */
 270 struct efx_rx_queue {
 271         struct efx_nic *efx;
 272         int queue;
 273         struct efx_channel *channel;
 274         struct efx_rx_buffer *buffer;
 275         struct efx_special_buffer rxd;
 276
 277         int added_count;
 278         int notified_count;
 279         int removed_count;
 280         spinlock_t add_lock;
 281         unsigned int max_fill;
 282         unsigned int fast_fill_trigger;
 283         unsigned int fast_fill_limit;
 284         unsigned int min_fill;
 285         unsigned int min_overfill;
 286         unsigned int alloc_page_count;
 287         unsigned int alloc_skb_count;
 288         struct delayed_work work;
 289         unsigned int slow_fill_count;
 290
 291         struct page *buf_page;
 292         dma_addr_t buf_dma_addr;
 293         char *buf_data;
 294         enum efx_flush_state flushed;
 295 };
 296
 297 /**
 298  * struct efx_buffer - An Efx general-purpose buffer
 299  * @addr: host base address of the buffer
 300  * @dma_addr: DMA base address of the buffer
 301  * @len: Buffer length, in bytes
 302  *
 303  * Falcon uses these buffers for its interrupt status registers and
 304  * MAC stats dumps.
 305  */
 306 struct efx_buffer {
 307         void *addr;
 308         dma_addr_t dma_addr;
 309         unsigned int len;
 310 };
 311
 312
 313 /* Flags for channel->used_flags */
 314 #define EFX_USED_BY_RX 1
 315 #define EFX_USED_BY_TX 2
 316 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
 317
 318 enum efx_rx_alloc_method {
 319         RX_ALLOC_METHOD_AUTO = 0,
 320         RX_ALLOC_METHOD_SKB = 1,
 321         RX_ALLOC_METHOD_PAGE = 2,
 322 };
 323
 324 /**
 325  * struct efx_channel - An Efx channel
 326  *
 327  * A channel comprises an event queue, at least one TX queue, at least
 328  * one RX queue, and an associated tasklet for processing the event
 329  * queue.
 330  *
 331  * @efx: Associated Efx NIC
 332  * @channel: Channel instance number
 333  * @name: Name for channel and IRQ
 334  * @used_flags: Channel is used by net driver
 335  * @enabled: Channel enabled indicator
 336  * @irq: IRQ number (MSI and MSI-X only)
 337  * @irq_moderation: IRQ moderation value (in hardware ticks)
 338  * @napi_dev: Net device used with NAPI
 339  * @napi_str: NAPI control structure
 340  * @reset_work: Scheduled reset work thread
 341  * @work_pending: Is work pending via NAPI?
 342  * @eventq: Event queue buffer
 343  * @eventq_read_ptr: Event queue read pointer
 344  * @last_eventq_read_ptr: Last event queue read pointer value.
 345  * @eventq_magic: Event queue magic value for driver-generated test events
 346  * @irq_count: Number of IRQs since last adaptive moderation decision
 347  * @irq_mod_score: IRQ moderation score
 348  * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
 349  *      and diagnostic counters
 350  * @rx_alloc_push_pages: RX allocation method currently in use for pushing
 351  *      descriptors
 352  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
 353  * @n_rx_ip_frag_err: Count of RX IP fragment errors
 354  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
 355  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
 356  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
 357  * @n_rx_overlength: Count of RX_OVERLENGTH errors
 358  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
 359  */
 360 struct efx_channel {
 361         struct efx_nic *efx;
 362         int channel;
 363         char name[IFNAMSIZ + 6];
 364         int used_flags;
 365         bool enabled;
 366         int irq;
 367         unsigned int irq_moderation;
 368         struct net_device *napi_dev;
 369         struct napi_struct napi_str;
 370         bool work_pending;
 371         struct efx_special_buffer eventq;
 372         unsigned int eventq_read_ptr;
 373         unsigned int last_eventq_read_ptr;
 374         unsigned int eventq_magic;
 375
 376         unsigned int irq_count;
 377         unsigned int irq_mod_score;
 378
 379         int rx_alloc_level;
 380         int rx_alloc_push_pages;
 381
 382         unsigned n_rx_tobe_disc;
 383         unsigned n_rx_ip_frag_err;
 384         unsigned n_rx_ip_hdr_chksum_err;
 385         unsigned n_rx_tcp_udp_chksum_err;
 386         unsigned n_rx_frm_trunc;
 387         unsigned n_rx_overlength;
 388         unsigned n_skbuff_leaks;
 389
 390         /* Used to pipeline received packets in order to optimise memory
 391          * access with prefetches.
 392          */
 393         struct efx_rx_buffer *rx_pkt;
 394         bool rx_pkt_csummed;
 395
 396 };
 397
 398 enum efx_led_mode {
 399         EFX_LED_OFF     = 0,
 400         EFX_LED_ON      = 1,
 401         EFX_LED_DEFAULT = 2
 402 };
 403
 404 #define STRING_TABLE_LOOKUP(val, member) \
 405         ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
 406
 407 extern const char *efx_loopback_mode_names[];
 408 extern const unsigned int efx_loopback_mode_max;
 409 #define LOOPBACK_MODE(efx) \
 410         STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
 411
 412 extern const char *efx_interrupt_mode_names[];
 413 extern const unsigned int efx_interrupt_mode_max;
 414 #define INT_MODE(efx) \
 415         STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode)
 416
 417 extern const char *efx_reset_type_names[];
 418 extern const unsigned int efx_reset_type_max;
 419 #define RESET_TYPE(type) \
 420         STRING_TABLE_LOOKUP(type, efx_reset_type)
 421
 422 enum efx_int_mode {
 423         /* Be careful if altering to correct macro below */
 424         EFX_INT_MODE_MSIX = 0,
 425         EFX_INT_MODE_MSI = 1,
 426         EFX_INT_MODE_LEGACY = 2,
 427         EFX_INT_MODE_MAX        /* Insert any new items before this */
 428 };
 429 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
 430
 431 enum phy_type {
 432         PHY_TYPE_NONE = 0,
 433         PHY_TYPE_TXC43128 = 1,
 434         PHY_TYPE_88E1111 = 2,
 435         PHY_TYPE_SFX7101 = 3,
 436         PHY_TYPE_QT2022C2 = 4,
 437         PHY_TYPE_PM8358 = 6,
 438         PHY_TYPE_SFT9001A = 8,
 439         PHY_TYPE_QT2025C = 9,
 440         PHY_TYPE_SFT9001B = 10,
 441         PHY_TYPE_MAX    /* Insert any new items before this */
 442 };
 443
 444 #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
 445
 446 enum nic_state {
 447         STATE_INIT = 0,
 448         STATE_RUNNING = 1,
 449         STATE_FINI = 2,
 450         STATE_DISABLED = 3,
 451         STATE_MAX,
 452 };
 453
 454 /*
 455  * Alignment of page-allocated RX buffers
 456  *
 457  * Controls the number of bytes inserted at the start of an RX buffer.
 458  * This is the equivalent of NET_IP_ALIGN [which controls the alignment
 459  * of the skb->head for hardware DMA].
 460  */
 461 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 462 #define EFX_PAGE_IP_ALIGN 0
 463 #else
 464 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
 465 #endif
 466
 467 /*
 468  * Alignment of the skb->head which wraps a page-allocated RX buffer
 469  *
 470  * The skb allocated to wrap an rx_buffer can have this alignment. Since
 471  * the data is memcpy'd from the rx_buf, it does not need to be equal to
 472  * EFX_PAGE_IP_ALIGN.
 473  */
 474 #define EFX_PAGE_SKB_ALIGN 2
 475
 476 /* Forward declaration */
 477 struct efx_nic;
 478
 479 /* Pseudo bit-mask flow control field */
 480 enum efx_fc_type {
 481         EFX_FC_RX = FLOW_CTRL_RX,
 482         EFX_FC_TX = FLOW_CTRL_TX,
 483         EFX_FC_AUTO = 4,
 484 };
 485
 486 /* Supported MAC bit-mask */
 487 enum efx_mac_type {
 488         EFX_GMAC = 1,
 489         EFX_XMAC = 2,
 490 };
 491
 492 /**
 493  * struct efx_link_state - Current state of the link
 494  * @up: Link is up
 495  * @fd: Link is full-duplex
 496  * @fc: Actual flow control flags
 497  * @speed: Link speed (Mbps)
 498  */
 499 struct efx_link_state {
 500         bool up;
 501         bool fd;
 502         enum efx_fc_type fc;
 503         unsigned int speed;
 504 };
 505
 506 /**
 507  * struct efx_mac_operations - Efx MAC operations table
 508  * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
 509  * @update_stats: Update statistics
 510  * @irq: Hardware MAC event callback. Serialised by the mac_lock
 511  * @poll: Poll for hardware state. Serialised by the mac_lock
 512  */
 513 struct efx_mac_operations {
 514         void (*reconfigure) (struct efx_nic *efx);
 515         void (*update_stats) (struct efx_nic *efx);
 516         void (*irq) (struct efx_nic *efx);
 517         void (*poll) (struct efx_nic *efx);
 518 };
 519
 520 /**
 521  * struct efx_phy_operations - Efx PHY operations table
 522  * @init: Initialise PHY
 523  * @fini: Shut down PHY
 524  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
 525  * @clear_interrupt: Clear down interrupt
 526  * @poll: Poll for hardware state. Serialised by the mac_lock.
 527  * @get_settings: Get ethtool settings. Serialised by the mac_lock.
 528  * @set_settings: Set ethtool settings. Serialised by the mac_lock.
 529  * @set_npage_adv: Set abilities advertised in (Extended) Next Page
 530  *      (only needed where AN bit is set in mmds)
 531  * @num_tests: Number of PHY-specific tests/results
 532  * @test_names: Names of the tests/results
 533  * @run_tests: Run tests and record results as appropriate.
 534  *      Flags are the ethtool tests flags.
 535  * @mmds: MMD presence mask
 536  * @loopbacks: Supported loopback modes mask
 537  */
 538 struct efx_phy_operations {
 539         enum efx_mac_type macs;
 540         int (*init) (struct efx_nic *efx);
 541         void (*fini) (struct efx_nic *efx);
 542         void (*reconfigure) (struct efx_nic *efx);
 543         void (*clear_interrupt) (struct efx_nic *efx);
 544         void (*poll) (struct efx_nic *efx);
 545         void (*get_settings) (struct efx_nic *efx,
 546                               struct ethtool_cmd *ecmd);
 547         int (*set_settings) (struct efx_nic *efx,
 548                              struct ethtool_cmd *ecmd);
 549         void (*set_npage_adv) (struct efx_nic *efx, u32);
 550         u32 num_tests;
 551         const char *const *test_names;
 552         int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
 553         int mmds;
 554         unsigned loopbacks;
 555 };
 556
 557 /**
 558  * @enum efx_phy_mode - PHY operating mode flags
 559  * @PHY_MODE_NORMAL: on and should pass traffic
 560  * @PHY_MODE_TX_DISABLED: on with TX disabled
 561  * @PHY_MODE_LOW_POWER: set to low power through MDIO
 562  * @PHY_MODE_OFF: switched off through external control
 563  * @PHY_MODE_SPECIAL: on but will not pass traffic
 564  */
 565 enum efx_phy_mode {
 566         PHY_MODE_NORMAL         = 0,
 567         PHY_MODE_TX_DISABLED    = 1,
 568         PHY_MODE_LOW_POWER      = 2,
 569         PHY_MODE_OFF            = 4,
 570         PHY_MODE_SPECIAL        = 8,
 571 };
 572
 573 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
 574 {
 575         return !!(mode & ~PHY_MODE_TX_DISABLED);
 576 }
 577
 578 /*
 579  * Efx extended statistics
 580  *
 581  * Not all statistics are provided by all supported MACs.  The purpose
 582  * is this structure is to contain the raw statistics provided by each
 583  * MAC.
 584  */
 585 struct efx_mac_stats {
 586         u64 tx_bytes;
 587         u64 tx_good_bytes;
 588         u64 tx_bad_bytes;
 589         unsigned long tx_packets;
 590         unsigned long tx_bad;
 591         unsigned long tx_pause;
 592         unsigned long tx_control;
 593         unsigned long tx_unicast;
 594         unsigned long tx_multicast;
 595         unsigned long tx_broadcast;
 596         unsigned long tx_lt64;
 597         unsigned long tx_64;
 598         unsigned long tx_65_to_127;
 599         unsigned long tx_128_to_255;
 600         unsigned long tx_256_to_511;
 601         unsigned long tx_512_to_1023;
 602         unsigned long tx_1024_to_15xx;
 603         unsigned long tx_15xx_to_jumbo;
 604         unsigned long tx_gtjumbo;
 605         unsigned long tx_collision;
 606         unsigned long tx_single_collision;
 607         unsigned long tx_multiple_collision;
 608         unsigned long tx_excessive_collision;
 609         unsigned long tx_deferred;
 610         unsigned long tx_late_collision;
 611         unsigned long tx_excessive_deferred;
 612         unsigned long tx_non_tcpudp;
 613         unsigned long tx_mac_src_error;
 614         unsigned long tx_ip_src_error;
 615         u64 rx_bytes;
 616         u64 rx_good_bytes;
 617         u64 rx_bad_bytes;
 618         unsigned long rx_packets;
 619         unsigned long rx_good;
 620         unsigned long rx_bad;
 621         unsigned long rx_pause;
 622         unsigned long rx_control;
 623         unsigned long rx_unicast;
 624         unsigned long rx_multicast;
 625         unsigned long rx_broadcast;
 626         unsigned long rx_lt64;
 627         unsigned long rx_64;
 628         unsigned long rx_65_to_127;
 629         unsigned long rx_128_to_255;
 630         unsigned long rx_256_to_511;
 631         unsigned long rx_512_to_1023;
 632         unsigned long rx_1024_to_15xx;
 633         unsigned long rx_15xx_to_jumbo;
 634         unsigned long rx_gtjumbo;
 635         unsigned long rx_bad_lt64;
 636         unsigned long rx_bad_64_to_15xx;
 637         unsigned long rx_bad_15xx_to_jumbo;
 638         unsigned long rx_bad_gtjumbo;
 639         unsigned long rx_overflow;
 640         unsigned long rx_missed;
 641         unsigned long rx_false_carrier;
 642         unsigned long rx_symbol_error;
 643         unsigned long rx_align_error;
 644         unsigned long rx_length_error;
 645         unsigned long rx_internal_error;
 646         unsigned long rx_good_lt64;
 647 };
 648
 649 /* Number of bits used in a multicast filter hash address */
 650 #define EFX_MCAST_HASH_BITS 8
 651
 652 /* Number of (single-bit) entries in a multicast filter hash */
 653 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
 654
 655 /* An Efx multicast filter hash */
 656 union efx_multicast_hash {
 657         u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
 658         efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
 659 };
 660
 661 /**
 662  * struct efx_nic - an Efx NIC
 663  * @name: Device name (net device name or bus id before net device registered)
 664  * @pci_dev: The PCI device
 665  * @type: Controller type attributes
 666  * @legacy_irq: IRQ number
 667  * @workqueue: Workqueue for port reconfigures and the HW monitor.
 668  *      Work items do not hold and must not acquire RTNL.
 669  * @workqueue_name: Name of workqueue
 670  * @reset_work: Scheduled reset workitem
 671  * @monitor_work: Hardware monitor workitem
 672  * @membase_phys: Memory BAR value as physical address
 673  * @membase: Memory BAR value
 674  * @biu_lock: BIU (bus interface unit) lock
 675  * @interrupt_mode: Interrupt mode
 676  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
 677  * @irq_rx_moderation: IRQ moderation time for RX event queues
 678  * @state: Device state flag. Serialised by the rtnl_lock.
 679  * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
 680  * @tx_queue: TX DMA queues
 681  * @rx_queue: RX DMA queues
 682  * @channel: Channels
 683  * @next_buffer_table: First available buffer table id
 684  * @n_rx_queues: Number of RX queues
 685  * @n_channels: Number of channels in use
 686  * @rx_buffer_len: RX buffer length
 687  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
 688  * @int_error_count: Number of internal errors seen recently
 689  * @int_error_expire: Time at which error count will be expired
 690  * @irq_status: Interrupt status buffer
 691  * @last_irq_cpu: Last CPU to handle interrupt.
 692  *      This register is written with the SMP processor ID whenever an
 693  *      interrupt is handled.  It is used by falcon_test_interrupt()
 694  *      to verify that an interrupt has occurred.
 695  * @spi_flash: SPI flash device
 696  *      This field will be %NULL if no flash device is present.
 697  * @spi_eeprom: SPI EEPROM device
 698  *      This field will be %NULL if no EEPROM device is present.
 699  * @spi_lock: SPI bus lock
 700  * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
 701  * @nic_data: Hardware dependant state
 702  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
 703  *      @port_inhibited, efx_monitor() and efx_reconfigure_port()
 704  * @port_enabled: Port enabled indicator.
 705  *      Serialises efx_stop_all(), efx_start_all(), efx_monitor(),
 706  *      efx_phy_work(), and efx_mac_work() with kernel interfaces. Safe to read
 707  *      under any one of the rtnl_lock, mac_lock, or netif_tx_lock, but all
 708  *      three must be held to modify it.
 709  * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
 710  * @port_initialized: Port initialized?
 711  * @net_dev: Operating system network device. Consider holding the rtnl lock
 712  * @rx_checksum_enabled: RX checksumming enabled
 713  * @netif_stop_count: Port stop count
 714  * @netif_stop_lock: Port stop lock
 715  * @mac_stats: MAC statistics. These include all statistics the MACs
 716  *      can provide.  Generic code converts these into a standard
 717  *      &struct net_device_stats.
 718  * @stats_buffer: DMA buffer for statistics
 719  * @stats_lock: Statistics update lock. Serialises statistics fetches
 720  * @mac_op: MAC interface
 721  * @mac_address: Permanent MAC address
 722  * @phy_type: PHY type
 723  * @phy_lock: PHY access lock
 724  * @phy_op: PHY interface
 725  * @phy_data: PHY private data (including PHY-specific stats)
 726  * @mdio: PHY MDIO interface
 727  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
 728  * @mac_up: MAC link state
 729  * @link_state: Current state of the link
 730  * @n_link_state_changes: Number of times the link has changed state
 731  * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
 732  * @multicast_hash: Multicast hash table
 733  * @wanted_fc: Wanted flow control flags
 734  * @phy_work: work item for dealing with PHY events
 735  * @mac_work: work item for dealing with MAC events
 736  * @loopback_mode: Loopback status
 737  * @loopback_modes: Supported loopback mode bitmask
 738  * @loopback_selftest: Offline self-test private state
 739  *
 740  * The @priv field of the corresponding &struct net_device points to
 741  * this.
 742  */
 743 struct efx_nic {
 744         char name[IFNAMSIZ];
 745         struct pci_dev *pci_dev;
 746         const struct efx_nic_type *type;
 747         int legacy_irq;
 748         struct workqueue_struct *workqueue;
 749         char workqueue_name[16];
 750         struct work_struct reset_work;
 751         struct delayed_work monitor_work;
 752         resource_size_t membase_phys;
 753         void __iomem *membase;
 754         spinlock_t biu_lock;
 755         enum efx_int_mode interrupt_mode;
 756         bool irq_rx_adaptive;
 757         unsigned int irq_rx_moderation;
 758
 759         enum nic_state state;
 760         enum reset_type reset_pending;
 761
 762         struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
 763         struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
 764         struct efx_channel channel[EFX_MAX_CHANNELS];
 765
 766         unsigned next_buffer_table;
 767         int n_rx_queues;
 768         int n_channels;
 769         unsigned int rx_buffer_len;
 770         unsigned int rx_buffer_order;
 771
 772         unsigned int_error_count;
 773         unsigned long int_error_expire;
 774
 775         struct efx_buffer irq_status;
 776         volatile signed int last_irq_cpu;
 777
 778         struct efx_spi_device *spi_flash;
 779         struct efx_spi_device *spi_eeprom;
 780         struct mutex spi_lock;
 781
 782         unsigned n_rx_nodesc_drop_cnt;
 783
 784         struct falcon_nic_data *nic_data;
 785
 786         struct mutex mac_lock;
 787         struct work_struct mac_work;
 788         bool port_enabled;
 789         bool port_inhibited;
 790
 791         bool port_initialized;
 792         struct net_device *net_dev;
 793         bool rx_checksum_enabled;
 794
 795         atomic_t netif_stop_count;
 796         spinlock_t netif_stop_lock;
 797
 798         struct efx_mac_stats mac_stats;
 799         struct efx_buffer stats_buffer;
 800         spinlock_t stats_lock;
 801
 802         struct efx_mac_operations *mac_op;
 803         unsigned char mac_address[ETH_ALEN];
 804
 805         enum phy_type phy_type;
 806         spinlock_t phy_lock;
 807         struct work_struct phy_work;
 808         struct efx_phy_operations *phy_op;
 809         void *phy_data;
 810         struct mdio_if_info mdio;
 811         enum efx_phy_mode phy_mode;
 812
 813         bool mac_up;
 814         struct efx_link_state link_state;
 815         unsigned int n_link_state_changes;
 816
 817         bool promiscuous;
 818         union efx_multicast_hash multicast_hash;
 819         enum efx_fc_type wanted_fc;
 820
 821         atomic_t rx_reset;
 822         enum efx_loopback_mode loopback_mode;
 823         unsigned int loopback_modes;
 824
 825         void *loopback_selftest;
 826 };
 827
 828 static inline int efx_dev_registered(struct efx_nic *efx)
 829 {
 830         return efx->net_dev->reg_state == NETREG_REGISTERED;
 831 }
 832
 833 /* Net device name, for inclusion in log messages if it has been registered.
 834  * Use efx->name not efx->net_dev->name so that races with (un)registration
 835  * are harmless.
 836  */
 837 static inline const char *efx_dev_name(struct efx_nic *efx)
 838 {
 839         return efx_dev_registered(efx) ? efx->name : "";
 840 }
 841
 842 /**
 843  * struct efx_nic_type - Efx device type definition
 844  * @mem_map_size: Memory BAR mapped size
 845  * @txd_ptr_tbl_base: TX descriptor ring base address
 846  * @rxd_ptr_tbl_base: RX descriptor ring base address
 847  * @buf_tbl_base: Buffer table base address
 848  * @evq_ptr_tbl_base: Event queue pointer table base address
 849  * @evq_rptr_tbl_base: Event queue read-pointer table base address
 850  * @max_dma_mask: Maximum possible DMA mask
 851  * @rx_buffer_padding: Padding added to each RX buffer
 852  * @max_interrupt_mode: Highest capability interrupt mode supported
 853  *      from &enum efx_init_mode.
 854  * @phys_addr_channels: Number of channels with physically addressed
 855  *      descriptors
 856  */
 857 struct efx_nic_type {
 858         unsigned int mem_map_size;
 859         unsigned int txd_ptr_tbl_base;
 860         unsigned int rxd_ptr_tbl_base;
 861         unsigned int buf_tbl_base;
 862         unsigned int evq_ptr_tbl_base;
 863         unsigned int evq_rptr_tbl_base;
 864
 865         u64 max_dma_mask;
 866
 867         unsigned int rx_buffer_padding;
 868         unsigned int max_interrupt_mode;
 869         unsigned int phys_addr_channels;
 870 };
 871
 872 /**************************************************************************
 873  *
 874  * Prototypes and inline functions
 875  *
 876  *************************************************************************/
 877
 878 /* Iterate over all used channels */
 879 #define efx_for_each_channel(_channel, _efx)                            \
 880         for (_channel = &_efx->channel[0];                              \
 881              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 882              _channel++)                                                \
 883                 if (!_channel->used_flags)                              \
 884                         continue;                                       \
 885                 else
 886
 887 /* Iterate over all used TX queues */
 888 #define efx_for_each_tx_queue(_tx_queue, _efx)                          \
 889         for (_tx_queue = &_efx->tx_queue[0];                            \
 890              _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT];           \
 891              _tx_queue++)
 892
 893 /* Iterate over all TX queues belonging to a channel */
 894 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)              \
 895         for (_tx_queue = &_channel->efx->tx_queue[0];                   \
 896              _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT];  \
 897              _tx_queue++)                                               \
 898                 if (_tx_queue->channel != _channel)                     \
 899                         continue;                                       \
 900                 else
 901
 902 /* Iterate over all used RX queues */
 903 #define efx_for_each_rx_queue(_rx_queue, _efx)                          \
 904         for (_rx_queue = &_efx->rx_queue[0];                            \
 905              _rx_queue < &_efx->rx_queue[_efx->n_rx_queues];            \
 906              _rx_queue++)
 907
 908 /* Iterate over all RX queues belonging to a channel */
 909 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)              \
 910         for (_rx_queue = &_channel->efx->rx_queue[_channel->channel];   \
 911              _rx_queue;                                                 \
 912              _rx_queue = NULL)                                          \
 913                 if (_rx_queue->channel != _channel)                     \
 914                         continue;                                       \
 915                 else
 916
 917 /* Returns a pointer to the specified receive buffer in the RX
 918  * descriptor queue.
 919  */
 920 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
 921                                                   unsigned int index)
 922 {
 923         return (&rx_queue->buffer[index]);
 924 }
 925
 926 /* Set bit in a little-endian bitfield */
 927 static inline void set_bit_le(unsigned nr, unsigned char *addr)
 928 {
 929         addr[nr / 8] |= (1 << (nr % 8));
 930 }
 931
 932 /* Clear bit in a little-endian bitfield */
 933 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
 934 {
 935         addr[nr / 8] &= ~(1 << (nr % 8));
 936 }
 937
 938
 939 /**
 940  * EFX_MAX_FRAME_LEN - calculate maximum frame length
 941  *
 942  * This calculates the maximum frame length that will be used for a
 943  * given MTU.  The frame length will be equal to the MTU plus a
 944  * constant amount of header space and padding.  This is the quantity
 945  * that the net driver will program into the MAC as the maximum frame
 946  * length.
 947  *
 948  * The 10G MAC used in Falcon requires 8-byte alignment on the frame
 949  * length, so we round up to the nearest 8.
 950  *
 951  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
 952  * XGMII cycle).  If the frame length reaches the maximum value in the
 953  * same cycle, the XMAC can miss the IPG altogether.  We work around
 954  * this by adding a further 16 bytes.
 955  */
 956 #define EFX_MAX_FRAME_LEN(mtu) \
 957         ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
 958
 959
 960 #endif /* EFX_NET_DRIVER_H */