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i2c-mpc: Do not generate STOP after read.
[linux-2.6/linux-2.6-openrd.git] / drivers / i2c / busses / i2c-mpc.c
blobf627001108b8dc5855f591207e766f01f230225a
1 /*
2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
8 *
9 * Release 0.8
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_i2c.h>
22
23 #include <linux/io.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #include <asm/mpc52xx.h>
30 #include <sysdev/fsl_soc.h>
31
32 #define DRV_NAME "mpc-i2c"
33
34 #define MPC_I2C_FDR 0x04
35 #define MPC_I2C_CR 0x08
36 #define MPC_I2C_SR 0x0c
37 #define MPC_I2C_DR 0x10
38 #define MPC_I2C_DFSRR 0x14
39
40 #define CCR_MEN 0x80
41 #define CCR_MIEN 0x40
42 #define CCR_MSTA 0x20
43 #define CCR_MTX 0x10
44 #define CCR_TXAK 0x08
45 #define CCR_RSTA 0x04
46
47 #define CSR_MCF 0x80
48 #define CSR_MAAS 0x40
49 #define CSR_MBB 0x20
50 #define CSR_MAL 0x10
51 #define CSR_SRW 0x04
52 #define CSR_MIF 0x02
53 #define CSR_RXAK 0x01
54
55 struct mpc_i2c {
56 struct device *dev;
57 void __iomem *base;
58 u32 interrupt;
59 wait_queue_head_t queue;
60 struct i2c_adapter adap;
61 int irq;
62 };
63
64 struct mpc_i2c_divider {
65 u16 divider;
66 u16 fdr; /* including dfsrr */
67 };
68
69 struct mpc_i2c_match_data {
70 void (*setclock)(struct device_node *node,
71 struct mpc_i2c *i2c,
72 u32 clock, u32 prescaler);
73 u32 prescaler;
74 };
75
76 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
77 {
78 writeb(x, i2c->base + MPC_I2C_CR);
79 }
80
81 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
82 {
83 struct mpc_i2c *i2c = dev_id;
84 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
85 /* Read again to allow register to stabilise */
86 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
87 writeb(0, i2c->base + MPC_I2C_SR);
88 wake_up(&i2c->queue);
89 }
90 return IRQ_HANDLED;
91 }
92
93 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
94 * the bus, because it wants to send ACK.
95 * Following sequence of enabling/disabling and sending start/stop generates
96 * the pulse, so it's all OK.
97 */
98 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
99 {
100 writeccr(i2c, 0);
101 udelay(30);
102 writeccr(i2c, CCR_MEN);
103 udelay(30);
104 writeccr(i2c, CCR_MSTA | CCR_MTX);
105 udelay(30);
106 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
107 udelay(30);
108 writeccr(i2c, CCR_MEN);
109 udelay(30);
110 }
111
112 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
113 {
114 unsigned long orig_jiffies = jiffies;
115 u32 x;
116 int result = 0;
117
118 if (i2c->irq == NO_IRQ) {
119 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
120 schedule();
121 if (time_after(jiffies, orig_jiffies + timeout)) {
122 dev_dbg(i2c->dev, "timeout\n");
123 writeccr(i2c, 0);
124 result = -EIO;
125 break;
126 }
127 }
128 x = readb(i2c->base + MPC_I2C_SR);
129 writeb(0, i2c->base + MPC_I2C_SR);
130 } else {
131 /* Interrupt mode */
132 result = wait_event_timeout(i2c->queue,
133 (i2c->interrupt & CSR_MIF), timeout);
134
135 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
136 dev_dbg(i2c->dev, "wait timeout\n");
137 writeccr(i2c, 0);
138 result = -ETIMEDOUT;
139 }
140
141 x = i2c->interrupt;
142 i2c->interrupt = 0;
143 }
144
145 if (result < 0)
146 return result;
147
148 if (!(x & CSR_MCF)) {
149 dev_dbg(i2c->dev, "unfinished\n");
150 return -EIO;
151 }
152
153 if (x & CSR_MAL) {
154 dev_dbg(i2c->dev, "MAL\n");
155 return -EIO;
156 }
157
158 if (writing && (x & CSR_RXAK)) {
159 dev_dbg(i2c->dev, "No RXAK\n");
160 /* generate stop */
161 writeccr(i2c, CCR_MEN);
162 return -EIO;
163 }
164 return 0;
165 }
166
167 #ifdef CONFIG_PPC_MPC52xx
168 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
169 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
170 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
171 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
172 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
173 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
174 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
175 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
176 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
177 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
178 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
179 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
180 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
181 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
182 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
183 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
184 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
185 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
186 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
187 };
188
189 int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
190 {
191 const struct mpc_i2c_divider *div = NULL;
192 unsigned int pvr = mfspr(SPRN_PVR);
193 u32 divider;
194 int i;
195
196 if (!clock)
197 return -EINVAL;
198
199 /* Determine divider value */
200 divider = mpc5xxx_get_bus_frequency(node) / clock;
201
202 /*
203 * We want to choose an FDR/DFSR that generates an I2C bus speed that
204 * is equal to or lower than the requested speed.
205 */
206 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
207 div = &mpc_i2c_dividers_52xx[i];
208 /* Old MPC5200 rev A CPUs do not support the high bits */
209 if (div->fdr & 0xc0 && pvr == 0x80822011)
210 continue;
211 if (div->divider >= divider)
212 break;
213 }
214
215 return div ? (int)div->fdr : -EINVAL;
216 }
217
218 static void mpc_i2c_setclock_52xx(struct device_node *node,
219 struct mpc_i2c *i2c,
220 u32 clock, u32 prescaler)
221 {
222 int ret, fdr;
223
224 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
225 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
226
227 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
228
229 if (ret >= 0)
230 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
231 }
232 #else /* !CONFIG_PPC_MPC52xx */
233 static void mpc_i2c_setclock_52xx(struct device_node *node,
234 struct mpc_i2c *i2c,
235 u32 clock, u32 prescaler)
236 {
237 }
238 #endif /* CONFIG_PPC_MPC52xx*/
239
240 #ifdef CONFIG_FSL_SOC
241 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
242 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
243 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
244 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
245 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
246 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
247 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
248 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
249 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
250 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
251 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
252 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
253 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
254 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
255 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
256 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
257 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
258 {49152, 0x011e}, {61440, 0x011f}
259 };
260
261 u32 mpc_i2c_get_sec_cfg_8xxx(void)
262 {
263 struct device_node *node = NULL;
264 u32 __iomem *reg;
265 u32 val = 0;
266
267 node = of_find_node_by_name(NULL, "global-utilities");
268 if (node) {
269 const u32 *prop = of_get_property(node, "reg", NULL);
270 if (prop) {
271 /*
272 * Map and check POR Device Status Register 2
273 * (PORDEVSR2) at 0xE0014
274 */
275 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
276 if (!reg)
277 printk(KERN_ERR
278 "Error: couldn't map PORDEVSR2\n");
279 else
280 val = in_be32(reg) & 0x00000080; /* sec-cfg */
281 iounmap(reg);
282 }
283 }
284 if (node)
285 of_node_put(node);
286
287 return val;
288 }
289
290 int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
291 {
292 const struct mpc_i2c_divider *div = NULL;
293 u32 divider;
294 int i;
295
296 if (!clock)
297 return -EINVAL;
298
299 /* Determine proper divider value */
300 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
301 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
302 if (!prescaler)
303 prescaler = 1;
304
305 divider = fsl_get_sys_freq() / clock / prescaler;
306
307 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
308 fsl_get_sys_freq(), clock, divider);
309
310 /*
311 * We want to choose an FDR/DFSR that generates an I2C bus speed that
312 * is equal to or lower than the requested speed.
313 */
314 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
315 div = &mpc_i2c_dividers_8xxx[i];
316 if (div->divider >= divider)
317 break;
318 }
319
320 return div ? (int)div->fdr : -EINVAL;
321 }
322
323 static void mpc_i2c_setclock_8xxx(struct device_node *node,
324 struct mpc_i2c *i2c,
325 u32 clock, u32 prescaler)
326 {
327 int ret, fdr;
328
329 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
330 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
331
332 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
333 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
334
335 if (ret >= 0)
336 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
337 clock, fdr >> 8, fdr & 0xff);
338 }
339
340 #else /* !CONFIG_FSL_SOC */
341 static void mpc_i2c_setclock_8xxx(struct device_node *node,
342 struct mpc_i2c *i2c,
343 u32 clock, u32 prescaler)
344 {
345 }
346 #endif /* CONFIG_FSL_SOC */
347
348 static void mpc_i2c_start(struct mpc_i2c *i2c)
349 {
350 /* Clear arbitration */
351 writeb(0, i2c->base + MPC_I2C_SR);
352 /* Start with MEN */
353 writeccr(i2c, CCR_MEN);
354 }
355
356 static void mpc_i2c_stop(struct mpc_i2c *i2c)
357 {
358 writeccr(i2c, CCR_MEN);
359 }
360
361 static int mpc_write(struct mpc_i2c *i2c, int target,
362 const u8 *data, int length, int restart)
363 {
364 int i, result;
365 unsigned timeout = i2c->adap.timeout;
366 u32 flags = restart ? CCR_RSTA : 0;
367
368 /* Start as master */
369 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
370 /* Write target byte */
371 writeb((target << 1), i2c->base + MPC_I2C_DR);
372
373 result = i2c_wait(i2c, timeout, 1);
374 if (result < 0)
375 return result;
376
377 for (i = 0; i < length; i++) {
378 /* Write data byte */
379 writeb(data[i], i2c->base + MPC_I2C_DR);
380
381 result = i2c_wait(i2c, timeout, 1);
382 if (result < 0)
383 return result;
384 }
385
386 return 0;
387 }
388
389 static int mpc_read(struct mpc_i2c *i2c, int target,
390 u8 *data, int length, int restart)
391 {
392 unsigned timeout = i2c->adap.timeout;
393 int i, result;
394 u32 flags = restart ? CCR_RSTA : 0;
395
396 /* Switch to read - restart */
397 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
398 /* Write target address byte - this time with the read flag set */
399 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
400
401 result = i2c_wait(i2c, timeout, 1);
402 if (result < 0)
403 return result;
404
405 if (length) {
406 if (length == 1)
407 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
408 else
409 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
410 /* Dummy read */
411 readb(i2c->base + MPC_I2C_DR);
412 }
413
414 for (i = 0; i < length; i++) {
415 result = i2c_wait(i2c, timeout, 0);
416 if (result < 0)
417 return result;
418
419 /* Generate txack on next to last byte */
420 if (i == length - 2)
421 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
422 /* Do not generate stop on last byte */
423 if (i == length - 1)
424 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX);
425 data[i] = readb(i2c->base + MPC_I2C_DR);
426 }
427
428 return length;
429 }
430
431 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
432 {
433 struct i2c_msg *pmsg;
434 int i;
435 int ret = 0;
436 unsigned long orig_jiffies = jiffies;
437 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
438
439 mpc_i2c_start(i2c);
440
441 /* Allow bus up to 1s to become not busy */
442 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
443 if (signal_pending(current)) {
444 dev_dbg(i2c->dev, "Interrupted\n");
445 writeccr(i2c, 0);
446 return -EINTR;
447 }
448 if (time_after(jiffies, orig_jiffies + HZ)) {
449 dev_dbg(i2c->dev, "timeout\n");
450 if (readb(i2c->base + MPC_I2C_SR) ==
451 (CSR_MCF | CSR_MBB | CSR_RXAK))
452 mpc_i2c_fixup(i2c);
453 return -EIO;
454 }
455 schedule();
456 }
457
458 for (i = 0; ret >= 0 && i < num; i++) {
459 pmsg = &msgs[i];
460 dev_dbg(i2c->dev,
461 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
462 pmsg->flags & I2C_M_RD ? "read" : "write",
463 pmsg->len, pmsg->addr, i + 1, num);
464 if (pmsg->flags & I2C_M_RD)
465 ret =
466 mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
467 else
468 ret =
469 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
470 }
471 mpc_i2c_stop(i2c);
472 return (ret < 0) ? ret : num;
473 }
474
475 static u32 mpc_functionality(struct i2c_adapter *adap)
476 {
477 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
478 }
479
480 static const struct i2c_algorithm mpc_algo = {
481 .master_xfer = mpc_xfer,
482 .functionality = mpc_functionality,
483 };
484
485 static struct i2c_adapter mpc_ops = {
486 .owner = THIS_MODULE,
487 .name = "MPC adapter",
488 .algo = &mpc_algo,
489 .timeout = HZ,
490 };
491
492 static int __devinit fsl_i2c_probe(struct of_device *op,
493 const struct of_device_id *match)
494 {
495 struct mpc_i2c *i2c;
496 const u32 *prop;
497 u32 clock = 0;
498 int result = 0;
499 int plen;
500
501 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
502 if (!i2c)
503 return -ENOMEM;
504
505 i2c->dev = &op->dev; /* for debug and error output */
506
507 init_waitqueue_head(&i2c->queue);
508
509 i2c->base = of_iomap(op->node, 0);
510 if (!i2c->base) {
511 dev_err(i2c->dev, "failed to map controller\n");
512 result = -ENOMEM;
513 goto fail_map;
514 }
515
516 i2c->irq = irq_of_parse_and_map(op->node, 0);
517 if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
518 result = request_irq(i2c->irq, mpc_i2c_isr,
519 IRQF_SHARED, "i2c-mpc", i2c);
520 if (result < 0) {
521 dev_err(i2c->dev, "failed to attach interrupt\n");
522 goto fail_request;
523 }
524 }
525
526 if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
527 prop = of_get_property(op->node, "clock-frequency", &plen);
528 if (prop && plen == sizeof(u32))
529 clock = *prop;
530
531 if (match->data) {
532 struct mpc_i2c_match_data *data =
533 (struct mpc_i2c_match_data *)match->data;
534 data->setclock(op->node, i2c, clock, data->prescaler);
535 } else {
536 /* Backwards compatibility */
537 if (of_get_property(op->node, "dfsrr", NULL))
538 mpc_i2c_setclock_8xxx(op->node, i2c,
539 clock, 0);
540 }
541 }
542
543 dev_set_drvdata(&op->dev, i2c);
544
545 i2c->adap = mpc_ops;
546 i2c_set_adapdata(&i2c->adap, i2c);
547 i2c->adap.dev.parent = &op->dev;
548
549 result = i2c_add_adapter(&i2c->adap);
550 if (result < 0) {
551 dev_err(i2c->dev, "failed to add adapter\n");
552 goto fail_add;
553 }
554 of_register_i2c_devices(&i2c->adap, op->node);
555
556 return result;
557
558 fail_add:
559 dev_set_drvdata(&op->dev, NULL);
560 free_irq(i2c->irq, i2c);
561 fail_request:
562 irq_dispose_mapping(i2c->irq);
563 iounmap(i2c->base);
564 fail_map:
565 kfree(i2c);
566 return result;
567 };
568
569 static int __devexit fsl_i2c_remove(struct of_device *op)
570 {
571 struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
572
573 i2c_del_adapter(&i2c->adap);
574 dev_set_drvdata(&op->dev, NULL);
575
576 if (i2c->irq != NO_IRQ)
577 free_irq(i2c->irq, i2c);
578
579 irq_dispose_mapping(i2c->irq);
580 iounmap(i2c->base);
581 kfree(i2c);
582 return 0;
583 };
584
585 static const struct of_device_id mpc_i2c_of_match[] = {
586 {.compatible = "mpc5200-i2c",
587 .data = &(struct mpc_i2c_match_data) {
588 .setclock = mpc_i2c_setclock_52xx,
589 },
590 },
591 {.compatible = "fsl,mpc5200b-i2c",
592 .data = &(struct mpc_i2c_match_data) {
593 .setclock = mpc_i2c_setclock_52xx,
594 },
595 },
596 {.compatible = "fsl,mpc5200-i2c",
597 .data = &(struct mpc_i2c_match_data) {
598 .setclock = mpc_i2c_setclock_52xx,
599 },
600 },
601 {.compatible = "fsl,mpc8313-i2c",
602 .data = &(struct mpc_i2c_match_data) {
603 .setclock = mpc_i2c_setclock_8xxx,
604 },
605 },
606 {.compatible = "fsl,mpc8543-i2c",
607 .data = &(struct mpc_i2c_match_data) {
608 .setclock = mpc_i2c_setclock_8xxx,
609 .prescaler = 2,
610 },
611 },
612 {.compatible = "fsl,mpc8544-i2c",
613 .data = &(struct mpc_i2c_match_data) {
614 .setclock = mpc_i2c_setclock_8xxx,
615 .prescaler = 3,
616 },
617 /* Backward compatibility */
618 },
619 {.compatible = "fsl-i2c", },
620 {},
621 };
622
623 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
624
625
626 /* Structure for a device driver */
627 static struct of_platform_driver mpc_i2c_driver = {
628 .match_table = mpc_i2c_of_match,
629 .probe = fsl_i2c_probe,
630 .remove = __devexit_p(fsl_i2c_remove),
631 .driver = {
632 .owner = THIS_MODULE,
633 .name = DRV_NAME,
634 },
635 };
636
637 static int __init fsl_i2c_init(void)
638 {
639 int rv;
640
641 rv = of_register_platform_driver(&mpc_i2c_driver);
642 if (rv)
643 printk(KERN_ERR DRV_NAME
644 " of_register_platform_driver failed (%i)\n", rv);
645 return rv;
646 }
647
648 static void __exit fsl_i2c_exit(void)
649 {
650 of_unregister_platform_driver(&mpc_i2c_driver);
651 }
652
653 module_init(fsl_i2c_init);
654 module_exit(fsl_i2c_exit);
655
656 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
657 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
658 "MPC824x/85xx/52xx processors");
659 MODULE_LICENSE("GPL");
linux 2.6 git repository for openrd