MIPS: Optimize spinlocks.
commit500c2e1fdbcc2b273bd4c695a9b8ac8196f61614
authorDavid Daney <ddaney@caviumnetworks.com>
Thu, 4 Feb 2010 19:31:49 +0000 (4 11:31 -0800)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 27 Feb 2010 11:53:42 +0000 (27 12:53 +0100)
treef24c80f609a739beed194fd5c66abf9bc48ce0d6
parente275ed5ee94b358964a0dae1c8b49f0bff260b60
MIPS: Optimize spinlocks.

The current locking mechanism uses a ll/sc sequence to release a
spinlock.  This is slower than a wmb() followed by a store to unlock.

The branching forward to .subsection 2 on sc failure slows down the
contended case.  So we get rid of that part too.

Since we are now working on naturally aligned u16 values, we can get
rid of a masking operation as the LHU already does the right thing.
The ANDI are reversed for better scheduling on multi-issue CPUs

On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet
forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/barrier.h
arch/mips/include/asm/spinlock.h
arch/mips/include/asm/spinlock_types.h