spi/fsl_espi: change the read behaviour of the SPIRF
commit477ca3ad6ac5cdbd5bd40941fc22c6eedc9aa90d
authorMingkai Hu <Mingkai.hu@freescale.com>
Wed, 1 Dec 2010 09:29:18 +0000 (1 17:29 +0800)
committerGrant Likely <grant.likely@secretlab.ca>
Thu, 30 Dec 2010 06:04:46 +0000 (29 23:04 -0700)
tree9552afcd670e798b1d98ccc4efe2f5baae572d3d
parent94a544a4e8d05a027613443c529c399c39cc3371
spi/fsl_espi: change the read behaviour of the SPIRF

The user must read N bytes of SPIRF (1 <= N <= 4) that do not exceed the
amount of data in the receive FIFO, so read the SPIRF byte by byte when
the data in receive FIFO is less than 4 bytes.

On Simics, when read N bytes that exceed the amout of data in receive
FIFO, we can't read the data out, that is we can't clear the rx FIFO,
then the CPU will loop on the espi rx interrupt.

Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
drivers/spi/spi_fsl_espi.c