drivers/net/ethernet/mellanox/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/bitops.h>
  38 #include <linux/compiler.h>
  39 #include <linux/list.h>
  40 #include <linux/mutex.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/if_vlan.h>
  43 #ifdef CONFIG_MLX4_EN_DCB
  44 #include <linux/dcbnl.h>
  45 #endif
  46 #include <linux/cpu_rmap.h>
  47
  48 #include <linux/mlx4/device.h>
  49 #include <linux/mlx4/qp.h>
  50 #include <linux/mlx4/cq.h>
  51 #include <linux/mlx4/srq.h>
  52 #include <linux/mlx4/doorbell.h>
  53 #include <linux/mlx4/cmd.h>
  54
  55 #include "en_port.h"
  56
  57 #define DRV_NAME        "mlx4_en"
  58 #define DRV_VERSION     "2.0"
  59 #define DRV_RELDATE     "Dec 2011"
  60
  61 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  62
  63 /*
  64  * Device constants
  65  */
  66
  67
  68 #define MLX4_EN_PAGE_SHIFT      12
  69 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  70 #define MAX_RX_RINGS            16
  71 #define MIN_RX_RINGS            4
  72 #define TXBB_SIZE               64
  73 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  74 #define STAMP_STRIDE            64
  75 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  76 #define STAMP_SHIFT             31
  77 #define STAMP_VAL               0x7fffffff
  78 #define STATS_DELAY             (HZ / 4)
  79 #define MAX_NUM_OF_FS_RULES     256
  80
  81 #define MLX4_EN_FILTER_HASH_SHIFT 4
  82 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
  83
  84 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  85 #define MAX_DESC_SIZE           512
  86 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  87
  88 /*
  89  * OS related constants and tunables
  90  */
  91
  92 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
  93
  94 /* Use the maximum between 16384 and a single page */
  95 #define MLX4_EN_ALLOC_SIZE      PAGE_ALIGN(16384)
  96 #define MLX4_EN_ALLOC_ORDER     get_order(MLX4_EN_ALLOC_SIZE)
  97
  98 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
  99  * and 4K allocations) */
 100 enum {
 101         FRAG_SZ0 = 512 - NET_IP_ALIGN,
 102         FRAG_SZ1 = 1024,
 103         FRAG_SZ2 = 4096,
 104         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 105 };
 106 #define MLX4_EN_MAX_RX_FRAGS    4
 107
 108 /* Maximum ring sizes */
 109 #define MLX4_EN_MAX_TX_SIZE     8192
 110 #define MLX4_EN_MAX_RX_SIZE     8192
 111
 112 /* Minimum ring size for our page-allocation scheme to work */
 113 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 114 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 115
 116 #define MLX4_EN_SMALL_PKT_SIZE          64
 117 #define MLX4_EN_MAX_TX_RING_P_UP        32
 118 #define MLX4_EN_NUM_UP                  8
 119 #define MLX4_EN_DEF_TX_RING_SIZE        512
 120 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 121
 122 /* Target number of packets to coalesce with interrupt moderation */
 123 #define MLX4_EN_RX_COAL_TARGET  44
 124 #define MLX4_EN_RX_COAL_TIME    0x10
 125
 126 #define MLX4_EN_TX_COAL_PKTS    16
 127 #define MLX4_EN_TX_COAL_TIME    0x10
 128
 129 #define MLX4_EN_RX_RATE_LOW             400000
 130 #define MLX4_EN_RX_COAL_TIME_LOW        0
 131 #define MLX4_EN_RX_RATE_HIGH            450000
 132 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 133 #define MLX4_EN_RX_SIZE_THRESH          1024
 134 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 135 #define MLX4_EN_SAMPLE_INTERVAL         0
 136 #define MLX4_EN_AVG_PKT_SMALL           256
 137
 138 #define MLX4_EN_AUTO_CONF       0xffff
 139
 140 #define MLX4_EN_DEF_RX_PAUSE    1
 141 #define MLX4_EN_DEF_TX_PAUSE    1
 142
 143 /* Interval between successive polls in the Tx routine when polling is used
 144    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 145 #define MLX4_EN_TX_POLL_MODER   16
 146 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 147
 148 #define ETH_LLC_SNAP_SIZE       8
 149
 150 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 151 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 152 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
 153
 154 #define MLX4_EN_MIN_MTU         46
 155 #define ETH_BCAST               0xffffffffffffULL
 156
 157 #define MLX4_EN_LOOPBACK_RETRIES        5
 158 #define MLX4_EN_LOOPBACK_TIMEOUT        100
 159
 160 #ifdef MLX4_EN_PERF_STAT
 161 /* Number of samples to 'average' */
 162 #define AVG_SIZE                        128
 163 #define AVG_FACTOR                      1024
 164 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 165
 166 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 167 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 168 #define AVG_PERF_COUNTER(cnt, sample) \
 169         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 170 #define GET_PERF_COUNTER(cnt)           (cnt)
 171 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 172
 173 #else
 174
 175 #define NUM_PERF_STATS                  0
 176 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 177 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 178 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 179 #define GET_PERF_COUNTER(cnt)           (0)
 180 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 181 #endif /* MLX4_EN_PERF_STAT */
 182
 183 /*
 184  * Configurables
 185  */
 186
 187 enum cq_type {
 188         RX = 0,
 189         TX = 1,
 190 };
 191
 192
 193 /*
 194  * Useful macros
 195  */
 196 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 197 #define XNOR(x, y)              (!(x) == !(y))
 198 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 199
 200
 201 struct mlx4_en_tx_info {
 202         struct sk_buff *skb;
 203         u32 nr_txbb;
 204         u32 nr_bytes;
 205         u8 linear;
 206         u8 data_offset;
 207         u8 inl;
 208 };
 209
 210
 211 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 212 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 213 #define MLX4_EN_MEMTYPE_PAD     0x100
 214 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 215
 216
 217 struct mlx4_en_tx_desc {
 218         struct mlx4_wqe_ctrl_seg ctrl;
 219         union {
 220                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 221                 struct mlx4_wqe_lso_seg lso;
 222                 struct mlx4_wqe_inline_seg inl;
 223         };
 224 };
 225
 226 #define MLX4_EN_USE_SRQ         0x01000000
 227
 228 #define MLX4_EN_CX3_LOW_ID      0x1000
 229 #define MLX4_EN_CX3_HIGH_ID     0x1005
 230
 231 struct mlx4_en_rx_alloc {
 232         struct page *page;
 233         dma_addr_t dma;
 234         u16 offset;
 235 };
 236
 237 struct mlx4_en_tx_ring {
 238         struct mlx4_hwq_resources wqres;
 239         u32 size ; /* number of TXBBs */
 240         u32 size_mask;
 241         u16 stride;
 242         u16 cqn;        /* index of port CQ associated with this ring */
 243         u32 prod;
 244         u32 cons;
 245         u32 buf_size;
 246         u32 doorbell_qpn;
 247         void *buf;
 248         u16 poll_cnt;
 249         struct mlx4_en_tx_info *tx_info;
 250         u8 *bounce_buf;
 251         u32 last_nr_txbb;
 252         struct mlx4_qp qp;
 253         struct mlx4_qp_context context;
 254         int qpn;
 255         enum mlx4_qp_state qp_state;
 256         struct mlx4_srq dummy;
 257         unsigned long bytes;
 258         unsigned long packets;
 259         unsigned long tx_csum;
 260         struct mlx4_bf bf;
 261         bool bf_enabled;
 262         struct netdev_queue *tx_queue;
 263 };
 264
 265 struct mlx4_en_rx_desc {
 266         /* actual number of entries depends on rx ring stride */
 267         struct mlx4_wqe_data_seg data[0];
 268 };
 269
 270 struct mlx4_en_rx_ring {
 271         struct mlx4_hwq_resources wqres;
 272         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 273         u32 size ;      /* number of Rx descs*/
 274         u32 actual_size;
 275         u32 size_mask;
 276         u16 stride;
 277         u16 log_stride;
 278         u16 cqn;        /* index of port CQ associated with this ring */
 279         u32 prod;
 280         u32 cons;
 281         u32 buf_size;
 282         u8  fcs_del;
 283         void *buf;
 284         void *rx_info;
 285         unsigned long bytes;
 286         unsigned long packets;
 287         unsigned long csum_ok;
 288         unsigned long csum_none;
 289 };
 290
 291 struct mlx4_en_cq {
 292         struct mlx4_cq          mcq;
 293         struct mlx4_hwq_resources wqres;
 294         int                     ring;
 295         spinlock_t              lock;
 296         struct net_device      *dev;
 297         struct napi_struct      napi;
 298         int size;
 299         int buf_size;
 300         unsigned vector;
 301         enum cq_type is_tx;
 302         u16 moder_time;
 303         u16 moder_cnt;
 304         struct mlx4_cqe *buf;
 305 #define MLX4_EN_OPCODE_ERROR    0x1e
 306 };
 307
 308 struct mlx4_en_port_profile {
 309         u32 flags;
 310         u32 tx_ring_num;
 311         u32 rx_ring_num;
 312         u32 tx_ring_size;
 313         u32 rx_ring_size;
 314         u8 rx_pause;
 315         u8 rx_ppp;
 316         u8 tx_pause;
 317         u8 tx_ppp;
 318         int rss_rings;
 319 };
 320
 321 struct mlx4_en_profile {
 322         int rss_xor;
 323         int udp_rss;
 324         u8 rss_mask;
 325         u32 active_ports;
 326         u32 small_pkt_int;
 327         u8 no_reset;
 328         u8 num_tx_rings_p_up;
 329         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 330 };
 331
 332 struct mlx4_en_dev {
 333         struct mlx4_dev         *dev;
 334         struct pci_dev          *pdev;
 335         struct mutex            state_lock;
 336         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 337         u32                     port_cnt;
 338         bool                    device_up;
 339         struct mlx4_en_profile  profile;
 340         u32                     LSO_support;
 341         struct workqueue_struct *workqueue;
 342         struct device           *dma_device;
 343         void __iomem            *uar_map;
 344         struct mlx4_uar         priv_uar;
 345         struct mlx4_mr          mr;
 346         u32                     priv_pdn;
 347         spinlock_t              uar_lock;
 348         u8                      mac_removed[MLX4_MAX_PORTS + 1];
 349 };
 350
 351
 352 struct mlx4_en_rss_map {
 353         int base_qpn;
 354         struct mlx4_qp qps[MAX_RX_RINGS];
 355         enum mlx4_qp_state state[MAX_RX_RINGS];
 356         struct mlx4_qp indir_qp;
 357         enum mlx4_qp_state indir_state;
 358 };
 359
 360 struct mlx4_en_port_state {
 361         int link_state;
 362         int link_speed;
 363         int transciver;
 364 };
 365
 366 struct mlx4_en_pkt_stats {
 367         unsigned long broadcast;
 368         unsigned long rx_prio[8];
 369         unsigned long tx_prio[8];
 370 #define NUM_PKT_STATS           17
 371 };
 372
 373 struct mlx4_en_port_stats {
 374         unsigned long tso_packets;
 375         unsigned long queue_stopped;
 376         unsigned long wake_queue;
 377         unsigned long tx_timeout;
 378         unsigned long rx_alloc_failed;
 379         unsigned long rx_chksum_good;
 380         unsigned long rx_chksum_none;
 381         unsigned long tx_chksum_offload;
 382 #define NUM_PORT_STATS          8
 383 };
 384
 385 struct mlx4_en_perf_stats {
 386         u32 tx_poll;
 387         u64 tx_pktsz_avg;
 388         u32 inflight_avg;
 389         u16 tx_coal_avg;
 390         u16 rx_coal_avg;
 391         u32 napi_quota;
 392 #define NUM_PERF_COUNTERS               6
 393 };
 394
 395 enum mlx4_en_mclist_act {
 396         MCLIST_NONE,
 397         MCLIST_REM,
 398         MCLIST_ADD,
 399 };
 400
 401 struct mlx4_en_mc_list {
 402         struct list_head        list;
 403         enum mlx4_en_mclist_act action;
 404         u8                      addr[ETH_ALEN];
 405         u64                     reg_id;
 406 };
 407
 408 struct mlx4_en_frag_info {
 409         u16 frag_size;
 410         u16 frag_prefix_size;
 411         u16 frag_stride;
 412         u16 frag_align;
 413         u16 last_offset;
 414
 415 };
 416
 417 #ifdef CONFIG_MLX4_EN_DCB
 418 /* Minimal TC BW - setting to 0 will block traffic */
 419 #define MLX4_EN_BW_MIN 1
 420 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
 421
 422 #define MLX4_EN_TC_ETS 7
 423
 424 #endif
 425
 426 struct ethtool_flow_id {
 427         struct ethtool_rx_flow_spec flow_spec;
 428         u64 id;
 429 };
 430
 431 struct mlx4_en_priv {
 432         struct mlx4_en_dev *mdev;
 433         struct mlx4_en_port_profile *prof;
 434         struct net_device *dev;
 435         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 436         struct net_device_stats stats;
 437         struct net_device_stats ret_stats;
 438         struct mlx4_en_port_state port_state;
 439         spinlock_t stats_lock;
 440         struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
 441
 442         unsigned long last_moder_packets[MAX_RX_RINGS];
 443         unsigned long last_moder_tx_packets;
 444         unsigned long last_moder_bytes[MAX_RX_RINGS];
 445         unsigned long last_moder_jiffies;
 446         int last_moder_time[MAX_RX_RINGS];
 447         u16 rx_usecs;
 448         u16 rx_frames;
 449         u16 tx_usecs;
 450         u16 tx_frames;
 451         u32 pkt_rate_low;
 452         u16 rx_usecs_low;
 453         u32 pkt_rate_high;
 454         u16 rx_usecs_high;
 455         u16 sample_interval;
 456         u16 adaptive_rx_coal;
 457         u32 msg_enable;
 458         u32 loopback_ok;
 459         u32 validate_loopback;
 460
 461         struct mlx4_hwq_resources res;
 462         int link_state;
 463         int last_link_state;
 464         bool port_up;
 465         int port;
 466         int registered;
 467         int allocated;
 468         int stride;
 469         u64 mac;
 470         int mac_index;
 471         unsigned max_mtu;
 472         int base_qpn;
 473
 474         struct mlx4_en_rss_map rss_map;
 475         __be32 ctrl_flags;
 476         u32 flags;
 477 #define MLX4_EN_FLAG_PROMISC    0x1
 478 #define MLX4_EN_FLAG_MC_PROMISC 0x2
 479         u32 tx_ring_num;
 480         u32 rx_ring_num;
 481         u32 rx_skb_size;
 482         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 483         u16 num_frags;
 484         u16 log_rx_info;
 485
 486         struct mlx4_en_tx_ring *tx_ring;
 487         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 488         struct mlx4_en_cq *tx_cq;
 489         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 490         struct mlx4_qp drop_qp;
 491         struct work_struct mcast_task;
 492         struct work_struct mac_task;
 493         struct work_struct watchdog_task;
 494         struct work_struct linkstate_task;
 495         struct delayed_work stats_task;
 496         struct mlx4_en_perf_stats pstats;
 497         struct mlx4_en_pkt_stats pkstats;
 498         struct mlx4_en_port_stats port_stats;
 499         u64 stats_bitmap;
 500         struct list_head mc_list;
 501         struct list_head curr_list;
 502         u64 broadcast_id;
 503         struct mlx4_en_stat_out_mbox hw_stats;
 504         int vids[128];
 505         bool wol;
 506         struct device *ddev;
 507         int base_tx_qpn;
 508
 509 #ifdef CONFIG_MLX4_EN_DCB
 510         struct ieee_ets ets;
 511         u16 maxrate[IEEE_8021QAZ_MAX_TCS];
 512 #endif
 513 #ifdef CONFIG_RFS_ACCEL
 514         spinlock_t filters_lock;
 515         int last_filter_id;
 516         struct list_head filters;
 517         struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
 518 #endif
 519
 520 };
 521
 522 enum mlx4_en_wol {
 523         MLX4_EN_WOL_MAGIC = (1ULL << 61),
 524         MLX4_EN_WOL_ENABLED = (1ULL << 62),
 525 };
 526
 527 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
 528
 529 void mlx4_en_destroy_netdev(struct net_device *dev);
 530 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 531                         struct mlx4_en_port_profile *prof);
 532
 533 int mlx4_en_start_port(struct net_device *dev);
 534 void mlx4_en_stop_port(struct net_device *dev);
 535
 536 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 537 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 538
 539 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 540                       int entries, int ring, enum cq_type mode);
 541 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 542 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 543                         int cq_idx);
 544 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 545 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 546 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 547
 548 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 549 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 550 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 551
 552 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 553                            int qpn, u32 size, u16 stride);
 554 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 555 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 556                              struct mlx4_en_tx_ring *ring,
 557                              int cq, int user_prio);
 558 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 559                                 struct mlx4_en_tx_ring *ring);
 560
 561 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 562                            struct mlx4_en_rx_ring *ring,
 563                            u32 size, u16 stride);
 564 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 565                              struct mlx4_en_rx_ring *ring,
 566                              u32 size, u16 stride);
 567 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 568 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 569                                 struct mlx4_en_rx_ring *ring);
 570 int mlx4_en_process_rx_cq(struct net_device *dev,
 571                           struct mlx4_en_cq *cq,
 572                           int budget);
 573 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 574 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 575                 int is_tx, int rss, int qpn, int cqn, int user_prio,
 576                 struct mlx4_qp_context *context);
 577 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 578 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 579 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 580
 581 void mlx4_en_calc_rx_buf(struct net_device *dev);
 582 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 583 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 584 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
 585 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
 586 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 587 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 588
 589 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 590 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
 591
 592 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 593 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
 594
 595 #ifdef CONFIG_MLX4_EN_DCB
 596 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
 597 #endif
 598
 599 #ifdef CONFIG_RFS_ACCEL
 600 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv,
 601                              struct mlx4_en_rx_ring *rx_ring);
 602 #endif
 603
 604 #define MLX4_EN_NUM_SELF_TEST   5
 605 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
 606 u64 mlx4_en_mac_to_u64(u8 *addr);
 607
 608 /*
 609  * Globals
 610  */
 611 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 612
 613
 614
 615 /*
 616  * printk / logging functions
 617  */
 618
 619 __printf(3, 4)
 620 int en_print(const char *level, const struct mlx4_en_priv *priv,
 621              const char *format, ...);
 622
 623 #define en_dbg(mlevel, priv, format, arg...)                    \
 624 do {                                                            \
 625         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
 626                 en_print(KERN_DEBUG, priv, format, ##arg);      \
 627 } while (0)
 628 #define en_warn(priv, format, arg...)                   \
 629         en_print(KERN_WARNING, priv, format, ##arg)
 630 #define en_err(priv, format, arg...)                    \
 631         en_print(KERN_ERR, priv, format, ##arg)
 632 #define en_info(priv, format, arg...)                   \
 633         en_print(KERN_INFO, priv, format, ## arg)
 634
 635 #define mlx4_err(mdev, format, arg...)                  \
 636         pr_err("%s %s: " format, DRV_NAME,              \
 637                dev_name(&mdev->pdev->dev), ##arg)
 638 #define mlx4_info(mdev, format, arg...)                 \
 639         pr_info("%s %s: " format, DRV_NAME,             \
 640                 dev_name(&mdev->pdev->dev), ##arg)
 641 #define mlx4_warn(mdev, format, arg...)                 \
 642         pr_warning("%s %s: " format, DRV_NAME,          \
 643                    dev_name(&mdev->pdev->dev), ##arg)
 644
 645 #endif