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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6/libata-dev.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
blobe81a747ea8ce0ee4461fea92565fa32b15ea6682
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
64 #include "bnx2x_sp.h"
65
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
68 /* FW files */
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77
78 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
79
80 /* Time in jiffies before concluding the transmitter is hung */
81 #define TX_TIMEOUT (5*HZ)
82
83 static char version[] =
84 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
85 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
86
87 MODULE_AUTHOR("Eliezer Tamir");
88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
89 "BCM57710/57711/57711E/"
90 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
91 "57840/57840_MF Driver");
92 MODULE_LICENSE("GPL");
93 MODULE_VERSION(DRV_MODULE_VERSION);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
97
98
99 int num_queues;
100 module_param(num_queues, int, 0);
101 MODULE_PARM_DESC(num_queues,
102 " Set number of queues (default is as a number of CPUs)");
103
104 static int disable_tpa;
105 module_param(disable_tpa, int, 0);
106 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
107
108 #define INT_MODE_INTx 1
109 #define INT_MODE_MSI 2
110 int int_mode;
111 module_param(int_mode, int, 0);
112 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
113 "(1 INT#x; 2 MSI)");
114
115 static int dropless_fc;
116 module_param(dropless_fc, int, 0);
117 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118
119 static int mrrs = -1;
120 module_param(mrrs, int, 0);
121 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
122
123 static int debug;
124 module_param(debug, int, 0);
125 MODULE_PARM_DESC(debug, " Default debug msglevel");
126
127
128
129 struct workqueue_struct *bnx2x_wq;
130
131 struct bnx2x_mac_vals {
132 u32 xmac_addr;
133 u32 xmac_val;
134 u32 emac_addr;
135 u32 emac_val;
136 u32 umac_addr;
137 u32 umac_val;
138 u32 bmac_addr;
139 u32 bmac_val[2];
140 };
141
142 enum bnx2x_board_type {
143 BCM57710 = 0,
144 BCM57711,
145 BCM57711E,
146 BCM57712,
147 BCM57712_MF,
148 BCM57712_VF,
149 BCM57800,
150 BCM57800_MF,
151 BCM57800_VF,
152 BCM57810,
153 BCM57810_MF,
154 BCM57810_VF,
155 BCM57840_4_10,
156 BCM57840_2_20,
157 BCM57840_MF,
158 BCM57840_VF,
159 BCM57811,
160 BCM57811_MF,
161 BCM57840_O,
162 BCM57840_MFO,
163 BCM57811_VF
164 };
165
166 /* indexed by board_type, above */
167 static struct {
168 char *name;
169 } board_info[] = {
170 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
171 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
172 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
173 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
174 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
175 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
176 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
177 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
178 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
179 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
180 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
181 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
182 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
183 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
184 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
186 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
187 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
188 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
189 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
190 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
191 };
192
193 #ifndef PCI_DEVICE_ID_NX2_57710
194 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
195 #endif
196 #ifndef PCI_DEVICE_ID_NX2_57711
197 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
198 #endif
199 #ifndef PCI_DEVICE_ID_NX2_57711E
200 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
201 #endif
202 #ifndef PCI_DEVICE_ID_NX2_57712
203 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
204 #endif
205 #ifndef PCI_DEVICE_ID_NX2_57712_MF
206 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
207 #endif
208 #ifndef PCI_DEVICE_ID_NX2_57712_VF
209 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
210 #endif
211 #ifndef PCI_DEVICE_ID_NX2_57800
212 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
213 #endif
214 #ifndef PCI_DEVICE_ID_NX2_57800_MF
215 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
216 #endif
217 #ifndef PCI_DEVICE_ID_NX2_57800_VF
218 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
219 #endif
220 #ifndef PCI_DEVICE_ID_NX2_57810
221 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
222 #endif
223 #ifndef PCI_DEVICE_ID_NX2_57810_MF
224 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
225 #endif
226 #ifndef PCI_DEVICE_ID_NX2_57840_O
227 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
228 #endif
229 #ifndef PCI_DEVICE_ID_NX2_57810_VF
230 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
231 #endif
232 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
233 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
234 #endif
235 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
236 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
237 #endif
238 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
239 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
240 #endif
241 #ifndef PCI_DEVICE_ID_NX2_57840_MF
242 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
243 #endif
244 #ifndef PCI_DEVICE_ID_NX2_57840_VF
245 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
246 #endif
247 #ifndef PCI_DEVICE_ID_NX2_57811
248 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
249 #endif
250 #ifndef PCI_DEVICE_ID_NX2_57811_MF
251 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
252 #endif
253 #ifndef PCI_DEVICE_ID_NX2_57811_VF
254 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
255 #endif
256
257 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
277 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
278 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
279 { 0 }
280 };
281
282 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
283
284 /* Global resources for unloading a previously loaded device */
285 #define BNX2X_PREV_WAIT_NEEDED 1
286 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
287 static LIST_HEAD(bnx2x_prev_list);
288 /****************************************************************************
289 * General service functions
290 ****************************************************************************/
291
292 static void __storm_memset_dma_mapping(struct bnx2x *bp,
293 u32 addr, dma_addr_t mapping)
294 {
295 REG_WR(bp, addr, U64_LO(mapping));
296 REG_WR(bp, addr + 4, U64_HI(mapping));
297 }
298
299 static void storm_memset_spq_addr(struct bnx2x *bp,
300 dma_addr_t mapping, u16 abs_fid)
301 {
302 u32 addr = XSEM_REG_FAST_MEMORY +
303 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
304
305 __storm_memset_dma_mapping(bp, addr, mapping);
306 }
307
308 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
309 u16 pf_id)
310 {
311 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
312 pf_id);
313 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
318 pf_id);
319 }
320
321 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
322 u8 enable)
323 {
324 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
325 enable);
326 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
331 enable);
332 }
333
334 static void storm_memset_eq_data(struct bnx2x *bp,
335 struct event_ring_data *eq_data,
336 u16 pfid)
337 {
338 size_t size = sizeof(struct event_ring_data);
339
340 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
341
342 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
343 }
344
345 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
346 u16 pfid)
347 {
348 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
349 REG_WR16(bp, addr, eq_prod);
350 }
351
352 /* used only at init
353 * locking is done by mcp
354 */
355 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
356 {
357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
358 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
359 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
360 PCICFG_VENDOR_ID_OFFSET);
361 }
362
363 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
364 {
365 u32 val;
366
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
368 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
369 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
370 PCICFG_VENDOR_ID_OFFSET);
371
372 return val;
373 }
374
375 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
376 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
377 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
378 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
379 #define DMAE_DP_DST_NONE "dst_addr [none]"
380
381 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
382 {
383 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
384
385 switch (dmae->opcode & DMAE_COMMAND_DST) {
386 case DMAE_CMD_DST_PCI:
387 if (src_type == DMAE_CMD_SRC_PCI)
388 DP(msglvl, "DMAE: opcode 0x%08x\n"
389 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
390 "comp_addr [%x:%08x], comp_val 0x%08x\n",
391 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
392 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
393 dmae->comp_addr_hi, dmae->comp_addr_lo,
394 dmae->comp_val);
395 else
396 DP(msglvl, "DMAE: opcode 0x%08x\n"
397 "src [%08x], len [%d*4], dst [%x:%08x]\n"
398 "comp_addr [%x:%08x], comp_val 0x%08x\n",
399 dmae->opcode, dmae->src_addr_lo >> 2,
400 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
401 dmae->comp_addr_hi, dmae->comp_addr_lo,
402 dmae->comp_val);
403 break;
404 case DMAE_CMD_DST_GRC:
405 if (src_type == DMAE_CMD_SRC_PCI)
406 DP(msglvl, "DMAE: opcode 0x%08x\n"
407 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
408 "comp_addr [%x:%08x], comp_val 0x%08x\n",
409 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
410 dmae->len, dmae->dst_addr_lo >> 2,
411 dmae->comp_addr_hi, dmae->comp_addr_lo,
412 dmae->comp_val);
413 else
414 DP(msglvl, "DMAE: opcode 0x%08x\n"
415 "src [%08x], len [%d*4], dst [%08x]\n"
416 "comp_addr [%x:%08x], comp_val 0x%08x\n",
417 dmae->opcode, dmae->src_addr_lo >> 2,
418 dmae->len, dmae->dst_addr_lo >> 2,
419 dmae->comp_addr_hi, dmae->comp_addr_lo,
420 dmae->comp_val);
421 break;
422 default:
423 if (src_type == DMAE_CMD_SRC_PCI)
424 DP(msglvl, "DMAE: opcode 0x%08x\n"
425 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
426 "comp_addr [%x:%08x] comp_val 0x%08x\n",
427 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
428 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
429 dmae->comp_val);
430 else
431 DP(msglvl, "DMAE: opcode 0x%08x\n"
432 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
433 "comp_addr [%x:%08x] comp_val 0x%08x\n",
434 dmae->opcode, dmae->src_addr_lo >> 2,
435 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
436 dmae->comp_val);
437 break;
438 }
439 }
440
441 /* copy command into DMAE command memory and set DMAE command go */
442 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
443 {
444 u32 cmd_offset;
445 int i;
446
447 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
448 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
449 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
450 }
451 REG_WR(bp, dmae_reg_go_c[idx], 1);
452 }
453
454 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
455 {
456 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
457 DMAE_CMD_C_ENABLE);
458 }
459
460 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
461 {
462 return opcode & ~DMAE_CMD_SRC_RESET;
463 }
464
465 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
466 bool with_comp, u8 comp_type)
467 {
468 u32 opcode = 0;
469
470 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
471 (dst_type << DMAE_COMMAND_DST_SHIFT));
472
473 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
474
475 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
476 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
477 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
478 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
479
480 #ifdef __BIG_ENDIAN
481 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
482 #else
483 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
484 #endif
485 if (with_comp)
486 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
487 return opcode;
488 }
489
490 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
491 struct dmae_command *dmae,
492 u8 src_type, u8 dst_type)
493 {
494 memset(dmae, 0, sizeof(struct dmae_command));
495
496 /* set the opcode */
497 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
498 true, DMAE_COMP_PCI);
499
500 /* fill in the completion parameters */
501 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
502 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
503 dmae->comp_val = DMAE_COMP_VAL;
504 }
505
506 /* issue a dmae command over the init-channel and wait for completion */
507 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
508 {
509 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
510 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
511 int rc = 0;
512
513 /*
514 * Lock the dmae channel. Disable BHs to prevent a dead-lock
515 * as long as this code is called both from syscall context and
516 * from ndo_set_rx_mode() flow that may be called from BH.
517 */
518 spin_lock_bh(&bp->dmae_lock);
519
520 /* reset completion */
521 *wb_comp = 0;
522
523 /* post the command on the channel used for initializations */
524 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
525
526 /* wait for completion */
527 udelay(5);
528 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
529
530 if (!cnt ||
531 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
532 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
533 BNX2X_ERR("DMAE timeout!\n");
534 rc = DMAE_TIMEOUT;
535 goto unlock;
536 }
537 cnt--;
538 udelay(50);
539 }
540 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
541 BNX2X_ERR("DMAE PCI error!\n");
542 rc = DMAE_PCI_ERROR;
543 }
544
545 unlock:
546 spin_unlock_bh(&bp->dmae_lock);
547 return rc;
548 }
549
550 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
551 u32 len32)
552 {
553 struct dmae_command dmae;
554
555 if (!bp->dmae_ready) {
556 u32 *data = bnx2x_sp(bp, wb_data[0]);
557
558 if (CHIP_IS_E1(bp))
559 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
560 else
561 bnx2x_init_str_wr(bp, dst_addr, data, len32);
562 return;
563 }
564
565 /* set opcode and fixed command fields */
566 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
567
568 /* fill in addresses and len */
569 dmae.src_addr_lo = U64_LO(dma_addr);
570 dmae.src_addr_hi = U64_HI(dma_addr);
571 dmae.dst_addr_lo = dst_addr >> 2;
572 dmae.dst_addr_hi = 0;
573 dmae.len = len32;
574
575 /* issue the command and wait for completion */
576 bnx2x_issue_dmae_with_comp(bp, &dmae);
577 }
578
579 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
580 {
581 struct dmae_command dmae;
582
583 if (!bp->dmae_ready) {
584 u32 *data = bnx2x_sp(bp, wb_data[0]);
585 int i;
586
587 if (CHIP_IS_E1(bp))
588 for (i = 0; i < len32; i++)
589 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
590 else
591 for (i = 0; i < len32; i++)
592 data[i] = REG_RD(bp, src_addr + i*4);
593
594 return;
595 }
596
597 /* set opcode and fixed command fields */
598 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
599
600 /* fill in addresses and len */
601 dmae.src_addr_lo = src_addr >> 2;
602 dmae.src_addr_hi = 0;
603 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
604 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
605 dmae.len = len32;
606
607 /* issue the command and wait for completion */
608 bnx2x_issue_dmae_with_comp(bp, &dmae);
609 }
610
611 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
612 u32 addr, u32 len)
613 {
614 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
615 int offset = 0;
616
617 while (len > dmae_wr_max) {
618 bnx2x_write_dmae(bp, phys_addr + offset,
619 addr + offset, dmae_wr_max);
620 offset += dmae_wr_max * 4;
621 len -= dmae_wr_max;
622 }
623
624 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
625 }
626
627 static int bnx2x_mc_assert(struct bnx2x *bp)
628 {
629 char last_idx;
630 int i, rc = 0;
631 u32 row0, row1, row2, row3;
632
633 /* XSTORM */
634 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
635 XSTORM_ASSERT_LIST_INDEX_OFFSET);
636 if (last_idx)
637 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
638
639 /* print the asserts */
640 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
641
642 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
643 XSTORM_ASSERT_LIST_OFFSET(i));
644 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
645 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
646 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
647 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
648 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
649 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
650
651 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
652 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
653 i, row3, row2, row1, row0);
654 rc++;
655 } else {
656 break;
657 }
658 }
659
660 /* TSTORM */
661 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
662 TSTORM_ASSERT_LIST_INDEX_OFFSET);
663 if (last_idx)
664 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
665
666 /* print the asserts */
667 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
668
669 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
670 TSTORM_ASSERT_LIST_OFFSET(i));
671 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
672 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
673 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
674 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
675 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
676 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
677
678 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
679 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
680 i, row3, row2, row1, row0);
681 rc++;
682 } else {
683 break;
684 }
685 }
686
687 /* CSTORM */
688 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
689 CSTORM_ASSERT_LIST_INDEX_OFFSET);
690 if (last_idx)
691 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
692
693 /* print the asserts */
694 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
695
696 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
697 CSTORM_ASSERT_LIST_OFFSET(i));
698 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
699 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
700 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
701 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
702 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
703 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
704
705 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
706 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
707 i, row3, row2, row1, row0);
708 rc++;
709 } else {
710 break;
711 }
712 }
713
714 /* USTORM */
715 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
716 USTORM_ASSERT_LIST_INDEX_OFFSET);
717 if (last_idx)
718 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
719
720 /* print the asserts */
721 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
722
723 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
724 USTORM_ASSERT_LIST_OFFSET(i));
725 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
726 USTORM_ASSERT_LIST_OFFSET(i) + 4);
727 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
728 USTORM_ASSERT_LIST_OFFSET(i) + 8);
729 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
730 USTORM_ASSERT_LIST_OFFSET(i) + 12);
731
732 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
733 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
734 i, row3, row2, row1, row0);
735 rc++;
736 } else {
737 break;
738 }
739 }
740
741 return rc;
742 }
743
744 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
745 {
746 u32 addr, val;
747 u32 mark, offset;
748 __be32 data[9];
749 int word;
750 u32 trace_shmem_base;
751 if (BP_NOMCP(bp)) {
752 BNX2X_ERR("NO MCP - can not dump\n");
753 return;
754 }
755 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
756 (bp->common.bc_ver & 0xff0000) >> 16,
757 (bp->common.bc_ver & 0xff00) >> 8,
758 (bp->common.bc_ver & 0xff));
759
760 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
761 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
762 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
763
764 if (BP_PATH(bp) == 0)
765 trace_shmem_base = bp->common.shmem_base;
766 else
767 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
768 addr = trace_shmem_base - 0x800;
769
770 /* validate TRCB signature */
771 mark = REG_RD(bp, addr);
772 if (mark != MFW_TRACE_SIGNATURE) {
773 BNX2X_ERR("Trace buffer signature is missing.");
774 return ;
775 }
776
777 /* read cyclic buffer pointer */
778 addr += 4;
779 mark = REG_RD(bp, addr);
780 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
781 + ((mark + 0x3) & ~0x3) - 0x08000000;
782 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
783
784 printk("%s", lvl);
785
786 /* dump buffer after the mark */
787 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
788 for (word = 0; word < 8; word++)
789 data[word] = htonl(REG_RD(bp, offset + 4*word));
790 data[8] = 0x0;
791 pr_cont("%s", (char *)data);
792 }
793
794 /* dump buffer before the mark */
795 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
796 for (word = 0; word < 8; word++)
797 data[word] = htonl(REG_RD(bp, offset + 4*word));
798 data[8] = 0x0;
799 pr_cont("%s", (char *)data);
800 }
801 printk("%s" "end of fw dump\n", lvl);
802 }
803
804 static void bnx2x_fw_dump(struct bnx2x *bp)
805 {
806 bnx2x_fw_dump_lvl(bp, KERN_ERR);
807 }
808
809 static void bnx2x_hc_int_disable(struct bnx2x *bp)
810 {
811 int port = BP_PORT(bp);
812 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
813 u32 val = REG_RD(bp, addr);
814
815 /* in E1 we must use only PCI configuration space to disable
816 * MSI/MSIX capablility
817 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
818 */
819 if (CHIP_IS_E1(bp)) {
820 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
821 * Use mask register to prevent from HC sending interrupts
822 * after we exit the function
823 */
824 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
825
826 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
827 HC_CONFIG_0_REG_INT_LINE_EN_0 |
828 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
829 } else
830 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
831 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
832 HC_CONFIG_0_REG_INT_LINE_EN_0 |
833 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
834
835 DP(NETIF_MSG_IFDOWN,
836 "write %x to HC %d (addr 0x%x)\n",
837 val, port, addr);
838
839 /* flush all outstanding writes */
840 mmiowb();
841
842 REG_WR(bp, addr, val);
843 if (REG_RD(bp, addr) != val)
844 BNX2X_ERR("BUG! proper val not read from IGU!\n");
845 }
846
847 static void bnx2x_igu_int_disable(struct bnx2x *bp)
848 {
849 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
850
851 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
852 IGU_PF_CONF_INT_LINE_EN |
853 IGU_PF_CONF_ATTN_BIT_EN);
854
855 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
856
857 /* flush all outstanding writes */
858 mmiowb();
859
860 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
861 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
862 BNX2X_ERR("BUG! proper val not read from IGU!\n");
863 }
864
865 static void bnx2x_int_disable(struct bnx2x *bp)
866 {
867 if (bp->common.int_block == INT_BLOCK_HC)
868 bnx2x_hc_int_disable(bp);
869 else
870 bnx2x_igu_int_disable(bp);
871 }
872
873 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
874 {
875 int i;
876 u16 j;
877 struct hc_sp_status_block_data sp_sb_data;
878 int func = BP_FUNC(bp);
879 #ifdef BNX2X_STOP_ON_ERROR
880 u16 start = 0, end = 0;
881 u8 cos;
882 #endif
883 if (disable_int)
884 bnx2x_int_disable(bp);
885
886 bp->stats_state = STATS_STATE_DISABLED;
887 bp->eth_stats.unrecoverable_error++;
888 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
889
890 BNX2X_ERR("begin crash dump -----------------\n");
891
892 /* Indices */
893 /* Common */
894 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
895 bp->def_idx, bp->def_att_idx, bp->attn_state,
896 bp->spq_prod_idx, bp->stats_counter);
897 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
898 bp->def_status_blk->atten_status_block.attn_bits,
899 bp->def_status_blk->atten_status_block.attn_bits_ack,
900 bp->def_status_blk->atten_status_block.status_block_id,
901 bp->def_status_blk->atten_status_block.attn_bits_index);
902 BNX2X_ERR(" def (");
903 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
904 pr_cont("0x%x%s",
905 bp->def_status_blk->sp_sb.index_values[i],
906 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
907
908 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
909 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
910 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
911 i*sizeof(u32));
912
913 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid,
920 sp_sb_data.state);
921
922
923 for_each_eth_queue(bp, i) {
924 struct bnx2x_fastpath *fp = &bp->fp[i];
925 int loop;
926 struct hc_status_block_data_e2 sb_data_e2;
927 struct hc_status_block_data_e1x sb_data_e1x;
928 struct hc_status_block_sm *hc_sm_p =
929 CHIP_IS_E1x(bp) ?
930 sb_data_e1x.common.state_machine :
931 sb_data_e2.common.state_machine;
932 struct hc_index_data *hc_index_p =
933 CHIP_IS_E1x(bp) ?
934 sb_data_e1x.index_data :
935 sb_data_e2.index_data;
936 u8 data_size, cos;
937 u32 *sb_data_p;
938 struct bnx2x_fp_txdata txdata;
939
940 /* Rx */
941 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
942 i, fp->rx_bd_prod, fp->rx_bd_cons,
943 fp->rx_comp_prod,
944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
946 fp->rx_sge_prod, fp->last_max_sge,
947 le16_to_cpu(fp->fp_hc_idx));
948
949 /* Tx */
950 for_each_cos_in_tx_queue(fp, cos)
951 {
952 txdata = *fp->txdata_ptr[cos];
953 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
954 i, txdata.tx_pkt_prod,
955 txdata.tx_pkt_cons, txdata.tx_bd_prod,
956 txdata.tx_bd_cons,
957 le16_to_cpu(*txdata.tx_cons_sb));
958 }
959
960 loop = CHIP_IS_E1x(bp) ?
961 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
962
963 /* host sb data */
964
965 if (IS_FCOE_FP(fp))
966 continue;
967
968 BNX2X_ERR(" run indexes (");
969 for (j = 0; j < HC_SB_MAX_SM; j++)
970 pr_cont("0x%x%s",
971 fp->sb_running_index[j],
972 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
973
974 BNX2X_ERR(" indexes (");
975 for (j = 0; j < loop; j++)
976 pr_cont("0x%x%s",
977 fp->sb_index_values[j],
978 (j == loop - 1) ? ")" : " ");
979 /* fw sb data */
980 data_size = CHIP_IS_E1x(bp) ?
981 sizeof(struct hc_status_block_data_e1x) :
982 sizeof(struct hc_status_block_data_e2);
983 data_size /= sizeof(u32);
984 sb_data_p = CHIP_IS_E1x(bp) ?
985 (u32 *)&sb_data_e1x :
986 (u32 *)&sb_data_e2;
987 /* copy sb data in here */
988 for (j = 0; j < data_size; j++)
989 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
990 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
991 j * sizeof(u32));
992
993 if (!CHIP_IS_E1x(bp)) {
994 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
995 sb_data_e2.common.p_func.pf_id,
996 sb_data_e2.common.p_func.vf_id,
997 sb_data_e2.common.p_func.vf_valid,
998 sb_data_e2.common.p_func.vnic_id,
999 sb_data_e2.common.same_igu_sb_1b,
1000 sb_data_e2.common.state);
1001 } else {
1002 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1003 sb_data_e1x.common.p_func.pf_id,
1004 sb_data_e1x.common.p_func.vf_id,
1005 sb_data_e1x.common.p_func.vf_valid,
1006 sb_data_e1x.common.p_func.vnic_id,
1007 sb_data_e1x.common.same_igu_sb_1b,
1008 sb_data_e1x.common.state);
1009 }
1010
1011 /* SB_SMs data */
1012 for (j = 0; j < HC_SB_MAX_SM; j++) {
1013 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1014 j, hc_sm_p[j].__flags,
1015 hc_sm_p[j].igu_sb_id,
1016 hc_sm_p[j].igu_seg_id,
1017 hc_sm_p[j].time_to_expire,
1018 hc_sm_p[j].timer_value);
1019 }
1020
1021 /* Indecies data */
1022 for (j = 0; j < loop; j++) {
1023 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1024 hc_index_p[j].flags,
1025 hc_index_p[j].timeout);
1026 }
1027 }
1028
1029 #ifdef BNX2X_STOP_ON_ERROR
1030
1031 /* event queue */
1032 for (i = 0; i < NUM_EQ_DESC; i++) {
1033 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1034
1035 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1036 i, bp->eq_ring[i].message.opcode,
1037 bp->eq_ring[i].message.error);
1038 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1039 }
1040
1041 /* Rings */
1042 /* Rx */
1043 for_each_valid_rx_queue(bp, i) {
1044 struct bnx2x_fastpath *fp = &bp->fp[i];
1045
1046 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1047 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1048 for (j = start; j != end; j = RX_BD(j + 1)) {
1049 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1050 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1051
1052 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1053 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1054 }
1055
1056 start = RX_SGE(fp->rx_sge_prod);
1057 end = RX_SGE(fp->last_max_sge);
1058 for (j = start; j != end; j = RX_SGE(j + 1)) {
1059 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1060 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1061
1062 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1063 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1064 }
1065
1066 start = RCQ_BD(fp->rx_comp_cons - 10);
1067 end = RCQ_BD(fp->rx_comp_cons + 503);
1068 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1069 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1070
1071 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1072 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1073 }
1074 }
1075
1076 /* Tx */
1077 for_each_valid_tx_queue(bp, i) {
1078 struct bnx2x_fastpath *fp = &bp->fp[i];
1079 for_each_cos_in_tx_queue(fp, cos) {
1080 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1081
1082 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1083 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1084 for (j = start; j != end; j = TX_BD(j + 1)) {
1085 struct sw_tx_bd *sw_bd =
1086 &txdata->tx_buf_ring[j];
1087
1088 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1089 i, cos, j, sw_bd->skb,
1090 sw_bd->first_bd);
1091 }
1092
1093 start = TX_BD(txdata->tx_bd_cons - 10);
1094 end = TX_BD(txdata->tx_bd_cons + 254);
1095 for (j = start; j != end; j = TX_BD(j + 1)) {
1096 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1097
1098 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1099 i, cos, j, tx_bd[0], tx_bd[1],
1100 tx_bd[2], tx_bd[3]);
1101 }
1102 }
1103 }
1104 #endif
1105 bnx2x_fw_dump(bp);
1106 bnx2x_mc_assert(bp);
1107 BNX2X_ERR("end crash dump -----------------\n");
1108 }
1109
1110 /*
1111 * FLR Support for E2
1112 *
1113 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1114 * initialization.
1115 */
1116 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1117 #define FLR_WAIT_INTERVAL 50 /* usec */
1118 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1119
1120 struct pbf_pN_buf_regs {
1121 int pN;
1122 u32 init_crd;
1123 u32 crd;
1124 u32 crd_freed;
1125 };
1126
1127 struct pbf_pN_cmd_regs {
1128 int pN;
1129 u32 lines_occup;
1130 u32 lines_freed;
1131 };
1132
1133 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1134 struct pbf_pN_buf_regs *regs,
1135 u32 poll_count)
1136 {
1137 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1138 u32 cur_cnt = poll_count;
1139
1140 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1141 crd = crd_start = REG_RD(bp, regs->crd);
1142 init_crd = REG_RD(bp, regs->init_crd);
1143
1144 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1145 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1146 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1147
1148 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1149 (init_crd - crd_start))) {
1150 if (cur_cnt--) {
1151 udelay(FLR_WAIT_INTERVAL);
1152 crd = REG_RD(bp, regs->crd);
1153 crd_freed = REG_RD(bp, regs->crd_freed);
1154 } else {
1155 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1156 regs->pN);
1157 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1158 regs->pN, crd);
1159 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1160 regs->pN, crd_freed);
1161 break;
1162 }
1163 }
1164 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1165 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1166 }
1167
1168 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1169 struct pbf_pN_cmd_regs *regs,
1170 u32 poll_count)
1171 {
1172 u32 occup, to_free, freed, freed_start;
1173 u32 cur_cnt = poll_count;
1174
1175 occup = to_free = REG_RD(bp, regs->lines_occup);
1176 freed = freed_start = REG_RD(bp, regs->lines_freed);
1177
1178 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1179 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1180
1181 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1182 if (cur_cnt--) {
1183 udelay(FLR_WAIT_INTERVAL);
1184 occup = REG_RD(bp, regs->lines_occup);
1185 freed = REG_RD(bp, regs->lines_freed);
1186 } else {
1187 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1188 regs->pN);
1189 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1190 regs->pN, occup);
1191 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1192 regs->pN, freed);
1193 break;
1194 }
1195 }
1196 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1197 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1198 }
1199
1200 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1201 u32 expected, u32 poll_count)
1202 {
1203 u32 cur_cnt = poll_count;
1204 u32 val;
1205
1206 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1207 udelay(FLR_WAIT_INTERVAL);
1208
1209 return val;
1210 }
1211
1212 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1213 char *msg, u32 poll_cnt)
1214 {
1215 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1216 if (val != 0) {
1217 BNX2X_ERR("%s usage count=%d\n", msg, val);
1218 return 1;
1219 }
1220 return 0;
1221 }
1222
1223 /* Common routines with VF FLR cleanup */
1224 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1225 {
1226 /* adjust polling timeout */
1227 if (CHIP_REV_IS_EMUL(bp))
1228 return FLR_POLL_CNT * 2000;
1229
1230 if (CHIP_REV_IS_FPGA(bp))
1231 return FLR_POLL_CNT * 120;
1232
1233 return FLR_POLL_CNT;
1234 }
1235
1236 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1237 {
1238 struct pbf_pN_cmd_regs cmd_regs[] = {
1239 {0, (CHIP_IS_E3B0(bp)) ?
1240 PBF_REG_TQ_OCCUPANCY_Q0 :
1241 PBF_REG_P0_TQ_OCCUPANCY,
1242 (CHIP_IS_E3B0(bp)) ?
1243 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1244 PBF_REG_P0_TQ_LINES_FREED_CNT},
1245 {1, (CHIP_IS_E3B0(bp)) ?
1246 PBF_REG_TQ_OCCUPANCY_Q1 :
1247 PBF_REG_P1_TQ_OCCUPANCY,
1248 (CHIP_IS_E3B0(bp)) ?
1249 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1250 PBF_REG_P1_TQ_LINES_FREED_CNT},
1251 {4, (CHIP_IS_E3B0(bp)) ?
1252 PBF_REG_TQ_OCCUPANCY_LB_Q :
1253 PBF_REG_P4_TQ_OCCUPANCY,
1254 (CHIP_IS_E3B0(bp)) ?
1255 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1256 PBF_REG_P4_TQ_LINES_FREED_CNT}
1257 };
1258
1259 struct pbf_pN_buf_regs buf_regs[] = {
1260 {0, (CHIP_IS_E3B0(bp)) ?
1261 PBF_REG_INIT_CRD_Q0 :
1262 PBF_REG_P0_INIT_CRD ,
1263 (CHIP_IS_E3B0(bp)) ?
1264 PBF_REG_CREDIT_Q0 :
1265 PBF_REG_P0_CREDIT,
1266 (CHIP_IS_E3B0(bp)) ?
1267 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1268 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1269 {1, (CHIP_IS_E3B0(bp)) ?
1270 PBF_REG_INIT_CRD_Q1 :
1271 PBF_REG_P1_INIT_CRD,
1272 (CHIP_IS_E3B0(bp)) ?
1273 PBF_REG_CREDIT_Q1 :
1274 PBF_REG_P1_CREDIT,
1275 (CHIP_IS_E3B0(bp)) ?
1276 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1277 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1278 {4, (CHIP_IS_E3B0(bp)) ?
1279 PBF_REG_INIT_CRD_LB_Q :
1280 PBF_REG_P4_INIT_CRD,
1281 (CHIP_IS_E3B0(bp)) ?
1282 PBF_REG_CREDIT_LB_Q :
1283 PBF_REG_P4_CREDIT,
1284 (CHIP_IS_E3B0(bp)) ?
1285 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1286 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1287 };
1288
1289 int i;
1290
1291 /* Verify the command queues are flushed P0, P1, P4 */
1292 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1293 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1294
1295
1296 /* Verify the transmission buffers are flushed P0, P1, P4 */
1297 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1298 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1299 }
1300
1301 #define OP_GEN_PARAM(param) \
1302 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1303
1304 #define OP_GEN_TYPE(type) \
1305 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1306
1307 #define OP_GEN_AGG_VECT(index) \
1308 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1309
1310
1311 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1312 {
1313 u32 op_gen_command = 0;
1314
1315 u32 comp_addr = BAR_CSTRORM_INTMEM +
1316 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1317 int ret = 0;
1318
1319 if (REG_RD(bp, comp_addr)) {
1320 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1321 return 1;
1322 }
1323
1324 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1325 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1326 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1327 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1328
1329 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1330 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1331
1332 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1333 BNX2X_ERR("FW final cleanup did not succeed\n");
1334 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1335 (REG_RD(bp, comp_addr)));
1336 bnx2x_panic();
1337 return 1;
1338 }
1339 /* Zero completion for nxt FLR */
1340 REG_WR(bp, comp_addr, 0);
1341
1342 return ret;
1343 }
1344
1345 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1346 {
1347 u16 status;
1348
1349 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1350 return status & PCI_EXP_DEVSTA_TRPND;
1351 }
1352
1353 /* PF FLR specific routines
1354 */
1355 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1356 {
1357
1358 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1359 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1360 CFC_REG_NUM_LCIDS_INSIDE_PF,
1361 "CFC PF usage counter timed out",
1362 poll_cnt))
1363 return 1;
1364
1365
1366 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1367 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1368 DORQ_REG_PF_USAGE_CNT,
1369 "DQ PF usage counter timed out",
1370 poll_cnt))
1371 return 1;
1372
1373 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1374 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1375 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1376 "QM PF usage counter timed out",
1377 poll_cnt))
1378 return 1;
1379
1380 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1381 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1382 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1383 "Timers VNIC usage counter timed out",
1384 poll_cnt))
1385 return 1;
1386 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1387 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1388 "Timers NUM_SCANS usage counter timed out",
1389 poll_cnt))
1390 return 1;
1391
1392 /* Wait DMAE PF usage counter to zero */
1393 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1394 dmae_reg_go_c[INIT_DMAE_C(bp)],
1395 "DMAE dommand register timed out",
1396 poll_cnt))
1397 return 1;
1398
1399 return 0;
1400 }
1401
1402 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1403 {
1404 u32 val;
1405
1406 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1407 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1408
1409 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1410 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1411
1412 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1413 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1414
1415 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1416 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1417
1418 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1419 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1420
1421 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1422 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1423
1424 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1425 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1426
1427 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1428 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1429 val);
1430 }
1431
1432 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1433 {
1434 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1435
1436 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1437
1438 /* Re-enable PF target read access */
1439 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1440
1441 /* Poll HW usage counters */
1442 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1443 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1444 return -EBUSY;
1445
1446 /* Zero the igu 'trailing edge' and 'leading edge' */
1447
1448 /* Send the FW cleanup command */
1449 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1450 return -EBUSY;
1451
1452 /* ATC cleanup */
1453
1454 /* Verify TX hw is flushed */
1455 bnx2x_tx_hw_flushed(bp, poll_cnt);
1456
1457 /* Wait 100ms (not adjusted according to platform) */
1458 msleep(100);
1459
1460 /* Verify no pending pci transactions */
1461 if (bnx2x_is_pcie_pending(bp->pdev))
1462 BNX2X_ERR("PCIE Transactions still pending\n");
1463
1464 /* Debug */
1465 bnx2x_hw_enable_status(bp);
1466
1467 /*
1468 * Master enable - Due to WB DMAE writes performed before this
1469 * register is re-initialized as part of the regular function init
1470 */
1471 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1472
1473 return 0;
1474 }
1475
1476 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1477 {
1478 int port = BP_PORT(bp);
1479 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1480 u32 val = REG_RD(bp, addr);
1481 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1482 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1483 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1484
1485 if (msix) {
1486 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1487 HC_CONFIG_0_REG_INT_LINE_EN_0);
1488 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1489 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1490 if (single_msix)
1491 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1492 } else if (msi) {
1493 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1494 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1495 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1496 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1497 } else {
1498 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1499 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1500 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1501 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1502
1503 if (!CHIP_IS_E1(bp)) {
1504 DP(NETIF_MSG_IFUP,
1505 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1506
1507 REG_WR(bp, addr, val);
1508
1509 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1510 }
1511 }
1512
1513 if (CHIP_IS_E1(bp))
1514 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1515
1516 DP(NETIF_MSG_IFUP,
1517 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1518 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1519
1520 REG_WR(bp, addr, val);
1521 /*
1522 * Ensure that HC_CONFIG is written before leading/trailing edge config
1523 */
1524 mmiowb();
1525 barrier();
1526
1527 if (!CHIP_IS_E1(bp)) {
1528 /* init leading/trailing edge */
1529 if (IS_MF(bp)) {
1530 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1531 if (bp->port.pmf)
1532 /* enable nig and gpio3 attention */
1533 val |= 0x1100;
1534 } else
1535 val = 0xffff;
1536
1537 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1538 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1539 }
1540
1541 /* Make sure that interrupts are indeed enabled from here on */
1542 mmiowb();
1543 }
1544
1545 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1546 {
1547 u32 val;
1548 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1549 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1550 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1551
1552 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1553
1554 if (msix) {
1555 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1556 IGU_PF_CONF_SINGLE_ISR_EN);
1557 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1558 IGU_PF_CONF_ATTN_BIT_EN);
1559
1560 if (single_msix)
1561 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1562 } else if (msi) {
1563 val &= ~IGU_PF_CONF_INT_LINE_EN;
1564 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1565 IGU_PF_CONF_ATTN_BIT_EN |
1566 IGU_PF_CONF_SINGLE_ISR_EN);
1567 } else {
1568 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1569 val |= (IGU_PF_CONF_INT_LINE_EN |
1570 IGU_PF_CONF_ATTN_BIT_EN |
1571 IGU_PF_CONF_SINGLE_ISR_EN);
1572 }
1573
1574 /* Clean previous status - need to configure igu prior to ack*/
1575 if ((!msix) || single_msix) {
1576 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1577 bnx2x_ack_int(bp);
1578 }
1579
1580 val |= IGU_PF_CONF_FUNC_EN;
1581
1582 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1583 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1584
1585 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1586
1587 if (val & IGU_PF_CONF_INT_LINE_EN)
1588 pci_intx(bp->pdev, true);
1589
1590 barrier();
1591
1592 /* init leading/trailing edge */
1593 if (IS_MF(bp)) {
1594 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1595 if (bp->port.pmf)
1596 /* enable nig and gpio3 attention */
1597 val |= 0x1100;
1598 } else
1599 val = 0xffff;
1600
1601 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1602 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1603
1604 /* Make sure that interrupts are indeed enabled from here on */
1605 mmiowb();
1606 }
1607
1608 void bnx2x_int_enable(struct bnx2x *bp)
1609 {
1610 if (bp->common.int_block == INT_BLOCK_HC)
1611 bnx2x_hc_int_enable(bp);
1612 else
1613 bnx2x_igu_int_enable(bp);
1614 }
1615
1616 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1617 {
1618 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1619 int i, offset;
1620
1621 if (disable_hw)
1622 /* prevent the HW from sending interrupts */
1623 bnx2x_int_disable(bp);
1624
1625 /* make sure all ISRs are done */
1626 if (msix) {
1627 synchronize_irq(bp->msix_table[0].vector);
1628 offset = 1;
1629 if (CNIC_SUPPORT(bp))
1630 offset++;
1631 for_each_eth_queue(bp, i)
1632 synchronize_irq(bp->msix_table[offset++].vector);
1633 } else
1634 synchronize_irq(bp->pdev->irq);
1635
1636 /* make sure sp_task is not running */
1637 cancel_delayed_work(&bp->sp_task);
1638 cancel_delayed_work(&bp->period_task);
1639 flush_workqueue(bnx2x_wq);
1640 }
1641
1642 /* fast path */
1643
1644 /*
1645 * General service functions
1646 */
1647
1648 /* Return true if succeeded to acquire the lock */
1649 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1650 {
1651 u32 lock_status;
1652 u32 resource_bit = (1 << resource);
1653 int func = BP_FUNC(bp);
1654 u32 hw_lock_control_reg;
1655
1656 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1657 "Trying to take a lock on resource %d\n", resource);
1658
1659 /* Validating that the resource is within range */
1660 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1661 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1662 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1663 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1664 return false;
1665 }
1666
1667 if (func <= 5)
1668 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1669 else
1670 hw_lock_control_reg =
1671 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1672
1673 /* Try to acquire the lock */
1674 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1675 lock_status = REG_RD(bp, hw_lock_control_reg);
1676 if (lock_status & resource_bit)
1677 return true;
1678
1679 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1680 "Failed to get a lock on resource %d\n", resource);
1681 return false;
1682 }
1683
1684 /**
1685 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1686 *
1687 * @bp: driver handle
1688 *
1689 * Returns the recovery leader resource id according to the engine this function
1690 * belongs to. Currently only only 2 engines is supported.
1691 */
1692 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1693 {
1694 if (BP_PATH(bp))
1695 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1696 else
1697 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1698 }
1699
1700 /**
1701 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1702 *
1703 * @bp: driver handle
1704 *
1705 * Tries to acquire a leader lock for current engine.
1706 */
1707 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1708 {
1709 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1710 }
1711
1712 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1713
1714 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1715 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1716 {
1717 /* Set the interrupt occurred bit for the sp-task to recognize it
1718 * must ack the interrupt and transition according to the IGU
1719 * state machine.
1720 */
1721 atomic_set(&bp->interrupt_occurred, 1);
1722
1723 /* The sp_task must execute only after this bit
1724 * is set, otherwise we will get out of sync and miss all
1725 * further interrupts. Hence, the barrier.
1726 */
1727 smp_wmb();
1728
1729 /* schedule sp_task to workqueue */
1730 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1731 }
1732
1733 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1734 {
1735 struct bnx2x *bp = fp->bp;
1736 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1737 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1738 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1739 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1740
1741 DP(BNX2X_MSG_SP,
1742 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1743 fp->index, cid, command, bp->state,
1744 rr_cqe->ramrod_cqe.ramrod_type);
1745
1746 /* If cid is within VF range, replace the slowpath object with the
1747 * one corresponding to this VF
1748 */
1749 if (cid >= BNX2X_FIRST_VF_CID &&
1750 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1751 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1752
1753 switch (command) {
1754 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1755 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1756 drv_cmd = BNX2X_Q_CMD_UPDATE;
1757 break;
1758
1759 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1760 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1761 drv_cmd = BNX2X_Q_CMD_SETUP;
1762 break;
1763
1764 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1765 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1766 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1767 break;
1768
1769 case (RAMROD_CMD_ID_ETH_HALT):
1770 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1771 drv_cmd = BNX2X_Q_CMD_HALT;
1772 break;
1773
1774 case (RAMROD_CMD_ID_ETH_TERMINATE):
1775 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1776 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1777 break;
1778
1779 case (RAMROD_CMD_ID_ETH_EMPTY):
1780 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1781 drv_cmd = BNX2X_Q_CMD_EMPTY;
1782 break;
1783
1784 default:
1785 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1786 command, fp->index);
1787 return;
1788 }
1789
1790 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1791 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1792 /* q_obj->complete_cmd() failure means that this was
1793 * an unexpected completion.
1794 *
1795 * In this case we don't want to increase the bp->spq_left
1796 * because apparently we haven't sent this command the first
1797 * place.
1798 */
1799 #ifdef BNX2X_STOP_ON_ERROR
1800 bnx2x_panic();
1801 #else
1802 return;
1803 #endif
1804 /* SRIOV: reschedule any 'in_progress' operations */
1805 bnx2x_iov_sp_event(bp, cid, true);
1806
1807 smp_mb__before_atomic_inc();
1808 atomic_inc(&bp->cq_spq_left);
1809 /* push the change in bp->spq_left and towards the memory */
1810 smp_mb__after_atomic_inc();
1811
1812 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1813
1814 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1815 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1816 /* if Q update ramrod is completed for last Q in AFEX vif set
1817 * flow, then ACK MCP at the end
1818 *
1819 * mark pending ACK to MCP bit.
1820 * prevent case that both bits are cleared.
1821 * At the end of load/unload driver checks that
1822 * sp_state is cleared, and this order prevents
1823 * races
1824 */
1825 smp_mb__before_clear_bit();
1826 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1827 wmb();
1828 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1829 smp_mb__after_clear_bit();
1830
1831 /* schedule the sp task as mcp ack is required */
1832 bnx2x_schedule_sp_task(bp);
1833 }
1834
1835 return;
1836 }
1837
1838 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1839 {
1840 struct bnx2x *bp = netdev_priv(dev_instance);
1841 u16 status = bnx2x_ack_int(bp);
1842 u16 mask;
1843 int i;
1844 u8 cos;
1845
1846 /* Return here if interrupt is shared and it's not for us */
1847 if (unlikely(status == 0)) {
1848 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1849 return IRQ_NONE;
1850 }
1851 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1852
1853 #ifdef BNX2X_STOP_ON_ERROR
1854 if (unlikely(bp->panic))
1855 return IRQ_HANDLED;
1856 #endif
1857
1858 for_each_eth_queue(bp, i) {
1859 struct bnx2x_fastpath *fp = &bp->fp[i];
1860
1861 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1862 if (status & mask) {
1863 /* Handle Rx or Tx according to SB id */
1864 prefetch(fp->rx_cons_sb);
1865 for_each_cos_in_tx_queue(fp, cos)
1866 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1867 prefetch(&fp->sb_running_index[SM_RX_ID]);
1868 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1869 status &= ~mask;
1870 }
1871 }
1872
1873 if (CNIC_SUPPORT(bp)) {
1874 mask = 0x2;
1875 if (status & (mask | 0x1)) {
1876 struct cnic_ops *c_ops = NULL;
1877
1878 rcu_read_lock();
1879 c_ops = rcu_dereference(bp->cnic_ops);
1880 if (c_ops && (bp->cnic_eth_dev.drv_state &
1881 CNIC_DRV_STATE_HANDLES_IRQ))
1882 c_ops->cnic_handler(bp->cnic_data, NULL);
1883 rcu_read_unlock();
1884
1885 status &= ~mask;
1886 }
1887 }
1888
1889 if (unlikely(status & 0x1)) {
1890
1891 /* schedule sp task to perform default status block work, ack
1892 * attentions and enable interrupts.
1893 */
1894 bnx2x_schedule_sp_task(bp);
1895
1896 status &= ~0x1;
1897 if (!status)
1898 return IRQ_HANDLED;
1899 }
1900
1901 if (unlikely(status))
1902 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1903 status);
1904
1905 return IRQ_HANDLED;
1906 }
1907
1908 /* Link */
1909
1910 /*
1911 * General service functions
1912 */
1913
1914 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1915 {
1916 u32 lock_status;
1917 u32 resource_bit = (1 << resource);
1918 int func = BP_FUNC(bp);
1919 u32 hw_lock_control_reg;
1920 int cnt;
1921
1922 /* Validating that the resource is within range */
1923 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1924 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1925 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1926 return -EINVAL;
1927 }
1928
1929 if (func <= 5) {
1930 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1931 } else {
1932 hw_lock_control_reg =
1933 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1934 }
1935
1936 /* Validating that the resource is not already taken */
1937 lock_status = REG_RD(bp, hw_lock_control_reg);
1938 if (lock_status & resource_bit) {
1939 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1940 lock_status, resource_bit);
1941 return -EEXIST;
1942 }
1943
1944 /* Try for 5 second every 5ms */
1945 for (cnt = 0; cnt < 1000; cnt++) {
1946 /* Try to acquire the lock */
1947 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1948 lock_status = REG_RD(bp, hw_lock_control_reg);
1949 if (lock_status & resource_bit)
1950 return 0;
1951
1952 msleep(5);
1953 }
1954 BNX2X_ERR("Timeout\n");
1955 return -EAGAIN;
1956 }
1957
1958 int bnx2x_release_leader_lock(struct bnx2x *bp)
1959 {
1960 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1961 }
1962
1963 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1964 {
1965 u32 lock_status;
1966 u32 resource_bit = (1 << resource);
1967 int func = BP_FUNC(bp);
1968 u32 hw_lock_control_reg;
1969
1970 /* Validating that the resource is within range */
1971 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1972 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1973 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1974 return -EINVAL;
1975 }
1976
1977 if (func <= 5) {
1978 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1979 } else {
1980 hw_lock_control_reg =
1981 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1982 }
1983
1984 /* Validating that the resource is currently taken */
1985 lock_status = REG_RD(bp, hw_lock_control_reg);
1986 if (!(lock_status & resource_bit)) {
1987 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1988 lock_status, resource_bit);
1989 return -EFAULT;
1990 }
1991
1992 REG_WR(bp, hw_lock_control_reg, resource_bit);
1993 return 0;
1994 }
1995
1996
1997 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1998 {
1999 /* The GPIO should be swapped if swap register is set and active */
2000 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2001 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2002 int gpio_shift = gpio_num +
2003 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2004 u32 gpio_mask = (1 << gpio_shift);
2005 u32 gpio_reg;
2006 int value;
2007
2008 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2009 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2010 return -EINVAL;
2011 }
2012
2013 /* read GPIO value */
2014 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2015
2016 /* get the requested pin value */
2017 if ((gpio_reg & gpio_mask) == gpio_mask)
2018 value = 1;
2019 else
2020 value = 0;
2021
2022 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2023
2024 return value;
2025 }
2026
2027 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2028 {
2029 /* The GPIO should be swapped if swap register is set and active */
2030 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2031 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2032 int gpio_shift = gpio_num +
2033 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2034 u32 gpio_mask = (1 << gpio_shift);
2035 u32 gpio_reg;
2036
2037 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2038 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2039 return -EINVAL;
2040 }
2041
2042 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2043 /* read GPIO and mask except the float bits */
2044 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2045
2046 switch (mode) {
2047 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2048 DP(NETIF_MSG_LINK,
2049 "Set GPIO %d (shift %d) -> output low\n",
2050 gpio_num, gpio_shift);
2051 /* clear FLOAT and set CLR */
2052 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2053 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2054 break;
2055
2056 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2057 DP(NETIF_MSG_LINK,
2058 "Set GPIO %d (shift %d) -> output high\n",
2059 gpio_num, gpio_shift);
2060 /* clear FLOAT and set SET */
2061 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2062 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2063 break;
2064
2065 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2066 DP(NETIF_MSG_LINK,
2067 "Set GPIO %d (shift %d) -> input\n",
2068 gpio_num, gpio_shift);
2069 /* set FLOAT */
2070 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2071 break;
2072
2073 default:
2074 break;
2075 }
2076
2077 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2078 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2079
2080 return 0;
2081 }
2082
2083 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2084 {
2085 u32 gpio_reg = 0;
2086 int rc = 0;
2087
2088 /* Any port swapping should be handled by caller. */
2089
2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2091 /* read GPIO and mask except the float bits */
2092 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2093 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2094 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2095 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2096
2097 switch (mode) {
2098 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2099 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2100 /* set CLR */
2101 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2102 break;
2103
2104 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2105 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2106 /* set SET */
2107 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2108 break;
2109
2110 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2111 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2112 /* set FLOAT */
2113 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2114 break;
2115
2116 default:
2117 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2118 rc = -EINVAL;
2119 break;
2120 }
2121
2122 if (rc == 0)
2123 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2124
2125 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2126
2127 return rc;
2128 }
2129
2130 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2131 {
2132 /* The GPIO should be swapped if swap register is set and active */
2133 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2134 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2135 int gpio_shift = gpio_num +
2136 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2137 u32 gpio_mask = (1 << gpio_shift);
2138 u32 gpio_reg;
2139
2140 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2141 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2142 return -EINVAL;
2143 }
2144
2145 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2146 /* read GPIO int */
2147 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2148
2149 switch (mode) {
2150 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2151 DP(NETIF_MSG_LINK,
2152 "Clear GPIO INT %d (shift %d) -> output low\n",
2153 gpio_num, gpio_shift);
2154 /* clear SET and set CLR */
2155 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2156 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2157 break;
2158
2159 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2160 DP(NETIF_MSG_LINK,
2161 "Set GPIO INT %d (shift %d) -> output high\n",
2162 gpio_num, gpio_shift);
2163 /* clear CLR and set SET */
2164 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2165 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2166 break;
2167
2168 default:
2169 break;
2170 }
2171
2172 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2173 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2174
2175 return 0;
2176 }
2177
2178 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2179 {
2180 u32 spio_reg;
2181
2182 /* Only 2 SPIOs are configurable */
2183 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2184 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2185 return -EINVAL;
2186 }
2187
2188 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2189 /* read SPIO and mask except the float bits */
2190 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2191
2192 switch (mode) {
2193 case MISC_SPIO_OUTPUT_LOW:
2194 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2195 /* clear FLOAT and set CLR */
2196 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2197 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2198 break;
2199
2200 case MISC_SPIO_OUTPUT_HIGH:
2201 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2202 /* clear FLOAT and set SET */
2203 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2204 spio_reg |= (spio << MISC_SPIO_SET_POS);
2205 break;
2206
2207 case MISC_SPIO_INPUT_HI_Z:
2208 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2209 /* set FLOAT */
2210 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2211 break;
2212
2213 default:
2214 break;
2215 }
2216
2217 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2218 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2219
2220 return 0;
2221 }
2222
2223 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2224 {
2225 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2226 switch (bp->link_vars.ieee_fc &
2227 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2228 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2229 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2230 ADVERTISED_Pause);
2231 break;
2232
2233 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2234 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2235 ADVERTISED_Pause);
2236 break;
2237
2238 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2239 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2240 break;
2241
2242 default:
2243 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2244 ADVERTISED_Pause);
2245 break;
2246 }
2247 }
2248
2249 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2250 {
2251 /* Initialize link parameters structure variables
2252 * It is recommended to turn off RX FC for jumbo frames
2253 * for better performance
2254 */
2255 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2256 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2257 else
2258 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2259 }
2260
2261 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2262 {
2263 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2264 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2265
2266 if (!BP_NOMCP(bp)) {
2267 bnx2x_set_requested_fc(bp);
2268 bnx2x_acquire_phy_lock(bp);
2269
2270 if (load_mode == LOAD_DIAG) {
2271 struct link_params *lp = &bp->link_params;
2272 lp->loopback_mode = LOOPBACK_XGXS;
2273 /* do PHY loopback at 10G speed, if possible */
2274 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2275 if (lp->speed_cap_mask[cfx_idx] &
2276 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2277 lp->req_line_speed[cfx_idx] =
2278 SPEED_10000;
2279 else
2280 lp->req_line_speed[cfx_idx] =
2281 SPEED_1000;
2282 }
2283 }
2284
2285 if (load_mode == LOAD_LOOPBACK_EXT) {
2286 struct link_params *lp = &bp->link_params;
2287 lp->loopback_mode = LOOPBACK_EXT;
2288 }
2289
2290 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2291
2292 bnx2x_release_phy_lock(bp);
2293
2294 bnx2x_calc_fc_adv(bp);
2295
2296 if (bp->link_vars.link_up) {
2297 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2298 bnx2x_link_report(bp);
2299 }
2300 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2301 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2302 return rc;
2303 }
2304 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2305 return -EINVAL;
2306 }
2307
2308 void bnx2x_link_set(struct bnx2x *bp)
2309 {
2310 if (!BP_NOMCP(bp)) {
2311 bnx2x_acquire_phy_lock(bp);
2312 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2313 bnx2x_release_phy_lock(bp);
2314
2315 bnx2x_calc_fc_adv(bp);
2316 } else
2317 BNX2X_ERR("Bootcode is missing - can not set link\n");
2318 }
2319
2320 static void bnx2x__link_reset(struct bnx2x *bp)
2321 {
2322 if (!BP_NOMCP(bp)) {
2323 bnx2x_acquire_phy_lock(bp);
2324 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2325 bnx2x_release_phy_lock(bp);
2326 } else
2327 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2328 }
2329
2330 void bnx2x_force_link_reset(struct bnx2x *bp)
2331 {
2332 bnx2x_acquire_phy_lock(bp);
2333 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2334 bnx2x_release_phy_lock(bp);
2335 }
2336
2337 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2338 {
2339 u8 rc = 0;
2340
2341 if (!BP_NOMCP(bp)) {
2342 bnx2x_acquire_phy_lock(bp);
2343 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2344 is_serdes);
2345 bnx2x_release_phy_lock(bp);
2346 } else
2347 BNX2X_ERR("Bootcode is missing - can not test link\n");
2348
2349 return rc;
2350 }
2351
2352
2353 /* Calculates the sum of vn_min_rates.
2354 It's needed for further normalizing of the min_rates.
2355 Returns:
2356 sum of vn_min_rates.
2357 or
2358 0 - if all the min_rates are 0.
2359 In the later case fainess algorithm should be deactivated.
2360 If not all min_rates are zero then those that are zeroes will be set to 1.
2361 */
2362 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2363 struct cmng_init_input *input)
2364 {
2365 int all_zero = 1;
2366 int vn;
2367
2368 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2369 u32 vn_cfg = bp->mf_config[vn];
2370 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2371 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2372
2373 /* Skip hidden vns */
2374 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2375 vn_min_rate = 0;
2376 /* If min rate is zero - set it to 1 */
2377 else if (!vn_min_rate)
2378 vn_min_rate = DEF_MIN_RATE;
2379 else
2380 all_zero = 0;
2381
2382 input->vnic_min_rate[vn] = vn_min_rate;
2383 }
2384
2385 /* if ETS or all min rates are zeros - disable fairness */
2386 if (BNX2X_IS_ETS_ENABLED(bp)) {
2387 input->flags.cmng_enables &=
2388 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2389 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2390 } else if (all_zero) {
2391 input->flags.cmng_enables &=
2392 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2393 DP(NETIF_MSG_IFUP,
2394 "All MIN values are zeroes fairness will be disabled\n");
2395 } else
2396 input->flags.cmng_enables |=
2397 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2398 }
2399
2400 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2401 struct cmng_init_input *input)
2402 {
2403 u16 vn_max_rate;
2404 u32 vn_cfg = bp->mf_config[vn];
2405
2406 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2407 vn_max_rate = 0;
2408 else {
2409 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2410
2411 if (IS_MF_SI(bp)) {
2412 /* maxCfg in percents of linkspeed */
2413 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2414 } else /* SD modes */
2415 /* maxCfg is absolute in 100Mb units */
2416 vn_max_rate = maxCfg * 100;
2417 }
2418
2419 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2420
2421 input->vnic_max_rate[vn] = vn_max_rate;
2422 }
2423
2424
2425 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2426 {
2427 if (CHIP_REV_IS_SLOW(bp))
2428 return CMNG_FNS_NONE;
2429 if (IS_MF(bp))
2430 return CMNG_FNS_MINMAX;
2431
2432 return CMNG_FNS_NONE;
2433 }
2434
2435 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2436 {
2437 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2438
2439 if (BP_NOMCP(bp))
2440 return; /* what should be the default bvalue in this case */
2441
2442 /* For 2 port configuration the absolute function number formula
2443 * is:
2444 * abs_func = 2 * vn + BP_PORT + BP_PATH
2445 *
2446 * and there are 4 functions per port
2447 *
2448 * For 4 port configuration it is
2449 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2450 *
2451 * and there are 2 functions per port
2452 */
2453 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2454 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2455
2456 if (func >= E1H_FUNC_MAX)
2457 break;
2458
2459 bp->mf_config[vn] =
2460 MF_CFG_RD(bp, func_mf_config[func].config);
2461 }
2462 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2463 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2464 bp->flags |= MF_FUNC_DIS;
2465 } else {
2466 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2467 bp->flags &= ~MF_FUNC_DIS;
2468 }
2469 }
2470
2471 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2472 {
2473 struct cmng_init_input input;
2474 memset(&input, 0, sizeof(struct cmng_init_input));
2475
2476 input.port_rate = bp->link_vars.line_speed;
2477
2478 if (cmng_type == CMNG_FNS_MINMAX) {
2479 int vn;
2480
2481 /* read mf conf from shmem */
2482 if (read_cfg)
2483 bnx2x_read_mf_cfg(bp);
2484
2485 /* vn_weight_sum and enable fairness if not 0 */
2486 bnx2x_calc_vn_min(bp, &input);
2487
2488 /* calculate and set min-max rate for each vn */
2489 if (bp->port.pmf)
2490 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2491 bnx2x_calc_vn_max(bp, vn, &input);
2492
2493 /* always enable rate shaping and fairness */
2494 input.flags.cmng_enables |=
2495 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2496
2497 bnx2x_init_cmng(&input, &bp->cmng);
2498 return;
2499 }
2500
2501 /* rate shaping and fairness are disabled */
2502 DP(NETIF_MSG_IFUP,
2503 "rate shaping and fairness are disabled\n");
2504 }
2505
2506 static void storm_memset_cmng(struct bnx2x *bp,
2507 struct cmng_init *cmng,
2508 u8 port)
2509 {
2510 int vn;
2511 size_t size = sizeof(struct cmng_struct_per_port);
2512
2513 u32 addr = BAR_XSTRORM_INTMEM +
2514 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2515
2516 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2517
2518 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2519 int func = func_by_vn(bp, vn);
2520
2521 addr = BAR_XSTRORM_INTMEM +
2522 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2523 size = sizeof(struct rate_shaping_vars_per_vn);
2524 __storm_memset_struct(bp, addr, size,
2525 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2526
2527 addr = BAR_XSTRORM_INTMEM +
2528 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2529 size = sizeof(struct fairness_vars_per_vn);
2530 __storm_memset_struct(bp, addr, size,
2531 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2532 }
2533 }
2534
2535 /* This function is called upon link interrupt */
2536 static void bnx2x_link_attn(struct bnx2x *bp)
2537 {
2538 /* Make sure that we are synced with the current statistics */
2539 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2540
2541 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2542
2543 if (bp->link_vars.link_up) {
2544
2545 /* dropless flow control */
2546 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2547 int port = BP_PORT(bp);
2548 u32 pause_enabled = 0;
2549
2550 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2551 pause_enabled = 1;
2552
2553 REG_WR(bp, BAR_USTRORM_INTMEM +
2554 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2555 pause_enabled);
2556 }
2557
2558 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2559 struct host_port_stats *pstats;
2560
2561 pstats = bnx2x_sp(bp, port_stats);
2562 /* reset old mac stats */
2563 memset(&(pstats->mac_stx[0]), 0,
2564 sizeof(struct mac_stx));
2565 }
2566 if (bp->state == BNX2X_STATE_OPEN)
2567 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2568 }
2569
2570 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2571 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2572
2573 if (cmng_fns != CMNG_FNS_NONE) {
2574 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2575 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2576 } else
2577 /* rate shaping and fairness are disabled */
2578 DP(NETIF_MSG_IFUP,
2579 "single function mode without fairness\n");
2580 }
2581
2582 __bnx2x_link_report(bp);
2583
2584 if (IS_MF(bp))
2585 bnx2x_link_sync_notify(bp);
2586 }
2587
2588 void bnx2x__link_status_update(struct bnx2x *bp)
2589 {
2590 if (bp->state != BNX2X_STATE_OPEN)
2591 return;
2592
2593 /* read updated dcb configuration */
2594 if (IS_PF(bp)) {
2595 bnx2x_dcbx_pmf_update(bp);
2596 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2597 if (bp->link_vars.link_up)
2598 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2599 else
2600 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2601 /* indicate link status */
2602 bnx2x_link_report(bp);
2603
2604 } else { /* VF */
2605 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2606 SUPPORTED_10baseT_Full |
2607 SUPPORTED_100baseT_Half |
2608 SUPPORTED_100baseT_Full |
2609 SUPPORTED_1000baseT_Full |
2610 SUPPORTED_2500baseX_Full |
2611 SUPPORTED_10000baseT_Full |
2612 SUPPORTED_TP |
2613 SUPPORTED_FIBRE |
2614 SUPPORTED_Autoneg |
2615 SUPPORTED_Pause |
2616 SUPPORTED_Asym_Pause);
2617 bp->port.advertising[0] = bp->port.supported[0];
2618
2619 bp->link_params.bp = bp;
2620 bp->link_params.port = BP_PORT(bp);
2621 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2622 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2623 bp->link_params.req_line_speed[0] = SPEED_10000;
2624 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2625 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2626 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2627 bp->link_vars.line_speed = SPEED_10000;
2628 bp->link_vars.link_status =
2629 (LINK_STATUS_LINK_UP |
2630 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2631 bp->link_vars.link_up = 1;
2632 bp->link_vars.duplex = DUPLEX_FULL;
2633 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2634 __bnx2x_link_report(bp);
2635 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2636 }
2637 }
2638
2639 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2640 u16 vlan_val, u8 allowed_prio)
2641 {
2642 struct bnx2x_func_state_params func_params = {NULL};
2643 struct bnx2x_func_afex_update_params *f_update_params =
2644 &func_params.params.afex_update;
2645
2646 func_params.f_obj = &bp->func_obj;
2647 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2648
2649 /* no need to wait for RAMROD completion, so don't
2650 * set RAMROD_COMP_WAIT flag
2651 */
2652
2653 f_update_params->vif_id = vifid;
2654 f_update_params->afex_default_vlan = vlan_val;
2655 f_update_params->allowed_priorities = allowed_prio;
2656
2657 /* if ramrod can not be sent, response to MCP immediately */
2658 if (bnx2x_func_state_change(bp, &func_params) < 0)
2659 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2660
2661 return 0;
2662 }
2663
2664 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2665 u16 vif_index, u8 func_bit_map)
2666 {
2667 struct bnx2x_func_state_params func_params = {NULL};
2668 struct bnx2x_func_afex_viflists_params *update_params =
2669 &func_params.params.afex_viflists;
2670 int rc;
2671 u32 drv_msg_code;
2672
2673 /* validate only LIST_SET and LIST_GET are received from switch */
2674 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2675 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2676 cmd_type);
2677
2678 func_params.f_obj = &bp->func_obj;
2679 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2680
2681 /* set parameters according to cmd_type */
2682 update_params->afex_vif_list_command = cmd_type;
2683 update_params->vif_list_index = vif_index;
2684 update_params->func_bit_map =
2685 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2686 update_params->func_to_clear = 0;
2687 drv_msg_code =
2688 (cmd_type == VIF_LIST_RULE_GET) ?
2689 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2690 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2691
2692 /* if ramrod can not be sent, respond to MCP immediately for
2693 * SET and GET requests (other are not triggered from MCP)
2694 */
2695 rc = bnx2x_func_state_change(bp, &func_params);
2696 if (rc < 0)
2697 bnx2x_fw_command(bp, drv_msg_code, 0);
2698
2699 return 0;
2700 }
2701
2702 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2703 {
2704 struct afex_stats afex_stats;
2705 u32 func = BP_ABS_FUNC(bp);
2706 u32 mf_config;
2707 u16 vlan_val;
2708 u32 vlan_prio;
2709 u16 vif_id;
2710 u8 allowed_prio;
2711 u8 vlan_mode;
2712 u32 addr_to_write, vifid, addrs, stats_type, i;
2713
2714 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2715 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2716 DP(BNX2X_MSG_MCP,
2717 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2718 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2719 }
2720
2721 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2722 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2723 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2724 DP(BNX2X_MSG_MCP,
2725 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2726 vifid, addrs);
2727 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2728 addrs);
2729 }
2730
2731 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2732 addr_to_write = SHMEM2_RD(bp,
2733 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2734 stats_type = SHMEM2_RD(bp,
2735 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2736
2737 DP(BNX2X_MSG_MCP,
2738 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2739 addr_to_write);
2740
2741 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2742
2743 /* write response to scratchpad, for MCP */
2744 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2745 REG_WR(bp, addr_to_write + i*sizeof(u32),
2746 *(((u32 *)(&afex_stats))+i));
2747
2748 /* send ack message to MCP */
2749 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2750 }
2751
2752 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2753 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2754 bp->mf_config[BP_VN(bp)] = mf_config;
2755 DP(BNX2X_MSG_MCP,
2756 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2757 mf_config);
2758
2759 /* if VIF_SET is "enabled" */
2760 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2761 /* set rate limit directly to internal RAM */
2762 struct cmng_init_input cmng_input;
2763 struct rate_shaping_vars_per_vn m_rs_vn;
2764 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2765 u32 addr = BAR_XSTRORM_INTMEM +
2766 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2767
2768 bp->mf_config[BP_VN(bp)] = mf_config;
2769
2770 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2771 m_rs_vn.vn_counter.rate =
2772 cmng_input.vnic_max_rate[BP_VN(bp)];
2773 m_rs_vn.vn_counter.quota =
2774 (m_rs_vn.vn_counter.rate *
2775 RS_PERIODIC_TIMEOUT_USEC) / 8;
2776
2777 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2778
2779 /* read relevant values from mf_cfg struct in shmem */
2780 vif_id =
2781 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2782 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2783 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2784 vlan_val =
2785 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2786 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2787 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2788 vlan_prio = (mf_config &
2789 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2790 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2791 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2792 vlan_mode =
2793 (MF_CFG_RD(bp,
2794 func_mf_config[func].afex_config) &
2795 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2796 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2797 allowed_prio =
2798 (MF_CFG_RD(bp,
2799 func_mf_config[func].afex_config) &
2800 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2801 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2802
2803 /* send ramrod to FW, return in case of failure */
2804 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2805 allowed_prio))
2806 return;
2807
2808 bp->afex_def_vlan_tag = vlan_val;
2809 bp->afex_vlan_mode = vlan_mode;
2810 } else {
2811 /* notify link down because BP->flags is disabled */
2812 bnx2x_link_report(bp);
2813
2814 /* send INVALID VIF ramrod to FW */
2815 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2816
2817 /* Reset the default afex VLAN */
2818 bp->afex_def_vlan_tag = -1;
2819 }
2820 }
2821 }
2822
2823 static void bnx2x_pmf_update(struct bnx2x *bp)
2824 {
2825 int port = BP_PORT(bp);
2826 u32 val;
2827
2828 bp->port.pmf = 1;
2829 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2830
2831 /*
2832 * We need the mb() to ensure the ordering between the writing to
2833 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2834 */
2835 smp_mb();
2836
2837 /* queue a periodic task */
2838 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2839
2840 bnx2x_dcbx_pmf_update(bp);
2841
2842 /* enable nig attention */
2843 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2844 if (bp->common.int_block == INT_BLOCK_HC) {
2845 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2846 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2847 } else if (!CHIP_IS_E1x(bp)) {
2848 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2849 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2850 }
2851
2852 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2853 }
2854
2855 /* end of Link */
2856
2857 /* slow path */
2858
2859 /*
2860 * General service functions
2861 */
2862
2863 /* send the MCP a request, block until there is a reply */
2864 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2865 {
2866 int mb_idx = BP_FW_MB_IDX(bp);
2867 u32 seq;
2868 u32 rc = 0;
2869 u32 cnt = 1;
2870 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2871
2872 mutex_lock(&bp->fw_mb_mutex);
2873 seq = ++bp->fw_seq;
2874 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2875 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2876
2877 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2878 (command | seq), param);
2879
2880 do {
2881 /* let the FW do it's magic ... */
2882 msleep(delay);
2883
2884 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2885
2886 /* Give the FW up to 5 second (500*10ms) */
2887 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2888
2889 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2890 cnt*delay, rc, seq);
2891
2892 /* is this a reply to our command? */
2893 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2894 rc &= FW_MSG_CODE_MASK;
2895 else {
2896 /* FW BUG! */
2897 BNX2X_ERR("FW failed to respond!\n");
2898 bnx2x_fw_dump(bp);
2899 rc = 0;
2900 }
2901 mutex_unlock(&bp->fw_mb_mutex);
2902
2903 return rc;
2904 }
2905
2906
2907 static void storm_memset_func_cfg(struct bnx2x *bp,
2908 struct tstorm_eth_function_common_config *tcfg,
2909 u16 abs_fid)
2910 {
2911 size_t size = sizeof(struct tstorm_eth_function_common_config);
2912
2913 u32 addr = BAR_TSTRORM_INTMEM +
2914 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2915
2916 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2917 }
2918
2919 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2920 {
2921 if (CHIP_IS_E1x(bp)) {
2922 struct tstorm_eth_function_common_config tcfg = {0};
2923
2924 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2925 }
2926
2927 /* Enable the function in the FW */
2928 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2929 storm_memset_func_en(bp, p->func_id, 1);
2930
2931 /* spq */
2932 if (p->func_flgs & FUNC_FLG_SPQ) {
2933 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2934 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2935 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2936 }
2937 }
2938
2939 /**
2940 * bnx2x_get_tx_only_flags - Return common flags
2941 *
2942 * @bp device handle
2943 * @fp queue handle
2944 * @zero_stats TRUE if statistics zeroing is needed
2945 *
2946 * Return the flags that are common for the Tx-only and not normal connections.
2947 */
2948 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2949 struct bnx2x_fastpath *fp,
2950 bool zero_stats)
2951 {
2952 unsigned long flags = 0;
2953
2954 /* PF driver will always initialize the Queue to an ACTIVE state */
2955 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2956
2957 /* tx only connections collect statistics (on the same index as the
2958 * parent connection). The statistics are zeroed when the parent
2959 * connection is initialized.
2960 */
2961
2962 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2963 if (zero_stats)
2964 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2965
2966
2967 #ifdef BNX2X_STOP_ON_ERROR
2968 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2969 #endif
2970
2971 return flags;
2972 }
2973
2974 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2975 struct bnx2x_fastpath *fp,
2976 bool leading)
2977 {
2978 unsigned long flags = 0;
2979
2980 /* calculate other queue flags */
2981 if (IS_MF_SD(bp))
2982 __set_bit(BNX2X_Q_FLG_OV, &flags);
2983
2984 if (IS_FCOE_FP(fp)) {
2985 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2986 /* For FCoE - force usage of default priority (for afex) */
2987 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2988 }
2989
2990 if (!fp->disable_tpa) {
2991 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2992 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2993 if (fp->mode == TPA_MODE_GRO)
2994 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2995 }
2996
2997 if (leading) {
2998 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2999 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3000 }
3001
3002 /* Always set HW VLAN stripping */
3003 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3004
3005 /* configure silent vlan removal */
3006 if (IS_MF_AFEX(bp))
3007 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3008
3009
3010 return flags | bnx2x_get_common_flags(bp, fp, true);
3011 }
3012
3013 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3014 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3015 u8 cos)
3016 {
3017 gen_init->stat_id = bnx2x_stats_id(fp);
3018 gen_init->spcl_id = fp->cl_id;
3019
3020 /* Always use mini-jumbo MTU for FCoE L2 ring */
3021 if (IS_FCOE_FP(fp))
3022 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3023 else
3024 gen_init->mtu = bp->dev->mtu;
3025
3026 gen_init->cos = cos;
3027 }
3028
3029 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3030 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3031 struct bnx2x_rxq_setup_params *rxq_init)
3032 {
3033 u8 max_sge = 0;
3034 u16 sge_sz = 0;
3035 u16 tpa_agg_size = 0;
3036
3037 if (!fp->disable_tpa) {
3038 pause->sge_th_lo = SGE_TH_LO(bp);
3039 pause->sge_th_hi = SGE_TH_HI(bp);
3040
3041 /* validate SGE ring has enough to cross high threshold */
3042 WARN_ON(bp->dropless_fc &&
3043 pause->sge_th_hi + FW_PREFETCH_CNT >
3044 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3045
3046 tpa_agg_size = TPA_AGG_SIZE;
3047 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3048 SGE_PAGE_SHIFT;
3049 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3050 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3051 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3052 }
3053
3054 /* pause - not for e1 */
3055 if (!CHIP_IS_E1(bp)) {
3056 pause->bd_th_lo = BD_TH_LO(bp);
3057 pause->bd_th_hi = BD_TH_HI(bp);
3058
3059 pause->rcq_th_lo = RCQ_TH_LO(bp);
3060 pause->rcq_th_hi = RCQ_TH_HI(bp);
3061 /*
3062 * validate that rings have enough entries to cross
3063 * high thresholds
3064 */
3065 WARN_ON(bp->dropless_fc &&
3066 pause->bd_th_hi + FW_PREFETCH_CNT >
3067 bp->rx_ring_size);
3068 WARN_ON(bp->dropless_fc &&
3069 pause->rcq_th_hi + FW_PREFETCH_CNT >
3070 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3071
3072 pause->pri_map = 1;
3073 }
3074
3075 /* rxq setup */
3076 rxq_init->dscr_map = fp->rx_desc_mapping;
3077 rxq_init->sge_map = fp->rx_sge_mapping;
3078 rxq_init->rcq_map = fp->rx_comp_mapping;
3079 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3080
3081 /* This should be a maximum number of data bytes that may be
3082 * placed on the BD (not including paddings).
3083 */
3084 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3085 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3086
3087 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3088 rxq_init->tpa_agg_sz = tpa_agg_size;
3089 rxq_init->sge_buf_sz = sge_sz;
3090 rxq_init->max_sges_pkt = max_sge;
3091 rxq_init->rss_engine_id = BP_FUNC(bp);
3092 rxq_init->mcast_engine_id = BP_FUNC(bp);
3093
3094 /* Maximum number or simultaneous TPA aggregation for this Queue.
3095 *
3096 * For PF Clients it should be the maximum available number.
3097 * VF driver(s) may want to define it to a smaller value.
3098 */
3099 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3100
3101 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3102 rxq_init->fw_sb_id = fp->fw_sb_id;
3103
3104 if (IS_FCOE_FP(fp))
3105 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3106 else
3107 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3108 /* configure silent vlan removal
3109 * if multi function mode is afex, then mask default vlan
3110 */
3111 if (IS_MF_AFEX(bp)) {
3112 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3113 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3114 }
3115 }
3116
3117 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3118 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3119 u8 cos)
3120 {
3121 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3122 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3123 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3124 txq_init->fw_sb_id = fp->fw_sb_id;
3125
3126 /*
3127 * set the tss leading client id for TX classfication ==
3128 * leading RSS client id
3129 */
3130 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3131
3132 if (IS_FCOE_FP(fp)) {
3133 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3134 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3135 }
3136 }
3137
3138 static void bnx2x_pf_init(struct bnx2x *bp)
3139 {
3140 struct bnx2x_func_init_params func_init = {0};
3141 struct event_ring_data eq_data = { {0} };
3142 u16 flags;
3143
3144 if (!CHIP_IS_E1x(bp)) {
3145 /* reset IGU PF statistics: MSIX + ATTN */
3146 /* PF */
3147 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3148 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3149 (CHIP_MODE_IS_4_PORT(bp) ?
3150 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3151 /* ATTN */
3152 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3153 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3154 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3155 (CHIP_MODE_IS_4_PORT(bp) ?
3156 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3157 }
3158
3159 /* function setup flags */
3160 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3161
3162 /* This flag is relevant for E1x only.
3163 * E2 doesn't have a TPA configuration in a function level.
3164 */
3165 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3166
3167 func_init.func_flgs = flags;
3168 func_init.pf_id = BP_FUNC(bp);
3169 func_init.func_id = BP_FUNC(bp);
3170 func_init.spq_map = bp->spq_mapping;
3171 func_init.spq_prod = bp->spq_prod_idx;
3172
3173 bnx2x_func_init(bp, &func_init);
3174
3175 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3176
3177 /*
3178 * Congestion management values depend on the link rate
3179 * There is no active link so initial link rate is set to 10 Gbps.
3180 * When the link comes up The congestion management values are
3181 * re-calculated according to the actual link rate.
3182 */
3183 bp->link_vars.line_speed = SPEED_10000;
3184 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3185
3186 /* Only the PMF sets the HW */
3187 if (bp->port.pmf)
3188 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3189
3190 /* init Event Queue - PCI bus guarantees correct endianity*/
3191 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3192 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3193 eq_data.producer = bp->eq_prod;
3194 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3195 eq_data.sb_id = DEF_SB_ID;
3196 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3197 }
3198
3199
3200 static void bnx2x_e1h_disable(struct bnx2x *bp)
3201 {
3202 int port = BP_PORT(bp);
3203
3204 bnx2x_tx_disable(bp);
3205
3206 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3207 }
3208
3209 static void bnx2x_e1h_enable(struct bnx2x *bp)
3210 {
3211 int port = BP_PORT(bp);
3212
3213 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3214
3215 /* Tx queue should be only reenabled */
3216 netif_tx_wake_all_queues(bp->dev);
3217
3218 /*
3219 * Should not call netif_carrier_on since it will be called if the link
3220 * is up when checking for link state
3221 */
3222 }
3223
3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3225
3226 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3227 {
3228 struct eth_stats_info *ether_stat =
3229 &bp->slowpath->drv_info_to_mcp.ether_stat;
3230
3231 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3232 ETH_STAT_INFO_VERSION_LEN);
3233
3234 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3235 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3236 ether_stat->mac_local);
3237
3238 ether_stat->mtu_size = bp->dev->mtu;
3239
3240 if (bp->dev->features & NETIF_F_RXCSUM)
3241 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3242 if (bp->dev->features & NETIF_F_TSO)
3243 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3244 ether_stat->feature_flags |= bp->common.boot_mode;
3245
3246 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3247
3248 ether_stat->txq_size = bp->tx_ring_size;
3249 ether_stat->rxq_size = bp->rx_ring_size;
3250 }
3251
3252 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3253 {
3254 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3255 struct fcoe_stats_info *fcoe_stat =
3256 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3257
3258 if (!CNIC_LOADED(bp))
3259 return;
3260
3261 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3262 bp->fip_mac, ETH_ALEN);
3263
3264 fcoe_stat->qos_priority =
3265 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3266
3267 /* insert FCoE stats from ramrod response */
3268 if (!NO_FCOE(bp)) {
3269 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3270 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3271 tstorm_queue_statistics;
3272
3273 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3274 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3275 xstorm_queue_statistics;
3276
3277 struct fcoe_statistics_params *fw_fcoe_stat =
3278 &bp->fw_stats_data->fcoe;
3279
3280 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3281 fcoe_stat->rx_bytes_lo,
3282 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3283
3284 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3285 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3286 fcoe_stat->rx_bytes_lo,
3287 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3288
3289 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3290 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3291 fcoe_stat->rx_bytes_lo,
3292 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3293
3294 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3295 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3296 fcoe_stat->rx_bytes_lo,
3297 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3298
3299 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3300 fcoe_stat->rx_frames_lo,
3301 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3302
3303 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3304 fcoe_stat->rx_frames_lo,
3305 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3306
3307 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3308 fcoe_stat->rx_frames_lo,
3309 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3310
3311 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3312 fcoe_stat->rx_frames_lo,
3313 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3314
3315 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3316 fcoe_stat->tx_bytes_lo,
3317 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3318
3319 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3320 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3321 fcoe_stat->tx_bytes_lo,
3322 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3323
3324 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3325 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3326 fcoe_stat->tx_bytes_lo,
3327 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3328
3329 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3330 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3331 fcoe_stat->tx_bytes_lo,
3332 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3333
3334 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3335 fcoe_stat->tx_frames_lo,
3336 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3337
3338 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3339 fcoe_stat->tx_frames_lo,
3340 fcoe_q_xstorm_stats->ucast_pkts_sent);
3341
3342 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3343 fcoe_stat->tx_frames_lo,
3344 fcoe_q_xstorm_stats->bcast_pkts_sent);
3345
3346 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3347 fcoe_stat->tx_frames_lo,
3348 fcoe_q_xstorm_stats->mcast_pkts_sent);
3349 }
3350
3351 /* ask L5 driver to add data to the struct */
3352 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3353 }
3354
3355 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3356 {
3357 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3358 struct iscsi_stats_info *iscsi_stat =
3359 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3360
3361 if (!CNIC_LOADED(bp))
3362 return;
3363
3364 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3365 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3366
3367 iscsi_stat->qos_priority =
3368 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3369
3370 /* ask L5 driver to add data to the struct */
3371 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3372 }
3373
3374 /* called due to MCP event (on pmf):
3375 * reread new bandwidth configuration
3376 * configure FW
3377 * notify others function about the change
3378 */
3379 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3380 {
3381 if (bp->link_vars.link_up) {
3382 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3383 bnx2x_link_sync_notify(bp);
3384 }
3385 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3386 }
3387
3388 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3389 {
3390 bnx2x_config_mf_bw(bp);
3391 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3392 }
3393
3394 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3395 {
3396 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3397 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3398 }
3399
3400 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3401 {
3402 enum drv_info_opcode op_code;
3403 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3404
3405 /* if drv_info version supported by MFW doesn't match - send NACK */
3406 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3407 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3408 return;
3409 }
3410
3411 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3412 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3413
3414 memset(&bp->slowpath->drv_info_to_mcp, 0,
3415 sizeof(union drv_info_to_mcp));
3416
3417 switch (op_code) {
3418 case ETH_STATS_OPCODE:
3419 bnx2x_drv_info_ether_stat(bp);
3420 break;
3421 case FCOE_STATS_OPCODE:
3422 bnx2x_drv_info_fcoe_stat(bp);
3423 break;
3424 case ISCSI_STATS_OPCODE:
3425 bnx2x_drv_info_iscsi_stat(bp);
3426 break;
3427 default:
3428 /* if op code isn't supported - send NACK */
3429 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3430 return;
3431 }
3432
3433 /* if we got drv_info attn from MFW then these fields are defined in
3434 * shmem2 for sure
3435 */
3436 SHMEM2_WR(bp, drv_info_host_addr_lo,
3437 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3438 SHMEM2_WR(bp, drv_info_host_addr_hi,
3439 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3440
3441 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3442 }
3443
3444 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3445 {
3446 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3447
3448 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3449
3450 /*
3451 * This is the only place besides the function initialization
3452 * where the bp->flags can change so it is done without any
3453 * locks
3454 */
3455 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3456 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3457 bp->flags |= MF_FUNC_DIS;
3458
3459 bnx2x_e1h_disable(bp);
3460 } else {
3461 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3462 bp->flags &= ~MF_FUNC_DIS;
3463
3464 bnx2x_e1h_enable(bp);
3465 }
3466 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3467 }
3468 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3469 bnx2x_config_mf_bw(bp);
3470 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3471 }
3472
3473 /* Report results to MCP */
3474 if (dcc_event)
3475 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3476 else
3477 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3478 }
3479
3480 /* must be called under the spq lock */
3481 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3482 {
3483 struct eth_spe *next_spe = bp->spq_prod_bd;
3484
3485 if (bp->spq_prod_bd == bp->spq_last_bd) {
3486 bp->spq_prod_bd = bp->spq;
3487 bp->spq_prod_idx = 0;
3488 DP(BNX2X_MSG_SP, "end of spq\n");
3489 } else {
3490 bp->spq_prod_bd++;
3491 bp->spq_prod_idx++;
3492 }
3493 return next_spe;
3494 }
3495
3496 /* must be called under the spq lock */
3497 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3498 {
3499 int func = BP_FUNC(bp);
3500
3501 /*
3502 * Make sure that BD data is updated before writing the producer:
3503 * BD data is written to the memory, the producer is read from the
3504 * memory, thus we need a full memory barrier to ensure the ordering.
3505 */
3506 mb();
3507
3508 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3509 bp->spq_prod_idx);
3510 mmiowb();
3511 }
3512
3513 /**
3514 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3515 *
3516 * @cmd: command to check
3517 * @cmd_type: command type
3518 */
3519 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3520 {
3521 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3522 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3523 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3524 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3525 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3526 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3527 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3528 return true;
3529 else
3530 return false;
3531
3532 }
3533
3534
3535 /**
3536 * bnx2x_sp_post - place a single command on an SP ring
3537 *
3538 * @bp: driver handle
3539 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3540 * @cid: SW CID the command is related to
3541 * @data_hi: command private data address (high 32 bits)
3542 * @data_lo: command private data address (low 32 bits)
3543 * @cmd_type: command type (e.g. NONE, ETH)
3544 *
3545 * SP data is handled as if it's always an address pair, thus data fields are
3546 * not swapped to little endian in upper functions. Instead this function swaps
3547 * data as if it's two u32 fields.
3548 */
3549 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3550 u32 data_hi, u32 data_lo, int cmd_type)
3551 {
3552 struct eth_spe *spe;
3553 u16 type;
3554 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3555
3556 #ifdef BNX2X_STOP_ON_ERROR
3557 if (unlikely(bp->panic)) {
3558 BNX2X_ERR("Can't post SP when there is panic\n");
3559 return -EIO;
3560 }
3561 #endif
3562
3563 spin_lock_bh(&bp->spq_lock);
3564
3565 if (common) {
3566 if (!atomic_read(&bp->eq_spq_left)) {
3567 BNX2X_ERR("BUG! EQ ring full!\n");
3568 spin_unlock_bh(&bp->spq_lock);
3569 bnx2x_panic();
3570 return -EBUSY;
3571 }
3572 } else if (!atomic_read(&bp->cq_spq_left)) {
3573 BNX2X_ERR("BUG! SPQ ring full!\n");
3574 spin_unlock_bh(&bp->spq_lock);
3575 bnx2x_panic();
3576 return -EBUSY;
3577 }
3578
3579 spe = bnx2x_sp_get_next(bp);
3580
3581 /* CID needs port number to be encoded int it */
3582 spe->hdr.conn_and_cmd_data =
3583 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3584 HW_CID(bp, cid));
3585
3586 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3587
3588 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3589 SPE_HDR_FUNCTION_ID);
3590
3591 spe->hdr.type = cpu_to_le16(type);
3592
3593 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3594 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3595
3596 /*
3597 * It's ok if the actual decrement is issued towards the memory
3598 * somewhere between the spin_lock and spin_unlock. Thus no
3599 * more explict memory barrier is needed.
3600 */
3601 if (common)
3602 atomic_dec(&bp->eq_spq_left);
3603 else
3604 atomic_dec(&bp->cq_spq_left);
3605
3606
3607 DP(BNX2X_MSG_SP,
3608 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3609 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3610 (u32)(U64_LO(bp->spq_mapping) +
3611 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3612 HW_CID(bp, cid), data_hi, data_lo, type,
3613 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3614
3615 bnx2x_sp_prod_update(bp);
3616 spin_unlock_bh(&bp->spq_lock);
3617 return 0;
3618 }
3619
3620 /* acquire split MCP access lock register */
3621 static int bnx2x_acquire_alr(struct bnx2x *bp)
3622 {
3623 u32 j, val;
3624 int rc = 0;
3625
3626 might_sleep();
3627 for (j = 0; j < 1000; j++) {
3628 val = (1UL << 31);
3629 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3630 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3631 if (val & (1L << 31))
3632 break;
3633
3634 msleep(5);
3635 }
3636 if (!(val & (1L << 31))) {
3637 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3638 rc = -EBUSY;
3639 }
3640
3641 return rc;
3642 }
3643
3644 /* release split MCP access lock register */
3645 static void bnx2x_release_alr(struct bnx2x *bp)
3646 {
3647 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3648 }
3649
3650 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3651 #define BNX2X_DEF_SB_IDX 0x0002
3652
3653 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3654 {
3655 struct host_sp_status_block *def_sb = bp->def_status_blk;
3656 u16 rc = 0;
3657
3658 barrier(); /* status block is written to by the chip */
3659 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3660 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3661 rc |= BNX2X_DEF_SB_ATT_IDX;
3662 }
3663
3664 if (bp->def_idx != def_sb->sp_sb.running_index) {
3665 bp->def_idx = def_sb->sp_sb.running_index;
3666 rc |= BNX2X_DEF_SB_IDX;
3667 }
3668
3669 /* Do not reorder: indecies reading should complete before handling */
3670 barrier();
3671 return rc;
3672 }
3673
3674 /*
3675 * slow path service functions
3676 */
3677
3678 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3679 {
3680 int port = BP_PORT(bp);
3681 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3682 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3683 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3684 NIG_REG_MASK_INTERRUPT_PORT0;
3685 u32 aeu_mask;
3686 u32 nig_mask = 0;
3687 u32 reg_addr;
3688
3689 if (bp->attn_state & asserted)
3690 BNX2X_ERR("IGU ERROR\n");
3691
3692 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3693 aeu_mask = REG_RD(bp, aeu_addr);
3694
3695 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3696 aeu_mask, asserted);
3697 aeu_mask &= ~(asserted & 0x3ff);
3698 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3699
3700 REG_WR(bp, aeu_addr, aeu_mask);
3701 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3702
3703 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3704 bp->attn_state |= asserted;
3705 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3706
3707 if (asserted & ATTN_HARD_WIRED_MASK) {
3708 if (asserted & ATTN_NIG_FOR_FUNC) {
3709
3710 bnx2x_acquire_phy_lock(bp);
3711
3712 /* save nig interrupt mask */
3713 nig_mask = REG_RD(bp, nig_int_mask_addr);
3714
3715 /* If nig_mask is not set, no need to call the update
3716 * function.
3717 */
3718 if (nig_mask) {
3719 REG_WR(bp, nig_int_mask_addr, 0);
3720
3721 bnx2x_link_attn(bp);
3722 }
3723
3724 /* handle unicore attn? */
3725 }
3726 if (asserted & ATTN_SW_TIMER_4_FUNC)
3727 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3728
3729 if (asserted & GPIO_2_FUNC)
3730 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3731
3732 if (asserted & GPIO_3_FUNC)
3733 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3734
3735 if (asserted & GPIO_4_FUNC)
3736 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3737
3738 if (port == 0) {
3739 if (asserted & ATTN_GENERAL_ATTN_1) {
3740 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3741 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3742 }
3743 if (asserted & ATTN_GENERAL_ATTN_2) {
3744 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3745 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3746 }
3747 if (asserted & ATTN_GENERAL_ATTN_3) {
3748 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3749 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3750 }
3751 } else {
3752 if (asserted & ATTN_GENERAL_ATTN_4) {
3753 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3754 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3755 }
3756 if (asserted & ATTN_GENERAL_ATTN_5) {
3757 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3758 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3759 }
3760 if (asserted & ATTN_GENERAL_ATTN_6) {
3761 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3762 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3763 }
3764 }
3765
3766 } /* if hardwired */
3767
3768 if (bp->common.int_block == INT_BLOCK_HC)
3769 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3770 COMMAND_REG_ATTN_BITS_SET);
3771 else
3772 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3773
3774 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3775 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3776 REG_WR(bp, reg_addr, asserted);
3777
3778 /* now set back the mask */
3779 if (asserted & ATTN_NIG_FOR_FUNC) {
3780 /* Verify that IGU ack through BAR was written before restoring
3781 * NIG mask. This loop should exit after 2-3 iterations max.
3782 */
3783 if (bp->common.int_block != INT_BLOCK_HC) {
3784 u32 cnt = 0, igu_acked;
3785 do {
3786 igu_acked = REG_RD(bp,
3787 IGU_REG_ATTENTION_ACK_BITS);
3788 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3789 (++cnt < MAX_IGU_ATTN_ACK_TO));
3790 if (!igu_acked)
3791 DP(NETIF_MSG_HW,
3792 "Failed to verify IGU ack on time\n");
3793 barrier();
3794 }
3795 REG_WR(bp, nig_int_mask_addr, nig_mask);
3796 bnx2x_release_phy_lock(bp);
3797 }
3798 }
3799
3800 static void bnx2x_fan_failure(struct bnx2x *bp)
3801 {
3802 int port = BP_PORT(bp);
3803 u32 ext_phy_config;
3804 /* mark the failure */
3805 ext_phy_config =
3806 SHMEM_RD(bp,
3807 dev_info.port_hw_config[port].external_phy_config);
3808
3809 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3810 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3811 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3812 ext_phy_config);
3813
3814 /* log the failure */
3815 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3816 "Please contact OEM Support for assistance\n");
3817
3818 /*
3819 * Schedule device reset (unload)
3820 * This is due to some boards consuming sufficient power when driver is
3821 * up to overheat if fan fails.
3822 */
3823 smp_mb__before_clear_bit();
3824 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3825 smp_mb__after_clear_bit();
3826 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3827
3828 }
3829
3830 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3831 {
3832 int port = BP_PORT(bp);
3833 int reg_offset;
3834 u32 val;
3835
3836 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3837 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3838
3839 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3840
3841 val = REG_RD(bp, reg_offset);
3842 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3843 REG_WR(bp, reg_offset, val);
3844
3845 BNX2X_ERR("SPIO5 hw attention\n");
3846
3847 /* Fan failure attention */
3848 bnx2x_hw_reset_phy(&bp->link_params);
3849 bnx2x_fan_failure(bp);
3850 }
3851
3852 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3853 bnx2x_acquire_phy_lock(bp);
3854 bnx2x_handle_module_detect_int(&bp->link_params);
3855 bnx2x_release_phy_lock(bp);
3856 }
3857
3858 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3859
3860 val = REG_RD(bp, reg_offset);
3861 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3862 REG_WR(bp, reg_offset, val);
3863
3864 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3865 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3866 bnx2x_panic();
3867 }
3868 }
3869
3870 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3871 {
3872 u32 val;
3873
3874 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3875
3876 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3877 BNX2X_ERR("DB hw attention 0x%x\n", val);
3878 /* DORQ discard attention */
3879 if (val & 0x2)
3880 BNX2X_ERR("FATAL error from DORQ\n");
3881 }
3882
3883 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3884
3885 int port = BP_PORT(bp);
3886 int reg_offset;
3887
3888 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3889 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3890
3891 val = REG_RD(bp, reg_offset);
3892 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3893 REG_WR(bp, reg_offset, val);
3894
3895 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3896 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3897 bnx2x_panic();
3898 }
3899 }
3900
3901 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3902 {
3903 u32 val;
3904
3905 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3906
3907 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3908 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3909 /* CFC error attention */
3910 if (val & 0x2)
3911 BNX2X_ERR("FATAL error from CFC\n");
3912 }
3913
3914 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3915 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3916 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3917 /* RQ_USDMDP_FIFO_OVERFLOW */
3918 if (val & 0x18000)
3919 BNX2X_ERR("FATAL error from PXP\n");
3920
3921 if (!CHIP_IS_E1x(bp)) {
3922 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3923 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3924 }
3925 }
3926
3927 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3928
3929 int port = BP_PORT(bp);
3930 int reg_offset;
3931
3932 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3933 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3934
3935 val = REG_RD(bp, reg_offset);
3936 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3937 REG_WR(bp, reg_offset, val);
3938
3939 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3940 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3941 bnx2x_panic();
3942 }
3943 }
3944
3945 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3946 {
3947 u32 val;
3948
3949 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3950
3951 if (attn & BNX2X_PMF_LINK_ASSERT) {
3952 int func = BP_FUNC(bp);
3953
3954 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3955 bnx2x_read_mf_cfg(bp);
3956 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3957 func_mf_config[BP_ABS_FUNC(bp)].config);
3958 val = SHMEM_RD(bp,
3959 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3960 if (val & DRV_STATUS_DCC_EVENT_MASK)
3961 bnx2x_dcc_event(bp,
3962 (val & DRV_STATUS_DCC_EVENT_MASK));
3963
3964 if (val & DRV_STATUS_SET_MF_BW)
3965 bnx2x_set_mf_bw(bp);
3966
3967 if (val & DRV_STATUS_DRV_INFO_REQ)
3968 bnx2x_handle_drv_info_req(bp);
3969
3970 if (val & DRV_STATUS_VF_DISABLED)
3971 bnx2x_vf_handle_flr_event(bp);
3972
3973 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3974 bnx2x_pmf_update(bp);
3975
3976 if (bp->port.pmf &&
3977 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3978 bp->dcbx_enabled > 0)
3979 /* start dcbx state machine */
3980 bnx2x_dcbx_set_params(bp,
3981 BNX2X_DCBX_STATE_NEG_RECEIVED);
3982 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3983 bnx2x_handle_afex_cmd(bp,
3984 val & DRV_STATUS_AFEX_EVENT_MASK);
3985 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3986 bnx2x_handle_eee_event(bp);
3987 if (bp->link_vars.periodic_flags &
3988 PERIODIC_FLAGS_LINK_EVENT) {
3989 /* sync with link */
3990 bnx2x_acquire_phy_lock(bp);
3991 bp->link_vars.periodic_flags &=
3992 ~PERIODIC_FLAGS_LINK_EVENT;
3993 bnx2x_release_phy_lock(bp);
3994 if (IS_MF(bp))
3995 bnx2x_link_sync_notify(bp);
3996 bnx2x_link_report(bp);
3997 }
3998 /* Always call it here: bnx2x_link_report() will
3999 * prevent the link indication duplication.
4000 */
4001 bnx2x__link_status_update(bp);
4002 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4003
4004 BNX2X_ERR("MC assert!\n");
4005 bnx2x_mc_assert(bp);
4006 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4007 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4008 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4009 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4010 bnx2x_panic();
4011
4012 } else if (attn & BNX2X_MCP_ASSERT) {
4013
4014 BNX2X_ERR("MCP assert!\n");
4015 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4016 bnx2x_fw_dump(bp);
4017
4018 } else
4019 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4020 }
4021
4022 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4023 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4024 if (attn & BNX2X_GRC_TIMEOUT) {
4025 val = CHIP_IS_E1(bp) ? 0 :
4026 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4027 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4028 }
4029 if (attn & BNX2X_GRC_RSV) {
4030 val = CHIP_IS_E1(bp) ? 0 :
4031 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4032 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4033 }
4034 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4035 }
4036 }
4037
4038 /*
4039 * Bits map:
4040 * 0-7 - Engine0 load counter.
4041 * 8-15 - Engine1 load counter.
4042 * 16 - Engine0 RESET_IN_PROGRESS bit.
4043 * 17 - Engine1 RESET_IN_PROGRESS bit.
4044 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4045 * on the engine
4046 * 19 - Engine1 ONE_IS_LOADED.
4047 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4048 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4049 * just the one belonging to its engine).
4050 *
4051 */
4052 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4053
4054 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4055 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4056 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4057 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4058 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4059 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4060 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4061
4062 /*
4063 * Set the GLOBAL_RESET bit.
4064 *
4065 * Should be run under rtnl lock
4066 */
4067 void bnx2x_set_reset_global(struct bnx2x *bp)
4068 {
4069 u32 val;
4070 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4071 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4072 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4073 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4074 }
4075
4076 /*
4077 * Clear the GLOBAL_RESET bit.
4078 *
4079 * Should be run under rtnl lock
4080 */
4081 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4082 {
4083 u32 val;
4084 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4085 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4086 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4087 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4088 }
4089
4090 /*
4091 * Checks the GLOBAL_RESET bit.
4092 *
4093 * should be run under rtnl lock
4094 */
4095 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4096 {
4097 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4098
4099 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4100 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4101 }
4102
4103 /*
4104 * Clear RESET_IN_PROGRESS bit for the current engine.
4105 *
4106 * Should be run under rtnl lock
4107 */
4108 static void bnx2x_set_reset_done(struct bnx2x *bp)
4109 {
4110 u32 val;
4111 u32 bit = BP_PATH(bp) ?
4112 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4113 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4114 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4115
4116 /* Clear the bit */
4117 val &= ~bit;
4118 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4119
4120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4121 }
4122
4123 /*
4124 * Set RESET_IN_PROGRESS for the current engine.
4125 *
4126 * should be run under rtnl lock
4127 */
4128 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4129 {
4130 u32 val;
4131 u32 bit = BP_PATH(bp) ?
4132 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4133 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4134 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4135
4136 /* Set the bit */
4137 val |= bit;
4138 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4139 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4140 }
4141
4142 /*
4143 * Checks the RESET_IN_PROGRESS bit for the given engine.
4144 * should be run under rtnl lock
4145 */
4146 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4147 {
4148 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4149 u32 bit = engine ?
4150 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4151
4152 /* return false if bit is set */
4153 return (val & bit) ? false : true;
4154 }
4155
4156 /*
4157 * set pf load for the current pf.
4158 *
4159 * should be run under rtnl lock
4160 */
4161 void bnx2x_set_pf_load(struct bnx2x *bp)
4162 {
4163 u32 val1, val;
4164 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4165 BNX2X_PATH0_LOAD_CNT_MASK;
4166 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4167 BNX2X_PATH0_LOAD_CNT_SHIFT;
4168
4169 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4170 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4171
4172 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4173
4174 /* get the current counter value */
4175 val1 = (val & mask) >> shift;
4176
4177 /* set bit of that PF */
4178 val1 |= (1 << bp->pf_num);
4179
4180 /* clear the old value */
4181 val &= ~mask;
4182
4183 /* set the new one */
4184 val |= ((val1 << shift) & mask);
4185
4186 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4187 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4188 }
4189
4190 /**
4191 * bnx2x_clear_pf_load - clear pf load mark
4192 *
4193 * @bp: driver handle
4194 *
4195 * Should be run under rtnl lock.
4196 * Decrements the load counter for the current engine. Returns
4197 * whether other functions are still loaded
4198 */
4199 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4200 {
4201 u32 val1, val;
4202 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4203 BNX2X_PATH0_LOAD_CNT_MASK;
4204 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4205 BNX2X_PATH0_LOAD_CNT_SHIFT;
4206
4207 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4208 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4209 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4210
4211 /* get the current counter value */
4212 val1 = (val & mask) >> shift;
4213
4214 /* clear bit of that PF */
4215 val1 &= ~(1 << bp->pf_num);
4216
4217 /* clear the old value */
4218 val &= ~mask;
4219
4220 /* set the new one */
4221 val |= ((val1 << shift) & mask);
4222
4223 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4224 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4225 return val1 != 0;
4226 }
4227
4228 /*
4229 * Read the load status for the current engine.
4230 *
4231 * should be run under rtnl lock
4232 */
4233 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4234 {
4235 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4236 BNX2X_PATH0_LOAD_CNT_MASK);
4237 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4238 BNX2X_PATH0_LOAD_CNT_SHIFT);
4239 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4240
4241 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4242
4243 val = (val & mask) >> shift;
4244
4245 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4246 engine, val);
4247
4248 return val != 0;
4249 }
4250
4251 static void _print_next_block(int idx, const char *blk)
4252 {
4253 pr_cont("%s%s", idx ? ", " : "", blk);
4254 }
4255
4256 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4257 bool print)
4258 {
4259 int i = 0;
4260 u32 cur_bit = 0;
4261 for (i = 0; sig; i++) {
4262 cur_bit = ((u32)0x1 << i);
4263 if (sig & cur_bit) {
4264 switch (cur_bit) {
4265 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4266 if (print)
4267 _print_next_block(par_num++, "BRB");
4268 break;
4269 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4270 if (print)
4271 _print_next_block(par_num++, "PARSER");
4272 break;
4273 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4274 if (print)
4275 _print_next_block(par_num++, "TSDM");
4276 break;
4277 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4278 if (print)
4279 _print_next_block(par_num++,
4280 "SEARCHER");
4281 break;
4282 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4283 if (print)
4284 _print_next_block(par_num++, "TCM");
4285 break;
4286 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4287 if (print)
4288 _print_next_block(par_num++, "TSEMI");
4289 break;
4290 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4291 if (print)
4292 _print_next_block(par_num++, "XPB");
4293 break;
4294 }
4295
4296 /* Clear the bit */
4297 sig &= ~cur_bit;
4298 }
4299 }
4300
4301 return par_num;
4302 }
4303
4304 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4305 bool *global, bool print)
4306 {
4307 int i = 0;
4308 u32 cur_bit = 0;
4309 for (i = 0; sig; i++) {
4310 cur_bit = ((u32)0x1 << i);
4311 if (sig & cur_bit) {
4312 switch (cur_bit) {
4313 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4314 if (print)
4315 _print_next_block(par_num++, "PBF");
4316 break;
4317 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4318 if (print)
4319 _print_next_block(par_num++, "QM");
4320 break;
4321 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4322 if (print)
4323 _print_next_block(par_num++, "TM");
4324 break;
4325 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4326 if (print)
4327 _print_next_block(par_num++, "XSDM");
4328 break;
4329 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4330 if (print)
4331 _print_next_block(par_num++, "XCM");
4332 break;
4333 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4334 if (print)
4335 _print_next_block(par_num++, "XSEMI");
4336 break;
4337 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4338 if (print)
4339 _print_next_block(par_num++,
4340 "DOORBELLQ");
4341 break;
4342 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4343 if (print)
4344 _print_next_block(par_num++, "NIG");
4345 break;
4346 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4347 if (print)
4348 _print_next_block(par_num++,
4349 "VAUX PCI CORE");
4350 *global = true;
4351 break;
4352 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4353 if (print)
4354 _print_next_block(par_num++, "DEBUG");
4355 break;
4356 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4357 if (print)
4358 _print_next_block(par_num++, "USDM");
4359 break;
4360 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4361 if (print)
4362 _print_next_block(par_num++, "UCM");
4363 break;
4364 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4365 if (print)
4366 _print_next_block(par_num++, "USEMI");
4367 break;
4368 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4369 if (print)
4370 _print_next_block(par_num++, "UPB");
4371 break;
4372 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4373 if (print)
4374 _print_next_block(par_num++, "CSDM");
4375 break;
4376 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4377 if (print)
4378 _print_next_block(par_num++, "CCM");
4379 break;
4380 }
4381
4382 /* Clear the bit */
4383 sig &= ~cur_bit;
4384 }
4385 }
4386
4387 return par_num;
4388 }
4389
4390 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4391 bool print)
4392 {
4393 int i = 0;
4394 u32 cur_bit = 0;
4395 for (i = 0; sig; i++) {
4396 cur_bit = ((u32)0x1 << i);
4397 if (sig & cur_bit) {
4398 switch (cur_bit) {
4399 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4400 if (print)
4401 _print_next_block(par_num++, "CSEMI");
4402 break;
4403 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4404 if (print)
4405 _print_next_block(par_num++, "PXP");
4406 break;
4407 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4408 if (print)
4409 _print_next_block(par_num++,
4410 "PXPPCICLOCKCLIENT");
4411 break;
4412 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4413 if (print)
4414 _print_next_block(par_num++, "CFC");
4415 break;
4416 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4417 if (print)
4418 _print_next_block(par_num++, "CDU");
4419 break;
4420 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4421 if (print)
4422 _print_next_block(par_num++, "DMAE");
4423 break;
4424 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4425 if (print)
4426 _print_next_block(par_num++, "IGU");
4427 break;
4428 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4429 if (print)
4430 _print_next_block(par_num++, "MISC");
4431 break;
4432 }
4433
4434 /* Clear the bit */
4435 sig &= ~cur_bit;
4436 }
4437 }
4438
4439 return par_num;
4440 }
4441
4442 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4443 bool *global, bool print)
4444 {
4445 int i = 0;
4446 u32 cur_bit = 0;
4447 for (i = 0; sig; i++) {
4448 cur_bit = ((u32)0x1 << i);
4449 if (sig & cur_bit) {
4450 switch (cur_bit) {
4451 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4452 if (print)
4453 _print_next_block(par_num++, "MCP ROM");
4454 *global = true;
4455 break;
4456 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4457 if (print)
4458 _print_next_block(par_num++,
4459 "MCP UMP RX");
4460 *global = true;
4461 break;
4462 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4463 if (print)
4464 _print_next_block(par_num++,
4465 "MCP UMP TX");
4466 *global = true;
4467 break;
4468 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4469 if (print)
4470 _print_next_block(par_num++,
4471 "MCP SCPAD");
4472 *global = true;
4473 break;
4474 }
4475
4476 /* Clear the bit */
4477 sig &= ~cur_bit;
4478 }
4479 }
4480
4481 return par_num;
4482 }
4483
4484 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4485 bool print)
4486 {
4487 int i = 0;
4488 u32 cur_bit = 0;
4489 for (i = 0; sig; i++) {
4490 cur_bit = ((u32)0x1 << i);
4491 if (sig & cur_bit) {
4492 switch (cur_bit) {
4493 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4494 if (print)
4495 _print_next_block(par_num++, "PGLUE_B");
4496 break;
4497 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4498 if (print)
4499 _print_next_block(par_num++, "ATC");
4500 break;
4501 }
4502
4503 /* Clear the bit */
4504 sig &= ~cur_bit;
4505 }
4506 }
4507
4508 return par_num;
4509 }
4510
4511 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4512 u32 *sig)
4513 {
4514 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4515 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4516 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4517 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4518 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4519 int par_num = 0;
4520 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4521 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4522 sig[0] & HW_PRTY_ASSERT_SET_0,
4523 sig[1] & HW_PRTY_ASSERT_SET_1,
4524 sig[2] & HW_PRTY_ASSERT_SET_2,
4525 sig[3] & HW_PRTY_ASSERT_SET_3,
4526 sig[4] & HW_PRTY_ASSERT_SET_4);
4527 if (print)
4528 netdev_err(bp->dev,
4529 "Parity errors detected in blocks: ");
4530 par_num = bnx2x_check_blocks_with_parity0(
4531 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4532 par_num = bnx2x_check_blocks_with_parity1(
4533 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4534 par_num = bnx2x_check_blocks_with_parity2(
4535 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4536 par_num = bnx2x_check_blocks_with_parity3(
4537 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4538 par_num = bnx2x_check_blocks_with_parity4(
4539 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4540
4541 if (print)
4542 pr_cont("\n");
4543
4544 return true;
4545 } else
4546 return false;
4547 }
4548
4549 /**
4550 * bnx2x_chk_parity_attn - checks for parity attentions.
4551 *
4552 * @bp: driver handle
4553 * @global: true if there was a global attention
4554 * @print: show parity attention in syslog
4555 */
4556 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4557 {
4558 struct attn_route attn = { {0} };
4559 int port = BP_PORT(bp);
4560
4561 attn.sig[0] = REG_RD(bp,
4562 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4563 port*4);
4564 attn.sig[1] = REG_RD(bp,
4565 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4566 port*4);
4567 attn.sig[2] = REG_RD(bp,
4568 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4569 port*4);
4570 attn.sig[3] = REG_RD(bp,
4571 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4572 port*4);
4573
4574 if (!CHIP_IS_E1x(bp))
4575 attn.sig[4] = REG_RD(bp,
4576 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4577 port*4);
4578
4579 return bnx2x_parity_attn(bp, global, print, attn.sig);
4580 }
4581
4582
4583 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4584 {
4585 u32 val;
4586 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4587
4588 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4589 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4590 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4591 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4592 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4593 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4594 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4595 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4596 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4597 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4598 if (val &
4599 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4600 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4601 if (val &
4602 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4603 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4604 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4605 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4606 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4607 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4608 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4609 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4610 }
4611 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4612 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4613 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4614 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4615 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4616 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4617 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4618 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4619 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4620 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4621 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4622 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4623 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4624 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4625 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4626 }
4627
4628 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4629 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4630 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4631 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4632 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4633 }
4634
4635 }
4636
4637 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4638 {
4639 struct attn_route attn, *group_mask;
4640 int port = BP_PORT(bp);
4641 int index;
4642 u32 reg_addr;
4643 u32 val;
4644 u32 aeu_mask;
4645 bool global = false;
4646
4647 /* need to take HW lock because MCP or other port might also
4648 try to handle this event */
4649 bnx2x_acquire_alr(bp);
4650
4651 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4652 #ifndef BNX2X_STOP_ON_ERROR
4653 bp->recovery_state = BNX2X_RECOVERY_INIT;
4654 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4655 /* Disable HW interrupts */
4656 bnx2x_int_disable(bp);
4657 /* In case of parity errors don't handle attentions so that
4658 * other function would "see" parity errors.
4659 */
4660 #else
4661 bnx2x_panic();
4662 #endif
4663 bnx2x_release_alr(bp);
4664 return;
4665 }
4666
4667 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4668 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4669 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4670 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4671 if (!CHIP_IS_E1x(bp))
4672 attn.sig[4] =
4673 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4674 else
4675 attn.sig[4] = 0;
4676
4677 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4678 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4679
4680 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4681 if (deasserted & (1 << index)) {
4682 group_mask = &bp->attn_group[index];
4683
4684 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4685 index,
4686 group_mask->sig[0], group_mask->sig[1],
4687 group_mask->sig[2], group_mask->sig[3],
4688 group_mask->sig[4]);
4689
4690 bnx2x_attn_int_deasserted4(bp,
4691 attn.sig[4] & group_mask->sig[4]);
4692 bnx2x_attn_int_deasserted3(bp,
4693 attn.sig[3] & group_mask->sig[3]);
4694 bnx2x_attn_int_deasserted1(bp,
4695 attn.sig[1] & group_mask->sig[1]);
4696 bnx2x_attn_int_deasserted2(bp,
4697 attn.sig[2] & group_mask->sig[2]);
4698 bnx2x_attn_int_deasserted0(bp,
4699 attn.sig[0] & group_mask->sig[0]);
4700 }
4701 }
4702
4703 bnx2x_release_alr(bp);
4704
4705 if (bp->common.int_block == INT_BLOCK_HC)
4706 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4707 COMMAND_REG_ATTN_BITS_CLR);
4708 else
4709 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4710
4711 val = ~deasserted;
4712 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4713 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4714 REG_WR(bp, reg_addr, val);
4715
4716 if (~bp->attn_state & deasserted)
4717 BNX2X_ERR("IGU ERROR\n");
4718
4719 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4720 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4721
4722 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4723 aeu_mask = REG_RD(bp, reg_addr);
4724
4725 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4726 aeu_mask, deasserted);
4727 aeu_mask |= (deasserted & 0x3ff);
4728 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4729
4730 REG_WR(bp, reg_addr, aeu_mask);
4731 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4732
4733 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4734 bp->attn_state &= ~deasserted;
4735 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4736 }
4737
4738 static void bnx2x_attn_int(struct bnx2x *bp)
4739 {
4740 /* read local copy of bits */
4741 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4742 attn_bits);
4743 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4744 attn_bits_ack);
4745 u32 attn_state = bp->attn_state;
4746
4747 /* look for changed bits */
4748 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4749 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4750
4751 DP(NETIF_MSG_HW,
4752 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4753 attn_bits, attn_ack, asserted, deasserted);
4754
4755 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4756 BNX2X_ERR("BAD attention state\n");
4757
4758 /* handle bits that were raised */
4759 if (asserted)
4760 bnx2x_attn_int_asserted(bp, asserted);
4761
4762 if (deasserted)
4763 bnx2x_attn_int_deasserted(bp, deasserted);
4764 }
4765
4766 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4767 u16 index, u8 op, u8 update)
4768 {
4769 u32 igu_addr = bp->igu_base_addr;
4770 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4771 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4772 igu_addr);
4773 }
4774
4775 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4776 {
4777 /* No memory barriers */
4778 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4779 mmiowb(); /* keep prod updates ordered */
4780 }
4781
4782 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4783 union event_ring_elem *elem)
4784 {
4785 u8 err = elem->message.error;
4786
4787 if (!bp->cnic_eth_dev.starting_cid ||
4788 (cid < bp->cnic_eth_dev.starting_cid &&
4789 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4790 return 1;
4791
4792 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4793
4794 if (unlikely(err)) {
4795
4796 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4797 cid);
4798 bnx2x_panic_dump(bp, false);
4799 }
4800 bnx2x_cnic_cfc_comp(bp, cid, err);
4801 return 0;
4802 }
4803
4804 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4805 {
4806 struct bnx2x_mcast_ramrod_params rparam;
4807 int rc;
4808
4809 memset(&rparam, 0, sizeof(rparam));
4810
4811 rparam.mcast_obj = &bp->mcast_obj;
4812
4813 netif_addr_lock_bh(bp->dev);
4814
4815 /* Clear pending state for the last command */
4816 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4817
4818 /* If there are pending mcast commands - send them */
4819 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4820 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4821 if (rc < 0)
4822 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4823 rc);
4824 }
4825
4826 netif_addr_unlock_bh(bp->dev);
4827 }
4828
4829 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4830 union event_ring_elem *elem)
4831 {
4832 unsigned long ramrod_flags = 0;
4833 int rc = 0;
4834 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4835 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4836
4837 /* Always push next commands out, don't wait here */
4838 __set_bit(RAMROD_CONT, &ramrod_flags);
4839
4840 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4841 >> BNX2X_SWCID_SHIFT) {
4842 case BNX2X_FILTER_MAC_PENDING:
4843 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4844 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4845 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4846 else
4847 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4848
4849 break;
4850 case BNX2X_FILTER_MCAST_PENDING:
4851 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4852 /* This is only relevant for 57710 where multicast MACs are
4853 * configured as unicast MACs using the same ramrod.
4854 */
4855 bnx2x_handle_mcast_eqe(bp);
4856 return;
4857 default:
4858 BNX2X_ERR("Unsupported classification command: %d\n",
4859 elem->message.data.eth_event.echo);
4860 return;
4861 }
4862
4863 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4864
4865 if (rc < 0)
4866 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4867 else if (rc > 0)
4868 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4869
4870 }
4871
4872 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4873
4874 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4875 {
4876 netif_addr_lock_bh(bp->dev);
4877
4878 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4879
4880 /* Send rx_mode command again if was requested */
4881 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4882 bnx2x_set_storm_rx_mode(bp);
4883 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4884 &bp->sp_state))
4885 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4886 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4887 &bp->sp_state))
4888 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4889
4890 netif_addr_unlock_bh(bp->dev);
4891 }
4892
4893 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4894 union event_ring_elem *elem)
4895 {
4896 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4897 DP(BNX2X_MSG_SP,
4898 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4899 elem->message.data.vif_list_event.func_bit_map);
4900 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4901 elem->message.data.vif_list_event.func_bit_map);
4902 } else if (elem->message.data.vif_list_event.echo ==
4903 VIF_LIST_RULE_SET) {
4904 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4905 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4906 }
4907 }
4908
4909 /* called with rtnl_lock */
4910 static void bnx2x_after_function_update(struct bnx2x *bp)
4911 {
4912 int q, rc;
4913 struct bnx2x_fastpath *fp;
4914 struct bnx2x_queue_state_params queue_params = {NULL};
4915 struct bnx2x_queue_update_params *q_update_params =
4916 &queue_params.params.update;
4917
4918 /* Send Q update command with afex vlan removal values for all Qs */
4919 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4920
4921 /* set silent vlan removal values according to vlan mode */
4922 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4923 &q_update_params->update_flags);
4924 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4925 &q_update_params->update_flags);
4926 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4927
4928 /* in access mode mark mask and value are 0 to strip all vlans */
4929 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4930 q_update_params->silent_removal_value = 0;
4931 q_update_params->silent_removal_mask = 0;
4932 } else {
4933 q_update_params->silent_removal_value =
4934 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4935 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4936 }
4937
4938 for_each_eth_queue(bp, q) {
4939 /* Set the appropriate Queue object */
4940 fp = &bp->fp[q];
4941 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4942
4943 /* send the ramrod */
4944 rc = bnx2x_queue_state_change(bp, &queue_params);
4945 if (rc < 0)
4946 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4947 q);
4948 }
4949
4950 if (!NO_FCOE(bp)) {
4951 fp = &bp->fp[FCOE_IDX(bp)];
4952 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4953
4954 /* clear pending completion bit */
4955 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4956
4957 /* mark latest Q bit */
4958 smp_mb__before_clear_bit();
4959 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4960 smp_mb__after_clear_bit();
4961
4962 /* send Q update ramrod for FCoE Q */
4963 rc = bnx2x_queue_state_change(bp, &queue_params);
4964 if (rc < 0)
4965 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4966 q);
4967 } else {
4968 /* If no FCoE ring - ACK MCP now */
4969 bnx2x_link_report(bp);
4970 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4971 }
4972 }
4973
4974 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4975 struct bnx2x *bp, u32 cid)
4976 {
4977 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4978
4979 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4980 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4981 else
4982 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4983 }
4984
4985 static void bnx2x_eq_int(struct bnx2x *bp)
4986 {
4987 u16 hw_cons, sw_cons, sw_prod;
4988 union event_ring_elem *elem;
4989 u8 echo;
4990 u32 cid;
4991 u8 opcode;
4992 int rc, spqe_cnt = 0;
4993 struct bnx2x_queue_sp_obj *q_obj;
4994 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4995 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4996
4997 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4998
4999 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5000 * when we get the the next-page we nned to adjust so the loop
5001 * condition below will be met. The next element is the size of a
5002 * regular element and hence incrementing by 1
5003 */
5004 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5005 hw_cons++;
5006
5007 /* This function may never run in parallel with itself for a
5008 * specific bp, thus there is no need in "paired" read memory
5009 * barrier here.
5010 */
5011 sw_cons = bp->eq_cons;
5012 sw_prod = bp->eq_prod;
5013
5014 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5015 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5016
5017 for (; sw_cons != hw_cons;
5018 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5019
5020 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5021
5022 rc = bnx2x_iov_eq_sp_event(bp, elem);
5023 if (!rc) {
5024 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5025 rc);
5026 goto next_spqe;
5027 }
5028
5029 /* elem CID originates from FW; actually LE */
5030 cid = SW_CID((__force __le32)
5031 elem->message.data.cfc_del_event.cid);
5032 opcode = elem->message.opcode;
5033
5034 /* handle eq element */
5035 switch (opcode) {
5036 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5037 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5038 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5039 continue;
5040
5041 case EVENT_RING_OPCODE_STAT_QUERY:
5042 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5043 "got statistics comp event %d\n",
5044 bp->stats_comp++);
5045 /* nothing to do with stats comp */
5046 goto next_spqe;
5047
5048 case EVENT_RING_OPCODE_CFC_DEL:
5049 /* handle according to cid range */
5050 /*
5051 * we may want to verify here that the bp state is
5052 * HALTING
5053 */
5054 DP(BNX2X_MSG_SP,
5055 "got delete ramrod for MULTI[%d]\n", cid);
5056
5057 if (CNIC_LOADED(bp) &&
5058 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5059 goto next_spqe;
5060
5061 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5062
5063 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5064 break;
5065
5066
5067
5068 goto next_spqe;
5069
5070 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5071 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5072 if (f_obj->complete_cmd(bp, f_obj,
5073 BNX2X_F_CMD_TX_STOP))
5074 break;
5075 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5076 goto next_spqe;
5077
5078 case EVENT_RING_OPCODE_START_TRAFFIC:
5079 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5080 if (f_obj->complete_cmd(bp, f_obj,
5081 BNX2X_F_CMD_TX_START))
5082 break;
5083 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5084 goto next_spqe;
5085
5086 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5087 echo = elem->message.data.function_update_event.echo;
5088 if (echo == SWITCH_UPDATE) {
5089 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5090 "got FUNC_SWITCH_UPDATE ramrod\n");
5091 if (f_obj->complete_cmd(
5092 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5093 break;
5094
5095 } else {
5096 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5097 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5098 f_obj->complete_cmd(bp, f_obj,
5099 BNX2X_F_CMD_AFEX_UPDATE);
5100
5101 /* We will perform the Queues update from
5102 * sp_rtnl task as all Queue SP operations
5103 * should run under rtnl_lock.
5104 */
5105 smp_mb__before_clear_bit();
5106 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5107 &bp->sp_rtnl_state);
5108 smp_mb__after_clear_bit();
5109
5110 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5111 }
5112
5113 goto next_spqe;
5114
5115 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5116 f_obj->complete_cmd(bp, f_obj,
5117 BNX2X_F_CMD_AFEX_VIFLISTS);
5118 bnx2x_after_afex_vif_lists(bp, elem);
5119 goto next_spqe;
5120 case EVENT_RING_OPCODE_FUNCTION_START:
5121 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5122 "got FUNC_START ramrod\n");
5123 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5124 break;
5125
5126 goto next_spqe;
5127
5128 case EVENT_RING_OPCODE_FUNCTION_STOP:
5129 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5130 "got FUNC_STOP ramrod\n");
5131 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5132 break;
5133
5134 goto next_spqe;
5135 }
5136
5137 switch (opcode | bp->state) {
5138 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5139 BNX2X_STATE_OPEN):
5140 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5141 BNX2X_STATE_OPENING_WAIT4_PORT):
5142 cid = elem->message.data.eth_event.echo &
5143 BNX2X_SWCID_MASK;
5144 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5145 cid);
5146 rss_raw->clear_pending(rss_raw);
5147 break;
5148
5149 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5150 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5151 case (EVENT_RING_OPCODE_SET_MAC |
5152 BNX2X_STATE_CLOSING_WAIT4_HALT):
5153 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5154 BNX2X_STATE_OPEN):
5155 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5156 BNX2X_STATE_DIAG):
5157 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5158 BNX2X_STATE_CLOSING_WAIT4_HALT):
5159 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5160 bnx2x_handle_classification_eqe(bp, elem);
5161 break;
5162
5163 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5164 BNX2X_STATE_OPEN):
5165 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5166 BNX2X_STATE_DIAG):
5167 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5168 BNX2X_STATE_CLOSING_WAIT4_HALT):
5169 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5170 bnx2x_handle_mcast_eqe(bp);
5171 break;
5172
5173 case (EVENT_RING_OPCODE_FILTERS_RULES |
5174 BNX2X_STATE_OPEN):
5175 case (EVENT_RING_OPCODE_FILTERS_RULES |
5176 BNX2X_STATE_DIAG):
5177 case (EVENT_RING_OPCODE_FILTERS_RULES |
5178 BNX2X_STATE_CLOSING_WAIT4_HALT):
5179 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5180 bnx2x_handle_rx_mode_eqe(bp);
5181 break;
5182 default:
5183 /* unknown event log error and continue */
5184 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5185 elem->message.opcode, bp->state);
5186 }
5187 next_spqe:
5188 spqe_cnt++;
5189 } /* for */
5190
5191 smp_mb__before_atomic_inc();
5192 atomic_add(spqe_cnt, &bp->eq_spq_left);
5193
5194 bp->eq_cons = sw_cons;
5195 bp->eq_prod = sw_prod;
5196 /* Make sure that above mem writes were issued towards the memory */
5197 smp_wmb();
5198
5199 /* update producer */
5200 bnx2x_update_eq_prod(bp, bp->eq_prod);
5201 }
5202
5203 static void bnx2x_sp_task(struct work_struct *work)
5204 {
5205 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5206
5207 DP(BNX2X_MSG_SP, "sp task invoked\n");
5208
5209 /* make sure the atomic interupt_occurred has been written */
5210 smp_rmb();
5211 if (atomic_read(&bp->interrupt_occurred)) {
5212
5213 /* what work needs to be performed? */
5214 u16 status = bnx2x_update_dsb_idx(bp);
5215
5216 DP(BNX2X_MSG_SP, "status %x\n", status);
5217 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5218 atomic_set(&bp->interrupt_occurred, 0);
5219
5220 /* HW attentions */
5221 if (status & BNX2X_DEF_SB_ATT_IDX) {
5222 bnx2x_attn_int(bp);
5223 status &= ~BNX2X_DEF_SB_ATT_IDX;
5224 }
5225
5226 /* SP events: STAT_QUERY and others */
5227 if (status & BNX2X_DEF_SB_IDX) {
5228 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5229
5230 if (FCOE_INIT(bp) &&
5231 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5232 /* Prevent local bottom-halves from running as
5233 * we are going to change the local NAPI list.
5234 */
5235 local_bh_disable();
5236 napi_schedule(&bnx2x_fcoe(bp, napi));
5237 local_bh_enable();
5238 }
5239
5240 /* Handle EQ completions */
5241 bnx2x_eq_int(bp);
5242 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5243 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5244
5245 status &= ~BNX2X_DEF_SB_IDX;
5246 }
5247
5248 /* if status is non zero then perhaps something went wrong */
5249 if (unlikely(status))
5250 DP(BNX2X_MSG_SP,
5251 "got an unknown interrupt! (status 0x%x)\n", status);
5252
5253 /* ack status block only if something was actually handled */
5254 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5255 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5256
5257 }
5258
5259 /* must be called after the EQ processing (since eq leads to sriov
5260 * ramrod completion flows).
5261 * This flow may have been scheduled by the arrival of a ramrod
5262 * completion, or by the sriov code rescheduling itself.
5263 */
5264 bnx2x_iov_sp_task(bp);
5265
5266 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5267 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5268 &bp->sp_state)) {
5269 bnx2x_link_report(bp);
5270 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5271 }
5272 }
5273
5274 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5275 {
5276 struct net_device *dev = dev_instance;
5277 struct bnx2x *bp = netdev_priv(dev);
5278
5279 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5280 IGU_INT_DISABLE, 0);
5281
5282 #ifdef BNX2X_STOP_ON_ERROR
5283 if (unlikely(bp->panic))
5284 return IRQ_HANDLED;
5285 #endif
5286
5287 if (CNIC_LOADED(bp)) {
5288 struct cnic_ops *c_ops;
5289
5290 rcu_read_lock();
5291 c_ops = rcu_dereference(bp->cnic_ops);
5292 if (c_ops)
5293 c_ops->cnic_handler(bp->cnic_data, NULL);
5294 rcu_read_unlock();
5295 }
5296
5297 /* schedule sp task to perform default status block work, ack
5298 * attentions and enable interrupts.
5299 */
5300 bnx2x_schedule_sp_task(bp);
5301
5302 return IRQ_HANDLED;
5303 }
5304
5305 /* end of slow path */
5306
5307
5308 void bnx2x_drv_pulse(struct bnx2x *bp)
5309 {
5310 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5311 bp->fw_drv_pulse_wr_seq);
5312 }
5313
5314 static void bnx2x_timer(unsigned long data)
5315 {
5316 struct bnx2x *bp = (struct bnx2x *) data;
5317
5318 if (!netif_running(bp->dev))
5319 return;
5320
5321 if (IS_PF(bp) &&
5322 !BP_NOMCP(bp)) {
5323 int mb_idx = BP_FW_MB_IDX(bp);
5324 u32 drv_pulse;
5325 u32 mcp_pulse;
5326
5327 ++bp->fw_drv_pulse_wr_seq;
5328 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5329 /* TBD - add SYSTEM_TIME */
5330 drv_pulse = bp->fw_drv_pulse_wr_seq;
5331 bnx2x_drv_pulse(bp);
5332
5333 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5334 MCP_PULSE_SEQ_MASK);
5335 /* The delta between driver pulse and mcp response
5336 * should be 1 (before mcp response) or 0 (after mcp response)
5337 */
5338 if ((drv_pulse != mcp_pulse) &&
5339 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5340 /* someone lost a heartbeat... */
5341 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5342 drv_pulse, mcp_pulse);
5343 }
5344 }
5345
5346 if (bp->state == BNX2X_STATE_OPEN)
5347 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5348
5349 /* sample pf vf bulletin board for new posts from pf */
5350 if (IS_VF(bp))
5351 bnx2x_sample_bulletin(bp);
5352
5353 mod_timer(&bp->timer, jiffies + bp->current_interval);
5354 }
5355
5356 /* end of Statistics */
5357
5358 /* nic init */
5359
5360 /*
5361 * nic init service functions
5362 */
5363
5364 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5365 {
5366 u32 i;
5367 if (!(len%4) && !(addr%4))
5368 for (i = 0; i < len; i += 4)
5369 REG_WR(bp, addr + i, fill);
5370 else
5371 for (i = 0; i < len; i++)
5372 REG_WR8(bp, addr + i, fill);
5373
5374 }
5375
5376 /* helper: writes FP SP data to FW - data_size in dwords */
5377 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5378 int fw_sb_id,
5379 u32 *sb_data_p,
5380 u32 data_size)
5381 {
5382 int index;
5383 for (index = 0; index < data_size; index++)
5384 REG_WR(bp, BAR_CSTRORM_INTMEM +
5385 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5386 sizeof(u32)*index,
5387 *(sb_data_p + index));
5388 }
5389
5390 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5391 {
5392 u32 *sb_data_p;
5393 u32 data_size = 0;
5394 struct hc_status_block_data_e2 sb_data_e2;
5395 struct hc_status_block_data_e1x sb_data_e1x;
5396
5397 /* disable the function first */
5398 if (!CHIP_IS_E1x(bp)) {
5399 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5400 sb_data_e2.common.state = SB_DISABLED;
5401 sb_data_e2.common.p_func.vf_valid = false;
5402 sb_data_p = (u32 *)&sb_data_e2;
5403 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5404 } else {
5405 memset(&sb_data_e1x, 0,
5406 sizeof(struct hc_status_block_data_e1x));
5407 sb_data_e1x.common.state = SB_DISABLED;
5408 sb_data_e1x.common.p_func.vf_valid = false;
5409 sb_data_p = (u32 *)&sb_data_e1x;
5410 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5411 }
5412 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5413
5414 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5415 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5416 CSTORM_STATUS_BLOCK_SIZE);
5417 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5418 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5419 CSTORM_SYNC_BLOCK_SIZE);
5420 }
5421
5422 /* helper: writes SP SB data to FW */
5423 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5424 struct hc_sp_status_block_data *sp_sb_data)
5425 {
5426 int func = BP_FUNC(bp);
5427 int i;
5428 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5429 REG_WR(bp, BAR_CSTRORM_INTMEM +
5430 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5431 i*sizeof(u32),
5432 *((u32 *)sp_sb_data + i));
5433 }
5434
5435 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5436 {
5437 int func = BP_FUNC(bp);
5438 struct hc_sp_status_block_data sp_sb_data;
5439 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5440
5441 sp_sb_data.state = SB_DISABLED;
5442 sp_sb_data.p_func.vf_valid = false;
5443
5444 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5445
5446 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5447 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5448 CSTORM_SP_STATUS_BLOCK_SIZE);
5449 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5450 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5451 CSTORM_SP_SYNC_BLOCK_SIZE);
5452
5453 }
5454
5455
5456 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5457 int igu_sb_id, int igu_seg_id)
5458 {
5459 hc_sm->igu_sb_id = igu_sb_id;
5460 hc_sm->igu_seg_id = igu_seg_id;
5461 hc_sm->timer_value = 0xFF;
5462 hc_sm->time_to_expire = 0xFFFFFFFF;
5463 }
5464
5465
5466 /* allocates state machine ids. */
5467 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5468 {
5469 /* zero out state machine indices */
5470 /* rx indices */
5471 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5472
5473 /* tx indices */
5474 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5475 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5476 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5477 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5478
5479 /* map indices */
5480 /* rx indices */
5481 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5482 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5483
5484 /* tx indices */
5485 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5486 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5487 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5488 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5489 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5490 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5491 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5492 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5493 }
5494
5495 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5496 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5497 {
5498 int igu_seg_id;
5499
5500 struct hc_status_block_data_e2 sb_data_e2;
5501 struct hc_status_block_data_e1x sb_data_e1x;
5502 struct hc_status_block_sm *hc_sm_p;
5503 int data_size;
5504 u32 *sb_data_p;
5505
5506 if (CHIP_INT_MODE_IS_BC(bp))
5507 igu_seg_id = HC_SEG_ACCESS_NORM;
5508 else
5509 igu_seg_id = IGU_SEG_ACCESS_NORM;
5510
5511 bnx2x_zero_fp_sb(bp, fw_sb_id);
5512
5513 if (!CHIP_IS_E1x(bp)) {
5514 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5515 sb_data_e2.common.state = SB_ENABLED;
5516 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5517 sb_data_e2.common.p_func.vf_id = vfid;
5518 sb_data_e2.common.p_func.vf_valid = vf_valid;
5519 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5520 sb_data_e2.common.same_igu_sb_1b = true;
5521 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5522 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5523 hc_sm_p = sb_data_e2.common.state_machine;
5524 sb_data_p = (u32 *)&sb_data_e2;
5525 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5526 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5527 } else {
5528 memset(&sb_data_e1x, 0,
5529 sizeof(struct hc_status_block_data_e1x));
5530 sb_data_e1x.common.state = SB_ENABLED;
5531 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5532 sb_data_e1x.common.p_func.vf_id = 0xff;
5533 sb_data_e1x.common.p_func.vf_valid = false;
5534 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5535 sb_data_e1x.common.same_igu_sb_1b = true;
5536 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5537 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5538 hc_sm_p = sb_data_e1x.common.state_machine;
5539 sb_data_p = (u32 *)&sb_data_e1x;
5540 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5541 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5542 }
5543
5544 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5545 igu_sb_id, igu_seg_id);
5546 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5547 igu_sb_id, igu_seg_id);
5548
5549 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5550
5551 /* write indices to HW - PCI guarantees endianity of regpairs */
5552 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5553 }
5554
5555 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5556 u16 tx_usec, u16 rx_usec)
5557 {
5558 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5559 false, rx_usec);
5560 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5561 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5562 tx_usec);
5563 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5564 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5565 tx_usec);
5566 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5567 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5568 tx_usec);
5569 }
5570
5571 static void bnx2x_init_def_sb(struct bnx2x *bp)
5572 {
5573 struct host_sp_status_block *def_sb = bp->def_status_blk;
5574 dma_addr_t mapping = bp->def_status_blk_mapping;
5575 int igu_sp_sb_index;
5576 int igu_seg_id;
5577 int port = BP_PORT(bp);
5578 int func = BP_FUNC(bp);
5579 int reg_offset, reg_offset_en5;
5580 u64 section;
5581 int index;
5582 struct hc_sp_status_block_data sp_sb_data;
5583 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5584
5585 if (CHIP_INT_MODE_IS_BC(bp)) {
5586 igu_sp_sb_index = DEF_SB_IGU_ID;
5587 igu_seg_id = HC_SEG_ACCESS_DEF;
5588 } else {
5589 igu_sp_sb_index = bp->igu_dsb_id;
5590 igu_seg_id = IGU_SEG_ACCESS_DEF;
5591 }
5592
5593 /* ATTN */
5594 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5595 atten_status_block);
5596 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5597
5598 bp->attn_state = 0;
5599
5600 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5601 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5602 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5603 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5604 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5605 int sindex;
5606 /* take care of sig[0]..sig[4] */
5607 for (sindex = 0; sindex < 4; sindex++)
5608 bp->attn_group[index].sig[sindex] =
5609 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5610
5611 if (!CHIP_IS_E1x(bp))
5612 /*
5613 * enable5 is separate from the rest of the registers,
5614 * and therefore the address skip is 4
5615 * and not 16 between the different groups
5616 */
5617 bp->attn_group[index].sig[4] = REG_RD(bp,
5618 reg_offset_en5 + 0x4*index);
5619 else
5620 bp->attn_group[index].sig[4] = 0;
5621 }
5622
5623 if (bp->common.int_block == INT_BLOCK_HC) {
5624 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5625 HC_REG_ATTN_MSG0_ADDR_L);
5626
5627 REG_WR(bp, reg_offset, U64_LO(section));
5628 REG_WR(bp, reg_offset + 4, U64_HI(section));
5629 } else if (!CHIP_IS_E1x(bp)) {
5630 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5631 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5632 }
5633
5634 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5635 sp_sb);
5636
5637 bnx2x_zero_sp_sb(bp);
5638
5639 /* PCI guarantees endianity of regpairs */
5640 sp_sb_data.state = SB_ENABLED;
5641 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5642 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5643 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5644 sp_sb_data.igu_seg_id = igu_seg_id;
5645 sp_sb_data.p_func.pf_id = func;
5646 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5647 sp_sb_data.p_func.vf_id = 0xff;
5648
5649 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5650
5651 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5652 }
5653
5654 void bnx2x_update_coalesce(struct bnx2x *bp)
5655 {
5656 int i;
5657
5658 for_each_eth_queue(bp, i)
5659 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5660 bp->tx_ticks, bp->rx_ticks);
5661 }
5662
5663 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5664 {
5665 spin_lock_init(&bp->spq_lock);
5666 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5667
5668 bp->spq_prod_idx = 0;
5669 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5670 bp->spq_prod_bd = bp->spq;
5671 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5672 }
5673
5674 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5675 {
5676 int i;
5677 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5678 union event_ring_elem *elem =
5679 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5680
5681 elem->next_page.addr.hi =
5682 cpu_to_le32(U64_HI(bp->eq_mapping +
5683 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5684 elem->next_page.addr.lo =
5685 cpu_to_le32(U64_LO(bp->eq_mapping +
5686 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5687 }
5688 bp->eq_cons = 0;
5689 bp->eq_prod = NUM_EQ_DESC;
5690 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5691 /* we want a warning message before it gets rought... */
5692 atomic_set(&bp->eq_spq_left,
5693 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5694 }
5695
5696 /* called with netif_addr_lock_bh() */
5697 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5698 unsigned long rx_mode_flags,
5699 unsigned long rx_accept_flags,
5700 unsigned long tx_accept_flags,
5701 unsigned long ramrod_flags)
5702 {
5703 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5704 int rc;
5705
5706 memset(&ramrod_param, 0, sizeof(ramrod_param));
5707
5708 /* Prepare ramrod parameters */
5709 ramrod_param.cid = 0;
5710 ramrod_param.cl_id = cl_id;
5711 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5712 ramrod_param.func_id = BP_FUNC(bp);
5713
5714 ramrod_param.pstate = &bp->sp_state;
5715 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5716
5717 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5718 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5719
5720 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5721
5722 ramrod_param.ramrod_flags = ramrod_flags;
5723 ramrod_param.rx_mode_flags = rx_mode_flags;
5724
5725 ramrod_param.rx_accept_flags = rx_accept_flags;
5726 ramrod_param.tx_accept_flags = tx_accept_flags;
5727
5728 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5729 if (rc < 0) {
5730 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5731 return rc;
5732 }
5733
5734 return 0;
5735 }
5736
5737 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5738 unsigned long *rx_accept_flags,
5739 unsigned long *tx_accept_flags)
5740 {
5741 /* Clear the flags first */
5742 *rx_accept_flags = 0;
5743 *tx_accept_flags = 0;
5744
5745 switch (rx_mode) {
5746 case BNX2X_RX_MODE_NONE:
5747 /*
5748 * 'drop all' supersedes any accept flags that may have been
5749 * passed to the function.
5750 */
5751 break;
5752 case BNX2X_RX_MODE_NORMAL:
5753 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5754 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5755 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5756
5757 /* internal switching mode */
5758 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5759 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5760 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5761
5762 break;
5763 case BNX2X_RX_MODE_ALLMULTI:
5764 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5765 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5766 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5767
5768 /* internal switching mode */
5769 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5770 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5771 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5772
5773 break;
5774 case BNX2X_RX_MODE_PROMISC:
5775 /* According to deffinition of SI mode, iface in promisc mode
5776 * should receive matched and unmatched (in resolution of port)
5777 * unicast packets.
5778 */
5779 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5780 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5781 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5782 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5783
5784 /* internal switching mode */
5785 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5786 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5787
5788 if (IS_MF_SI(bp))
5789 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5790 else
5791 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5792
5793 break;
5794 default:
5795 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5796 return -EINVAL;
5797 }
5798
5799 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5800 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5801 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5802 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5803 }
5804
5805 return 0;
5806 }
5807
5808 /* called with netif_addr_lock_bh() */
5809 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5810 {
5811 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5812 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5813 int rc;
5814
5815 if (!NO_FCOE(bp))
5816 /* Configure rx_mode of FCoE Queue */
5817 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5818
5819 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5820 &tx_accept_flags);
5821 if (rc)
5822 return rc;
5823
5824 __set_bit(RAMROD_RX, &ramrod_flags);
5825 __set_bit(RAMROD_TX, &ramrod_flags);
5826
5827 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5828 rx_accept_flags, tx_accept_flags,
5829 ramrod_flags);
5830 }
5831
5832 static void bnx2x_init_internal_common(struct bnx2x *bp)
5833 {
5834 int i;
5835
5836 if (IS_MF_SI(bp))
5837 /*
5838 * In switch independent mode, the TSTORM needs to accept
5839 * packets that failed classification, since approximate match
5840 * mac addresses aren't written to NIG LLH
5841 */
5842 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5843 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5844 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5845 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5846 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5847
5848 /* Zero this manually as its initialization is
5849 currently missing in the initTool */
5850 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5851 REG_WR(bp, BAR_USTRORM_INTMEM +
5852 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5853 if (!CHIP_IS_E1x(bp)) {
5854 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5855 CHIP_INT_MODE_IS_BC(bp) ?
5856 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5857 }
5858 }
5859
5860 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5861 {
5862 switch (load_code) {
5863 case FW_MSG_CODE_DRV_LOAD_COMMON:
5864 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5865 bnx2x_init_internal_common(bp);
5866 /* no break */
5867
5868 case FW_MSG_CODE_DRV_LOAD_PORT:
5869 /* nothing to do */
5870 /* no break */
5871
5872 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5873 /* internal memory per function is
5874 initialized inside bnx2x_pf_init */
5875 break;
5876
5877 default:
5878 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5879 break;
5880 }
5881 }
5882
5883 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5884 {
5885 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5886 }
5887
5888 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5889 {
5890 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5891 }
5892
5893 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5894 {
5895 if (CHIP_IS_E1x(fp->bp))
5896 return BP_L_ID(fp->bp) + fp->index;
5897 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5898 return bnx2x_fp_igu_sb_id(fp);
5899 }
5900
5901 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5902 {
5903 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5904 u8 cos;
5905 unsigned long q_type = 0;
5906 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5907 fp->rx_queue = fp_idx;
5908 fp->cid = fp_idx;
5909 fp->cl_id = bnx2x_fp_cl_id(fp);
5910 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5911 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5912 /* qZone id equals to FW (per path) client id */
5913 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5914
5915 /* init shortcut */
5916 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5917
5918 /* Setup SB indicies */
5919 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5920
5921 /* Configure Queue State object */
5922 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5923 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5924
5925 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5926
5927 /* init tx data */
5928 for_each_cos_in_tx_queue(fp, cos) {
5929 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5930 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5931 FP_COS_TO_TXQ(fp, cos, bp),
5932 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5933 cids[cos] = fp->txdata_ptr[cos]->cid;
5934 }
5935
5936 /* nothing more for vf to do here */
5937 if (IS_VF(bp))
5938 return;
5939
5940 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5941 fp->fw_sb_id, fp->igu_sb_id);
5942 bnx2x_update_fpsb_idx(fp);
5943 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5944 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5945 bnx2x_sp_mapping(bp, q_rdata), q_type);
5946
5947 /**
5948 * Configure classification DBs: Always enable Tx switching
5949 */
5950 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5951
5952 DP(NETIF_MSG_IFUP,
5953 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5954 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5955 fp->igu_sb_id);
5956 }
5957
5958 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5959 {
5960 int i;
5961
5962 for (i = 1; i <= NUM_TX_RINGS; i++) {
5963 struct eth_tx_next_bd *tx_next_bd =
5964 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5965
5966 tx_next_bd->addr_hi =
5967 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5968 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5969 tx_next_bd->addr_lo =
5970 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5971 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5972 }
5973
5974 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5975 txdata->tx_db.data.zero_fill1 = 0;
5976 txdata->tx_db.data.prod = 0;
5977
5978 txdata->tx_pkt_prod = 0;
5979 txdata->tx_pkt_cons = 0;
5980 txdata->tx_bd_prod = 0;
5981 txdata->tx_bd_cons = 0;
5982 txdata->tx_pkt = 0;
5983 }
5984
5985 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5986 {
5987 int i;
5988
5989 for_each_tx_queue_cnic(bp, i)
5990 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
5991 }
5992 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5993 {
5994 int i;
5995 u8 cos;
5996
5997 for_each_eth_queue(bp, i)
5998 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5999 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6000 }
6001
6002 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6003 {
6004 if (!NO_FCOE(bp))
6005 bnx2x_init_fcoe_fp(bp);
6006
6007 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6008 BNX2X_VF_ID_INVALID, false,
6009 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6010
6011 /* ensure status block indices were read */
6012 rmb();
6013 bnx2x_init_rx_rings_cnic(bp);
6014 bnx2x_init_tx_rings_cnic(bp);
6015
6016 /* flush all */
6017 mb();
6018 mmiowb();
6019 }
6020
6021 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
6022 {
6023 int i;
6024
6025 for_each_eth_queue(bp, i)
6026 bnx2x_init_eth_fp(bp, i);
6027
6028 /* ensure status block indices were read */
6029 rmb();
6030 bnx2x_init_rx_rings(bp);
6031 bnx2x_init_tx_rings(bp);
6032
6033 if (IS_VF(bp))
6034 return;
6035
6036 /* Initialize MOD_ABS interrupts */
6037 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6038 bp->common.shmem_base, bp->common.shmem2_base,
6039 BP_PORT(bp));
6040
6041 bnx2x_init_def_sb(bp);
6042 bnx2x_update_dsb_idx(bp);
6043 bnx2x_init_sp_ring(bp);
6044 bnx2x_init_eq_ring(bp);
6045 bnx2x_init_internal(bp, load_code);
6046 bnx2x_pf_init(bp);
6047 bnx2x_stats_init(bp);
6048
6049 /* flush all before enabling interrupts */
6050 mb();
6051 mmiowb();
6052
6053 bnx2x_int_enable(bp);
6054
6055 /* Check for SPIO5 */
6056 bnx2x_attn_int_deasserted0(bp,
6057 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6058 AEU_INPUTS_ATTN_BITS_SPIO5);
6059 }
6060
6061 /* end of nic init */
6062
6063 /*
6064 * gzip service functions
6065 */
6066
6067 static int bnx2x_gunzip_init(struct bnx2x *bp)
6068 {
6069 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6070 &bp->gunzip_mapping, GFP_KERNEL);
6071 if (bp->gunzip_buf == NULL)
6072 goto gunzip_nomem1;
6073
6074 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6075 if (bp->strm == NULL)
6076 goto gunzip_nomem2;
6077
6078 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6079 if (bp->strm->workspace == NULL)
6080 goto gunzip_nomem3;
6081
6082 return 0;
6083
6084 gunzip_nomem3:
6085 kfree(bp->strm);
6086 bp->strm = NULL;
6087
6088 gunzip_nomem2:
6089 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6090 bp->gunzip_mapping);
6091 bp->gunzip_buf = NULL;
6092
6093 gunzip_nomem1:
6094 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6095 return -ENOMEM;
6096 }
6097
6098 static void bnx2x_gunzip_end(struct bnx2x *bp)
6099 {
6100 if (bp->strm) {
6101 vfree(bp->strm->workspace);
6102 kfree(bp->strm);
6103 bp->strm = NULL;
6104 }
6105
6106 if (bp->gunzip_buf) {
6107 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6108 bp->gunzip_mapping);
6109 bp->gunzip_buf = NULL;
6110 }
6111 }
6112
6113 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6114 {
6115 int n, rc;
6116
6117 /* check gzip header */
6118 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6119 BNX2X_ERR("Bad gzip header\n");
6120 return -EINVAL;
6121 }
6122
6123 n = 10;
6124
6125 #define FNAME 0x8
6126
6127 if (zbuf[3] & FNAME)
6128 while ((zbuf[n++] != 0) && (n < len));
6129
6130 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6131 bp->strm->avail_in = len - n;
6132 bp->strm->next_out = bp->gunzip_buf;
6133 bp->strm->avail_out = FW_BUF_SIZE;
6134
6135 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6136 if (rc != Z_OK)
6137 return rc;
6138
6139 rc = zlib_inflate(bp->strm, Z_FINISH);
6140 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6141 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6142 bp->strm->msg);
6143
6144 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6145 if (bp->gunzip_outlen & 0x3)
6146 netdev_err(bp->dev,
6147 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6148 bp->gunzip_outlen);
6149 bp->gunzip_outlen >>= 2;
6150
6151 zlib_inflateEnd(bp->strm);
6152
6153 if (rc == Z_STREAM_END)
6154 return 0;
6155
6156 return rc;
6157 }
6158
6159 /* nic load/unload */
6160
6161 /*
6162 * General service functions
6163 */
6164
6165 /* send a NIG loopback debug packet */
6166 static void bnx2x_lb_pckt(struct bnx2x *bp)
6167 {
6168 u32 wb_write[3];
6169
6170 /* Ethernet source and destination addresses */
6171 wb_write[0] = 0x55555555;
6172 wb_write[1] = 0x55555555;
6173 wb_write[2] = 0x20; /* SOP */
6174 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6175
6176 /* NON-IP protocol */
6177 wb_write[0] = 0x09000000;
6178 wb_write[1] = 0x55555555;
6179 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6180 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6181 }
6182
6183 /* some of the internal memories
6184 * are not directly readable from the driver
6185 * to test them we send debug packets
6186 */
6187 static int bnx2x_int_mem_test(struct bnx2x *bp)
6188 {
6189 int factor;
6190 int count, i;
6191 u32 val = 0;
6192
6193 if (CHIP_REV_IS_FPGA(bp))
6194 factor = 120;
6195 else if (CHIP_REV_IS_EMUL(bp))
6196 factor = 200;
6197 else
6198 factor = 1;
6199
6200 /* Disable inputs of parser neighbor blocks */
6201 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6202 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6203 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6204 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6205
6206 /* Write 0 to parser credits for CFC search request */
6207 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6208
6209 /* send Ethernet packet */
6210 bnx2x_lb_pckt(bp);
6211
6212 /* TODO do i reset NIG statistic? */
6213 /* Wait until NIG register shows 1 packet of size 0x10 */
6214 count = 1000 * factor;
6215 while (count) {
6216
6217 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6218 val = *bnx2x_sp(bp, wb_data[0]);
6219 if (val == 0x10)
6220 break;
6221
6222 msleep(10);
6223 count--;
6224 }
6225 if (val != 0x10) {
6226 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6227 return -1;
6228 }
6229
6230 /* Wait until PRS register shows 1 packet */
6231 count = 1000 * factor;
6232 while (count) {
6233 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6234 if (val == 1)
6235 break;
6236
6237 msleep(10);
6238 count--;
6239 }
6240 if (val != 0x1) {
6241 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6242 return -2;
6243 }
6244
6245 /* Reset and init BRB, PRS */
6246 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6247 msleep(50);
6248 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6249 msleep(50);
6250 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6251 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6252
6253 DP(NETIF_MSG_HW, "part2\n");
6254
6255 /* Disable inputs of parser neighbor blocks */
6256 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6257 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6258 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6259 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6260
6261 /* Write 0 to parser credits for CFC search request */
6262 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6263
6264 /* send 10 Ethernet packets */
6265 for (i = 0; i < 10; i++)
6266 bnx2x_lb_pckt(bp);
6267
6268 /* Wait until NIG register shows 10 + 1
6269 packets of size 11*0x10 = 0xb0 */
6270 count = 1000 * factor;
6271 while (count) {
6272
6273 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6274 val = *bnx2x_sp(bp, wb_data[0]);
6275 if (val == 0xb0)
6276 break;
6277
6278 msleep(10);
6279 count--;
6280 }
6281 if (val != 0xb0) {
6282 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6283 return -3;
6284 }
6285
6286 /* Wait until PRS register shows 2 packets */
6287 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6288 if (val != 2)
6289 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6290
6291 /* Write 1 to parser credits for CFC search request */
6292 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6293
6294 /* Wait until PRS register shows 3 packets */
6295 msleep(10 * factor);
6296 /* Wait until NIG register shows 1 packet of size 0x10 */
6297 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6298 if (val != 3)
6299 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6300
6301 /* clear NIG EOP FIFO */
6302 for (i = 0; i < 11; i++)
6303 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6304 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6305 if (val != 1) {
6306 BNX2X_ERR("clear of NIG failed\n");
6307 return -4;
6308 }
6309
6310 /* Reset and init BRB, PRS, NIG */
6311 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6312 msleep(50);
6313 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6314 msleep(50);
6315 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6316 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6317 if (!CNIC_SUPPORT(bp))
6318 /* set NIC mode */
6319 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6320
6321 /* Enable inputs of parser neighbor blocks */
6322 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6323 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6324 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6325 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6326
6327 DP(NETIF_MSG_HW, "done\n");
6328
6329 return 0; /* OK */
6330 }
6331
6332 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6333 {
6334 u32 val;
6335
6336 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6337 if (!CHIP_IS_E1x(bp))
6338 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6339 else
6340 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6341 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6342 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6343 /*
6344 * mask read length error interrupts in brb for parser
6345 * (parsing unit and 'checksum and crc' unit)
6346 * these errors are legal (PU reads fixed length and CAC can cause
6347 * read length error on truncated packets)
6348 */
6349 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6350 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6351 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6352 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6353 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6354 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6355 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6356 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6357 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6358 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6359 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6360 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6361 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6362 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6363 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6364 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6365 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6366 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6367 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6368
6369 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6370 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6371 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6372 if (!CHIP_IS_E1x(bp))
6373 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6374 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6375 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6376
6377 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6378 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6379 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6380 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6381
6382 if (!CHIP_IS_E1x(bp))
6383 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6384 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6385
6386 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6387 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6388 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6389 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6390 }
6391
6392 static void bnx2x_reset_common(struct bnx2x *bp)
6393 {
6394 u32 val = 0x1400;
6395
6396 /* reset_common */
6397 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6398 0xd3ffff7f);
6399
6400 if (CHIP_IS_E3(bp)) {
6401 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6402 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6403 }
6404
6405 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6406 }
6407
6408 static void bnx2x_setup_dmae(struct bnx2x *bp)
6409 {
6410 bp->dmae_ready = 0;
6411 spin_lock_init(&bp->dmae_lock);
6412 }
6413
6414 static void bnx2x_init_pxp(struct bnx2x *bp)
6415 {
6416 u16 devctl;
6417 int r_order, w_order;
6418
6419 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6420 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6421 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6422 if (bp->mrrs == -1)
6423 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6424 else {
6425 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6426 r_order = bp->mrrs;
6427 }
6428
6429 bnx2x_init_pxp_arb(bp, r_order, w_order);
6430 }
6431
6432 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6433 {
6434 int is_required;
6435 u32 val;
6436 int port;
6437
6438 if (BP_NOMCP(bp))
6439 return;
6440
6441 is_required = 0;
6442 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6443 SHARED_HW_CFG_FAN_FAILURE_MASK;
6444
6445 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6446 is_required = 1;
6447
6448 /*
6449 * The fan failure mechanism is usually related to the PHY type since
6450 * the power consumption of the board is affected by the PHY. Currently,
6451 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6452 */
6453 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6454 for (port = PORT_0; port < PORT_MAX; port++) {
6455 is_required |=
6456 bnx2x_fan_failure_det_req(
6457 bp,
6458 bp->common.shmem_base,
6459 bp->common.shmem2_base,
6460 port);
6461 }
6462
6463 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6464
6465 if (is_required == 0)
6466 return;
6467
6468 /* Fan failure is indicated by SPIO 5 */
6469 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6470
6471 /* set to active low mode */
6472 val = REG_RD(bp, MISC_REG_SPIO_INT);
6473 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6474 REG_WR(bp, MISC_REG_SPIO_INT, val);
6475
6476 /* enable interrupt to signal the IGU */
6477 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6478 val |= MISC_SPIO_SPIO5;
6479 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6480 }
6481
6482 void bnx2x_pf_disable(struct bnx2x *bp)
6483 {
6484 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6485 val &= ~IGU_PF_CONF_FUNC_EN;
6486
6487 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6488 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6489 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6490 }
6491
6492 static void bnx2x__common_init_phy(struct bnx2x *bp)
6493 {
6494 u32 shmem_base[2], shmem2_base[2];
6495 /* Avoid common init in case MFW supports LFA */
6496 if (SHMEM2_RD(bp, size) >
6497 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6498 return;
6499 shmem_base[0] = bp->common.shmem_base;
6500 shmem2_base[0] = bp->common.shmem2_base;
6501 if (!CHIP_IS_E1x(bp)) {
6502 shmem_base[1] =
6503 SHMEM2_RD(bp, other_shmem_base_addr);
6504 shmem2_base[1] =
6505 SHMEM2_RD(bp, other_shmem2_base_addr);
6506 }
6507 bnx2x_acquire_phy_lock(bp);
6508 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6509 bp->common.chip_id);
6510 bnx2x_release_phy_lock(bp);
6511 }
6512
6513 /**
6514 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6515 *
6516 * @bp: driver handle
6517 */
6518 static int bnx2x_init_hw_common(struct bnx2x *bp)
6519 {
6520 u32 val;
6521
6522 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6523
6524 /*
6525 * take the RESET lock to protect undi_unload flow from accessing
6526 * registers while we're resetting the chip
6527 */
6528 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6529
6530 bnx2x_reset_common(bp);
6531 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6532
6533 val = 0xfffc;
6534 if (CHIP_IS_E3(bp)) {
6535 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6536 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6537 }
6538 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6539
6540 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6541
6542 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6543
6544 if (!CHIP_IS_E1x(bp)) {
6545 u8 abs_func_id;
6546
6547 /**
6548 * 4-port mode or 2-port mode we need to turn of master-enable
6549 * for everyone, after that, turn it back on for self.
6550 * so, we disregard multi-function or not, and always disable
6551 * for all functions on the given path, this means 0,2,4,6 for
6552 * path 0 and 1,3,5,7 for path 1
6553 */
6554 for (abs_func_id = BP_PATH(bp);
6555 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6556 if (abs_func_id == BP_ABS_FUNC(bp)) {
6557 REG_WR(bp,
6558 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6559 1);
6560 continue;
6561 }
6562
6563 bnx2x_pretend_func(bp, abs_func_id);
6564 /* clear pf enable */
6565 bnx2x_pf_disable(bp);
6566 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6567 }
6568 }
6569
6570 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6571 if (CHIP_IS_E1(bp)) {
6572 /* enable HW interrupt from PXP on USDM overflow
6573 bit 16 on INT_MASK_0 */
6574 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6575 }
6576
6577 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6578 bnx2x_init_pxp(bp);
6579
6580 #ifdef __BIG_ENDIAN
6581 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6582 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6583 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6584 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6585 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6586 /* make sure this value is 0 */
6587 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6588
6589 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6590 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6591 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6592 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6593 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6594 #endif
6595
6596 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6597
6598 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6599 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6600
6601 /* let the HW do it's magic ... */
6602 msleep(100);
6603 /* finish PXP init */
6604 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6605 if (val != 1) {
6606 BNX2X_ERR("PXP2 CFG failed\n");
6607 return -EBUSY;
6608 }
6609 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6610 if (val != 1) {
6611 BNX2X_ERR("PXP2 RD_INIT failed\n");
6612 return -EBUSY;
6613 }
6614
6615 /* Timers bug workaround E2 only. We need to set the entire ILT to
6616 * have entries with value "0" and valid bit on.
6617 * This needs to be done by the first PF that is loaded in a path
6618 * (i.e. common phase)
6619 */
6620 if (!CHIP_IS_E1x(bp)) {
6621 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6622 * (i.e. vnic3) to start even if it is marked as "scan-off".
6623 * This occurs when a different function (func2,3) is being marked
6624 * as "scan-off". Real-life scenario for example: if a driver is being
6625 * load-unloaded while func6,7 are down. This will cause the timer to access
6626 * the ilt, translate to a logical address and send a request to read/write.
6627 * Since the ilt for the function that is down is not valid, this will cause
6628 * a translation error which is unrecoverable.
6629 * The Workaround is intended to make sure that when this happens nothing fatal
6630 * will occur. The workaround:
6631 * 1. First PF driver which loads on a path will:
6632 * a. After taking the chip out of reset, by using pretend,
6633 * it will write "0" to the following registers of
6634 * the other vnics.
6635 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6636 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6637 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6638 * And for itself it will write '1' to
6639 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6640 * dmae-operations (writing to pram for example.)
6641 * note: can be done for only function 6,7 but cleaner this
6642 * way.
6643 * b. Write zero+valid to the entire ILT.
6644 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6645 * VNIC3 (of that port). The range allocated will be the
6646 * entire ILT. This is needed to prevent ILT range error.
6647 * 2. Any PF driver load flow:
6648 * a. ILT update with the physical addresses of the allocated
6649 * logical pages.
6650 * b. Wait 20msec. - note that this timeout is needed to make
6651 * sure there are no requests in one of the PXP internal
6652 * queues with "old" ILT addresses.
6653 * c. PF enable in the PGLC.
6654 * d. Clear the was_error of the PF in the PGLC. (could have
6655 * occurred while driver was down)
6656 * e. PF enable in the CFC (WEAK + STRONG)
6657 * f. Timers scan enable
6658 * 3. PF driver unload flow:
6659 * a. Clear the Timers scan_en.
6660 * b. Polling for scan_on=0 for that PF.
6661 * c. Clear the PF enable bit in the PXP.
6662 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6663 * e. Write zero+valid to all ILT entries (The valid bit must
6664 * stay set)
6665 * f. If this is VNIC 3 of a port then also init
6666 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6667 * to the last enrty in the ILT.
6668 *
6669 * Notes:
6670 * Currently the PF error in the PGLC is non recoverable.
6671 * In the future the there will be a recovery routine for this error.
6672 * Currently attention is masked.
6673 * Having an MCP lock on the load/unload process does not guarantee that
6674 * there is no Timer disable during Func6/7 enable. This is because the
6675 * Timers scan is currently being cleared by the MCP on FLR.
6676 * Step 2.d can be done only for PF6/7 and the driver can also check if
6677 * there is error before clearing it. But the flow above is simpler and
6678 * more general.
6679 * All ILT entries are written by zero+valid and not just PF6/7
6680 * ILT entries since in the future the ILT entries allocation for
6681 * PF-s might be dynamic.
6682 */
6683 struct ilt_client_info ilt_cli;
6684 struct bnx2x_ilt ilt;
6685 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6686 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6687
6688 /* initialize dummy TM client */
6689 ilt_cli.start = 0;
6690 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6691 ilt_cli.client_num = ILT_CLIENT_TM;
6692
6693 /* Step 1: set zeroes to all ilt page entries with valid bit on
6694 * Step 2: set the timers first/last ilt entry to point
6695 * to the entire range to prevent ILT range error for 3rd/4th
6696 * vnic (this code assumes existence of the vnic)
6697 *
6698 * both steps performed by call to bnx2x_ilt_client_init_op()
6699 * with dummy TM client
6700 *
6701 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6702 * and his brother are split registers
6703 */
6704 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6705 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6706 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6707
6708 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6709 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6710 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6711 }
6712
6713 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6714 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6715
6716 if (!CHIP_IS_E1x(bp)) {
6717 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6718 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6719 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6720
6721 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6722
6723 /* let the HW do it's magic ... */
6724 do {
6725 msleep(200);
6726 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6727 } while (factor-- && (val != 1));
6728
6729 if (val != 1) {
6730 BNX2X_ERR("ATC_INIT failed\n");
6731 return -EBUSY;
6732 }
6733 }
6734
6735 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6736
6737 bnx2x_iov_init_dmae(bp);
6738
6739 /* clean the DMAE memory */
6740 bp->dmae_ready = 1;
6741 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6742
6743 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6744
6745 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6746
6747 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6748
6749 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6750
6751 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6752 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6753 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6754 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6755
6756 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6757
6758
6759 /* QM queues pointers table */
6760 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6761
6762 /* soft reset pulse */
6763 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6764 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6765
6766 if (CNIC_SUPPORT(bp))
6767 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6768
6769 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6770 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6771 if (!CHIP_REV_IS_SLOW(bp))
6772 /* enable hw interrupt from doorbell Q */
6773 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6774
6775 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6776
6777 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6778 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6779
6780 if (!CHIP_IS_E1(bp))
6781 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6782
6783 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6784 if (IS_MF_AFEX(bp)) {
6785 /* configure that VNTag and VLAN headers must be
6786 * received in afex mode
6787 */
6788 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6789 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6790 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6791 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6792 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6793 } else {
6794 /* Bit-map indicating which L2 hdrs may appear
6795 * after the basic Ethernet header
6796 */
6797 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6798 bp->path_has_ovlan ? 7 : 6);
6799 }
6800 }
6801
6802 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6803 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6804 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6805 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6806
6807 if (!CHIP_IS_E1x(bp)) {
6808 /* reset VFC memories */
6809 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6810 VFC_MEMORIES_RST_REG_CAM_RST |
6811 VFC_MEMORIES_RST_REG_RAM_RST);
6812 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6813 VFC_MEMORIES_RST_REG_CAM_RST |
6814 VFC_MEMORIES_RST_REG_RAM_RST);
6815
6816 msleep(20);
6817 }
6818
6819 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6820 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6821 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6822 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6823
6824 /* sync semi rtc */
6825 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6826 0x80000000);
6827 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6828 0x80000000);
6829
6830 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6831 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6832 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6833
6834 if (!CHIP_IS_E1x(bp)) {
6835 if (IS_MF_AFEX(bp)) {
6836 /* configure that VNTag and VLAN headers must be
6837 * sent in afex mode
6838 */
6839 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6840 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6841 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6842 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6843 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6844 } else {
6845 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6846 bp->path_has_ovlan ? 7 : 6);
6847 }
6848 }
6849
6850 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6851
6852 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6853
6854 if (CNIC_SUPPORT(bp)) {
6855 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6856 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6857 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6858 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6859 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6860 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6861 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6862 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6863 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6864 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6865 }
6866 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6867
6868 if (sizeof(union cdu_context) != 1024)
6869 /* we currently assume that a context is 1024 bytes */
6870 dev_alert(&bp->pdev->dev,
6871 "please adjust the size of cdu_context(%ld)\n",
6872 (long)sizeof(union cdu_context));
6873
6874 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6875 val = (4 << 24) + (0 << 12) + 1024;
6876 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6877
6878 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6879 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6880 /* enable context validation interrupt from CFC */
6881 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6882
6883 /* set the thresholds to prevent CFC/CDU race */
6884 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6885
6886 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6887
6888 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6889 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6890
6891 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6892 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6893
6894 /* Reset PCIE errors for debug */
6895 REG_WR(bp, 0x2814, 0xffffffff);
6896 REG_WR(bp, 0x3820, 0xffffffff);
6897
6898 if (!CHIP_IS_E1x(bp)) {
6899 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6900 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6901 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6902 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6903 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6904 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6905 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6906 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6907 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6908 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6909 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6910 }
6911
6912 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6913 if (!CHIP_IS_E1(bp)) {
6914 /* in E3 this done in per-port section */
6915 if (!CHIP_IS_E3(bp))
6916 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6917 }
6918 if (CHIP_IS_E1H(bp))
6919 /* not applicable for E2 (and above ...) */
6920 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6921
6922 if (CHIP_REV_IS_SLOW(bp))
6923 msleep(200);
6924
6925 /* finish CFC init */
6926 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6927 if (val != 1) {
6928 BNX2X_ERR("CFC LL_INIT failed\n");
6929 return -EBUSY;
6930 }
6931 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6932 if (val != 1) {
6933 BNX2X_ERR("CFC AC_INIT failed\n");
6934 return -EBUSY;
6935 }
6936 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6937 if (val != 1) {
6938 BNX2X_ERR("CFC CAM_INIT failed\n");
6939 return -EBUSY;
6940 }
6941 REG_WR(bp, CFC_REG_DEBUG0, 0);
6942
6943 if (CHIP_IS_E1(bp)) {
6944 /* read NIG statistic
6945 to see if this is our first up since powerup */
6946 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6947 val = *bnx2x_sp(bp, wb_data[0]);
6948
6949 /* do internal memory self test */
6950 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6951 BNX2X_ERR("internal mem self test failed\n");
6952 return -EBUSY;
6953 }
6954 }
6955
6956 bnx2x_setup_fan_failure_detection(bp);
6957
6958 /* clear PXP2 attentions */
6959 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6960
6961 bnx2x_enable_blocks_attention(bp);
6962 bnx2x_enable_blocks_parity(bp);
6963
6964 if (!BP_NOMCP(bp)) {
6965 if (CHIP_IS_E1x(bp))
6966 bnx2x__common_init_phy(bp);
6967 } else
6968 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6969
6970 return 0;
6971 }
6972
6973 /**
6974 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6975 *
6976 * @bp: driver handle
6977 */
6978 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6979 {
6980 int rc = bnx2x_init_hw_common(bp);
6981
6982 if (rc)
6983 return rc;
6984
6985 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6986 if (!BP_NOMCP(bp))
6987 bnx2x__common_init_phy(bp);
6988
6989 return 0;
6990 }
6991
6992 static int bnx2x_init_hw_port(struct bnx2x *bp)
6993 {
6994 int port = BP_PORT(bp);
6995 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6996 u32 low, high;
6997 u32 val;
6998
6999
7000 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7001
7002 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7003
7004 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7005 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7006 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7007
7008 /* Timers bug workaround: disables the pf_master bit in pglue at
7009 * common phase, we need to enable it here before any dmae access are
7010 * attempted. Therefore we manually added the enable-master to the
7011 * port phase (it also happens in the function phase)
7012 */
7013 if (!CHIP_IS_E1x(bp))
7014 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7015
7016 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7017 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7018 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7019 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7020
7021 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7022 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7023 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7024 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7025
7026 /* QM cid (connection) count */
7027 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7028
7029 if (CNIC_SUPPORT(bp)) {
7030 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7031 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7032 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7033 }
7034
7035 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7036
7037 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7038
7039 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7040
7041 if (IS_MF(bp))
7042 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7043 else if (bp->dev->mtu > 4096) {
7044 if (bp->flags & ONE_PORT_FLAG)
7045 low = 160;
7046 else {
7047 val = bp->dev->mtu;
7048 /* (24*1024 + val*4)/256 */
7049 low = 96 + (val/64) +
7050 ((val % 64) ? 1 : 0);
7051 }
7052 } else
7053 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7054 high = low + 56; /* 14*1024/256 */
7055 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7056 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7057 }
7058
7059 if (CHIP_MODE_IS_4_PORT(bp))
7060 REG_WR(bp, (BP_PORT(bp) ?
7061 BRB1_REG_MAC_GUARANTIED_1 :
7062 BRB1_REG_MAC_GUARANTIED_0), 40);
7063
7064
7065 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7066 if (CHIP_IS_E3B0(bp)) {
7067 if (IS_MF_AFEX(bp)) {
7068 /* configure headers for AFEX mode */
7069 REG_WR(bp, BP_PORT(bp) ?
7070 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7071 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7072 REG_WR(bp, BP_PORT(bp) ?
7073 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7074 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7075 REG_WR(bp, BP_PORT(bp) ?
7076 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7077 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7078 } else {
7079 /* Ovlan exists only if we are in multi-function +
7080 * switch-dependent mode, in switch-independent there
7081 * is no ovlan headers
7082 */
7083 REG_WR(bp, BP_PORT(bp) ?
7084 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7085 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7086 (bp->path_has_ovlan ? 7 : 6));
7087 }
7088 }
7089
7090 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7091 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7092 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7093 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7094
7095 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7096 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7097 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7098 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7099
7100 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7101 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7102
7103 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7104
7105 if (CHIP_IS_E1x(bp)) {
7106 /* configure PBF to work without PAUSE mtu 9000 */
7107 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7108
7109 /* update threshold */
7110 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7111 /* update init credit */
7112 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7113
7114 /* probe changes */
7115 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7116 udelay(50);
7117 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7118 }
7119
7120 if (CNIC_SUPPORT(bp))
7121 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7122
7123 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7124 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7125
7126 if (CHIP_IS_E1(bp)) {
7127 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7128 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7129 }
7130 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7131
7132 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7133
7134 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7135 /* init aeu_mask_attn_func_0/1:
7136 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7137 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7138 * bits 4-7 are used for "per vn group attention" */
7139 val = IS_MF(bp) ? 0xF7 : 0x7;
7140 /* Enable DCBX attention for all but E1 */
7141 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7142 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7143
7144 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7145
7146 if (!CHIP_IS_E1x(bp)) {
7147 /* Bit-map indicating which L2 hdrs may appear after the
7148 * basic Ethernet header
7149 */
7150 if (IS_MF_AFEX(bp))
7151 REG_WR(bp, BP_PORT(bp) ?
7152 NIG_REG_P1_HDRS_AFTER_BASIC :
7153 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7154 else
7155 REG_WR(bp, BP_PORT(bp) ?
7156 NIG_REG_P1_HDRS_AFTER_BASIC :
7157 NIG_REG_P0_HDRS_AFTER_BASIC,
7158 IS_MF_SD(bp) ? 7 : 6);
7159
7160 if (CHIP_IS_E3(bp))
7161 REG_WR(bp, BP_PORT(bp) ?
7162 NIG_REG_LLH1_MF_MODE :
7163 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7164 }
7165 if (!CHIP_IS_E3(bp))
7166 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7167
7168 if (!CHIP_IS_E1(bp)) {
7169 /* 0x2 disable mf_ov, 0x1 enable */
7170 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7171 (IS_MF_SD(bp) ? 0x1 : 0x2));
7172
7173 if (!CHIP_IS_E1x(bp)) {
7174 val = 0;
7175 switch (bp->mf_mode) {
7176 case MULTI_FUNCTION_SD:
7177 val = 1;
7178 break;
7179 case MULTI_FUNCTION_SI:
7180 case MULTI_FUNCTION_AFEX:
7181 val = 2;
7182 break;
7183 }
7184
7185 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7186 NIG_REG_LLH0_CLS_TYPE), val);
7187 }
7188 {
7189 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7190 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7191 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7192 }
7193 }
7194
7195 /* If SPIO5 is set to generate interrupts, enable it for this port */
7196 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7197 if (val & MISC_SPIO_SPIO5) {
7198 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7199 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7200 val = REG_RD(bp, reg_addr);
7201 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7202 REG_WR(bp, reg_addr, val);
7203 }
7204
7205 return 0;
7206 }
7207
7208 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7209 {
7210 int reg;
7211 u32 wb_write[2];
7212
7213 if (CHIP_IS_E1(bp))
7214 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7215 else
7216 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7217
7218 wb_write[0] = ONCHIP_ADDR1(addr);
7219 wb_write[1] = ONCHIP_ADDR2(addr);
7220 REG_WR_DMAE(bp, reg, wb_write, 2);
7221 }
7222
7223 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7224 {
7225 u32 data, ctl, cnt = 100;
7226 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7227 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7228 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7229 u32 sb_bit = 1 << (idu_sb_id%32);
7230 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7231 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7232
7233 /* Not supported in BC mode */
7234 if (CHIP_INT_MODE_IS_BC(bp))
7235 return;
7236
7237 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7238 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7239 IGU_REGULAR_CLEANUP_SET |
7240 IGU_REGULAR_BCLEANUP;
7241
7242 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7243 func_encode << IGU_CTRL_REG_FID_SHIFT |
7244 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7245
7246 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7247 data, igu_addr_data);
7248 REG_WR(bp, igu_addr_data, data);
7249 mmiowb();
7250 barrier();
7251 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7252 ctl, igu_addr_ctl);
7253 REG_WR(bp, igu_addr_ctl, ctl);
7254 mmiowb();
7255 barrier();
7256
7257 /* wait for clean up to finish */
7258 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7259 msleep(20);
7260
7261
7262 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7263 DP(NETIF_MSG_HW,
7264 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7265 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7266 }
7267 }
7268
7269 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7270 {
7271 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7272 }
7273
7274 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7275 {
7276 u32 i, base = FUNC_ILT_BASE(func);
7277 for (i = base; i < base + ILT_PER_FUNC; i++)
7278 bnx2x_ilt_wr(bp, i, 0);
7279 }
7280
7281
7282 static void bnx2x_init_searcher(struct bnx2x *bp)
7283 {
7284 int port = BP_PORT(bp);
7285 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7286 /* T1 hash bits value determines the T1 number of entries */
7287 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7288 }
7289
7290 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7291 {
7292 int rc;
7293 struct bnx2x_func_state_params func_params = {NULL};
7294 struct bnx2x_func_switch_update_params *switch_update_params =
7295 &func_params.params.switch_update;
7296
7297 /* Prepare parameters for function state transitions */
7298 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7299 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7300
7301 func_params.f_obj = &bp->func_obj;
7302 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7303
7304 /* Function parameters */
7305 switch_update_params->suspend = suspend;
7306
7307 rc = bnx2x_func_state_change(bp, &func_params);
7308
7309 return rc;
7310 }
7311
7312 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7313 {
7314 int rc, i, port = BP_PORT(bp);
7315 int vlan_en = 0, mac_en[NUM_MACS];
7316
7317
7318 /* Close input from network */
7319 if (bp->mf_mode == SINGLE_FUNCTION) {
7320 bnx2x_set_rx_filter(&bp->link_params, 0);
7321 } else {
7322 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7323 NIG_REG_LLH0_FUNC_EN);
7324 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7325 NIG_REG_LLH0_FUNC_EN, 0);
7326 for (i = 0; i < NUM_MACS; i++) {
7327 mac_en[i] = REG_RD(bp, port ?
7328 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7329 4 * i) :
7330 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7331 4 * i));
7332 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7333 4 * i) :
7334 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7335 }
7336 }
7337
7338 /* Close BMC to host */
7339 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7340 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7341
7342 /* Suspend Tx switching to the PF. Completion of this ramrod
7343 * further guarantees that all the packets of that PF / child
7344 * VFs in BRB were processed by the Parser, so it is safe to
7345 * change the NIC_MODE register.
7346 */
7347 rc = bnx2x_func_switch_update(bp, 1);
7348 if (rc) {
7349 BNX2X_ERR("Can't suspend tx-switching!\n");
7350 return rc;
7351 }
7352
7353 /* Change NIC_MODE register */
7354 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7355
7356 /* Open input from network */
7357 if (bp->mf_mode == SINGLE_FUNCTION) {
7358 bnx2x_set_rx_filter(&bp->link_params, 1);
7359 } else {
7360 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7361 NIG_REG_LLH0_FUNC_EN, vlan_en);
7362 for (i = 0; i < NUM_MACS; i++) {
7363 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7364 4 * i) :
7365 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7366 mac_en[i]);
7367 }
7368 }
7369
7370 /* Enable BMC to host */
7371 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7372 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7373
7374 /* Resume Tx switching to the PF */
7375 rc = bnx2x_func_switch_update(bp, 0);
7376 if (rc) {
7377 BNX2X_ERR("Can't resume tx-switching!\n");
7378 return rc;
7379 }
7380
7381 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7382 return 0;
7383 }
7384
7385 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7386 {
7387 int rc;
7388
7389 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7390
7391 if (CONFIGURE_NIC_MODE(bp)) {
7392 /* Configrue searcher as part of function hw init */
7393 bnx2x_init_searcher(bp);
7394
7395 /* Reset NIC mode */
7396 rc = bnx2x_reset_nic_mode(bp);
7397 if (rc)
7398 BNX2X_ERR("Can't change NIC mode!\n");
7399 return rc;
7400 }
7401
7402 return 0;
7403 }
7404
7405 static int bnx2x_init_hw_func(struct bnx2x *bp)
7406 {
7407 int port = BP_PORT(bp);
7408 int func = BP_FUNC(bp);
7409 int init_phase = PHASE_PF0 + func;
7410 struct bnx2x_ilt *ilt = BP_ILT(bp);
7411 u16 cdu_ilt_start;
7412 u32 addr, val;
7413 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7414 int i, main_mem_width, rc;
7415
7416 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7417
7418 /* FLR cleanup - hmmm */
7419 if (!CHIP_IS_E1x(bp)) {
7420 rc = bnx2x_pf_flr_clnup(bp);
7421 if (rc) {
7422 bnx2x_fw_dump(bp);
7423 return rc;
7424 }
7425 }
7426
7427 /* set MSI reconfigure capability */
7428 if (bp->common.int_block == INT_BLOCK_HC) {
7429 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7430 val = REG_RD(bp, addr);
7431 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7432 REG_WR(bp, addr, val);
7433 }
7434
7435 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7436 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7437
7438 ilt = BP_ILT(bp);
7439 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7440
7441 if (IS_SRIOV(bp))
7442 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7443 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7444
7445 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7446 * those of the VFs, so start line should be reset
7447 */
7448 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7449 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7450 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7451 ilt->lines[cdu_ilt_start + i].page_mapping =
7452 bp->context[i].cxt_mapping;
7453 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7454 }
7455
7456 bnx2x_ilt_init_op(bp, INITOP_SET);
7457
7458 if (!CONFIGURE_NIC_MODE(bp)) {
7459 bnx2x_init_searcher(bp);
7460 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7461 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7462 } else {
7463 /* Set NIC mode */
7464 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7465 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7466
7467 }
7468
7469 if (!CHIP_IS_E1x(bp)) {
7470 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7471
7472 /* Turn on a single ISR mode in IGU if driver is going to use
7473 * INT#x or MSI
7474 */
7475 if (!(bp->flags & USING_MSIX_FLAG))
7476 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7477 /*
7478 * Timers workaround bug: function init part.
7479 * Need to wait 20msec after initializing ILT,
7480 * needed to make sure there are no requests in
7481 * one of the PXP internal queues with "old" ILT addresses
7482 */
7483 msleep(20);
7484 /*
7485 * Master enable - Due to WB DMAE writes performed before this
7486 * register is re-initialized as part of the regular function
7487 * init
7488 */
7489 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7490 /* Enable the function in IGU */
7491 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7492 }
7493
7494 bp->dmae_ready = 1;
7495
7496 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7497
7498 if (!CHIP_IS_E1x(bp))
7499 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7500
7501 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7502 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7503 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7504 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7505 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7506 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7507 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7508 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7509 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7510 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7511 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7512 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7513 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7514
7515 if (!CHIP_IS_E1x(bp))
7516 REG_WR(bp, QM_REG_PF_EN, 1);
7517
7518 if (!CHIP_IS_E1x(bp)) {
7519 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7520 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7521 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7522 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7523 }
7524 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7525
7526 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7527 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7528
7529 bnx2x_iov_init_dq(bp);
7530
7531 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7532 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7533 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7534 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7535 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7536 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7537 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7538 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7539 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7540 if (!CHIP_IS_E1x(bp))
7541 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7542
7543 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7544
7545 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7546
7547 if (!CHIP_IS_E1x(bp))
7548 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7549
7550 if (IS_MF(bp)) {
7551 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7552 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7553 }
7554
7555 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7556
7557 /* HC init per function */
7558 if (bp->common.int_block == INT_BLOCK_HC) {
7559 if (CHIP_IS_E1H(bp)) {
7560 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7561
7562 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7563 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7564 }
7565 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7566
7567 } else {
7568 int num_segs, sb_idx, prod_offset;
7569
7570 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7571
7572 if (!CHIP_IS_E1x(bp)) {
7573 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7574 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7575 }
7576
7577 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7578
7579 if (!CHIP_IS_E1x(bp)) {
7580 int dsb_idx = 0;
7581 /**
7582 * Producer memory:
7583 * E2 mode: address 0-135 match to the mapping memory;
7584 * 136 - PF0 default prod; 137 - PF1 default prod;
7585 * 138 - PF2 default prod; 139 - PF3 default prod;
7586 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7587 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7588 * 144-147 reserved.
7589 *
7590 * E1.5 mode - In backward compatible mode;
7591 * for non default SB; each even line in the memory
7592 * holds the U producer and each odd line hold
7593 * the C producer. The first 128 producers are for
7594 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7595 * producers are for the DSB for each PF.
7596 * Each PF has five segments: (the order inside each
7597 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7598 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7599 * 144-147 attn prods;
7600 */
7601 /* non-default-status-blocks */
7602 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7603 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7604 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7605 prod_offset = (bp->igu_base_sb + sb_idx) *
7606 num_segs;
7607
7608 for (i = 0; i < num_segs; i++) {
7609 addr = IGU_REG_PROD_CONS_MEMORY +
7610 (prod_offset + i) * 4;
7611 REG_WR(bp, addr, 0);
7612 }
7613 /* send consumer update with value 0 */
7614 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7615 USTORM_ID, 0, IGU_INT_NOP, 1);
7616 bnx2x_igu_clear_sb(bp,
7617 bp->igu_base_sb + sb_idx);
7618 }
7619
7620 /* default-status-blocks */
7621 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7622 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7623
7624 if (CHIP_MODE_IS_4_PORT(bp))
7625 dsb_idx = BP_FUNC(bp);
7626 else
7627 dsb_idx = BP_VN(bp);
7628
7629 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7630 IGU_BC_BASE_DSB_PROD + dsb_idx :
7631 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7632
7633 /*
7634 * igu prods come in chunks of E1HVN_MAX (4) -
7635 * does not matters what is the current chip mode
7636 */
7637 for (i = 0; i < (num_segs * E1HVN_MAX);
7638 i += E1HVN_MAX) {
7639 addr = IGU_REG_PROD_CONS_MEMORY +
7640 (prod_offset + i)*4;
7641 REG_WR(bp, addr, 0);
7642 }
7643 /* send consumer update with 0 */
7644 if (CHIP_INT_MODE_IS_BC(bp)) {
7645 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7646 USTORM_ID, 0, IGU_INT_NOP, 1);
7647 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7648 CSTORM_ID, 0, IGU_INT_NOP, 1);
7649 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7650 XSTORM_ID, 0, IGU_INT_NOP, 1);
7651 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7652 TSTORM_ID, 0, IGU_INT_NOP, 1);
7653 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7654 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7655 } else {
7656 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7657 USTORM_ID, 0, IGU_INT_NOP, 1);
7658 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7659 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7660 }
7661 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7662
7663 /* !!! these should become driver const once
7664 rf-tool supports split-68 const */
7665 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7666 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7667 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7668 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7669 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7670 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7671 }
7672 }
7673
7674 /* Reset PCIE errors for debug */
7675 REG_WR(bp, 0x2114, 0xffffffff);
7676 REG_WR(bp, 0x2120, 0xffffffff);
7677
7678 if (CHIP_IS_E1x(bp)) {
7679 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7680 main_mem_base = HC_REG_MAIN_MEMORY +
7681 BP_PORT(bp) * (main_mem_size * 4);
7682 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7683 main_mem_width = 8;
7684
7685 val = REG_RD(bp, main_mem_prty_clr);
7686 if (val)
7687 DP(NETIF_MSG_HW,
7688 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7689 val);
7690
7691 /* Clear "false" parity errors in MSI-X table */
7692 for (i = main_mem_base;
7693 i < main_mem_base + main_mem_size * 4;
7694 i += main_mem_width) {
7695 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7696 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7697 i, main_mem_width / 4);
7698 }
7699 /* Clear HC parity attention */
7700 REG_RD(bp, main_mem_prty_clr);
7701 }
7702
7703 #ifdef BNX2X_STOP_ON_ERROR
7704 /* Enable STORMs SP logging */
7705 REG_WR8(bp, BAR_USTRORM_INTMEM +
7706 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7707 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7708 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7709 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7710 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7711 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7712 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7713 #endif
7714
7715 bnx2x_phy_probe(&bp->link_params);
7716
7717 return 0;
7718 }
7719
7720
7721 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7722 {
7723 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7724
7725 if (!CHIP_IS_E1x(bp))
7726 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7727 sizeof(struct host_hc_status_block_e2));
7728 else
7729 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7730 sizeof(struct host_hc_status_block_e1x));
7731
7732 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7733 }
7734
7735 void bnx2x_free_mem(struct bnx2x *bp)
7736 {
7737 int i;
7738
7739 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7740 sizeof(struct host_sp_status_block));
7741
7742 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7743 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7744
7745 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7746 sizeof(struct bnx2x_slowpath));
7747
7748 for (i = 0; i < L2_ILT_LINES(bp); i++)
7749 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7750 bp->context[i].size);
7751 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7752
7753 BNX2X_FREE(bp->ilt->lines);
7754
7755 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7756
7757 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7758 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7759
7760 bnx2x_iov_free_mem(bp);
7761 }
7762
7763
7764 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7765 {
7766 if (!CHIP_IS_E1x(bp))
7767 /* size = the status block + ramrod buffers */
7768 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7769 sizeof(struct host_hc_status_block_e2));
7770 else
7771 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7772 &bp->cnic_sb_mapping,
7773 sizeof(struct
7774 host_hc_status_block_e1x));
7775
7776 if (CONFIGURE_NIC_MODE(bp))
7777 /* allocate searcher T2 table, as it wan't allocated before */
7778 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7779
7780 /* write address to which L5 should insert its values */
7781 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7782 &bp->slowpath->drv_info_to_mcp;
7783
7784 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7785 goto alloc_mem_err;
7786
7787 return 0;
7788
7789 alloc_mem_err:
7790 bnx2x_free_mem_cnic(bp);
7791 BNX2X_ERR("Can't allocate memory\n");
7792 return -ENOMEM;
7793 }
7794
7795 int bnx2x_alloc_mem(struct bnx2x *bp)
7796 {
7797 int i, allocated, context_size;
7798
7799 if (!CONFIGURE_NIC_MODE(bp))
7800 /* allocate searcher T2 table */
7801 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7802
7803 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7804 sizeof(struct host_sp_status_block));
7805
7806 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7807 sizeof(struct bnx2x_slowpath));
7808
7809 /* Allocate memory for CDU context:
7810 * This memory is allocated separately and not in the generic ILT
7811 * functions because CDU differs in few aspects:
7812 * 1. There are multiple entities allocating memory for context -
7813 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7814 * its own ILT lines.
7815 * 2. Since CDU page-size is not a single 4KB page (which is the case
7816 * for the other ILT clients), to be efficient we want to support
7817 * allocation of sub-page-size in the last entry.
7818 * 3. Context pointers are used by the driver to pass to FW / update
7819 * the context (for the other ILT clients the pointers are used just to
7820 * free the memory during unload).
7821 */
7822 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7823
7824 for (i = 0, allocated = 0; allocated < context_size; i++) {
7825 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7826 (context_size - allocated));
7827 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7828 &bp->context[i].cxt_mapping,
7829 bp->context[i].size);
7830 allocated += bp->context[i].size;
7831 }
7832 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7833
7834 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7835 goto alloc_mem_err;
7836
7837 if (bnx2x_iov_alloc_mem(bp))
7838 goto alloc_mem_err;
7839
7840 /* Slow path ring */
7841 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7842
7843 /* EQ */
7844 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7845 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7846
7847 return 0;
7848
7849 alloc_mem_err:
7850 bnx2x_free_mem(bp);
7851 BNX2X_ERR("Can't allocate memory\n");
7852 return -ENOMEM;
7853 }
7854
7855 /*
7856 * Init service functions
7857 */
7858
7859 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7860 struct bnx2x_vlan_mac_obj *obj, bool set,
7861 int mac_type, unsigned long *ramrod_flags)
7862 {
7863 int rc;
7864 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7865
7866 memset(&ramrod_param, 0, sizeof(ramrod_param));
7867
7868 /* Fill general parameters */
7869 ramrod_param.vlan_mac_obj = obj;
7870 ramrod_param.ramrod_flags = *ramrod_flags;
7871
7872 /* Fill a user request section if needed */
7873 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7874 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7875
7876 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7877
7878 /* Set the command: ADD or DEL */
7879 if (set)
7880 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7881 else
7882 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7883 }
7884
7885 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7886
7887 if (rc == -EEXIST) {
7888 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7889 /* do not treat adding same MAC as error */
7890 rc = 0;
7891 } else if (rc < 0)
7892 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7893
7894 return rc;
7895 }
7896
7897 int bnx2x_del_all_macs(struct bnx2x *bp,
7898 struct bnx2x_vlan_mac_obj *mac_obj,
7899 int mac_type, bool wait_for_comp)
7900 {
7901 int rc;
7902 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7903
7904 /* Wait for completion of requested */
7905 if (wait_for_comp)
7906 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7907
7908 /* Set the mac type of addresses we want to clear */
7909 __set_bit(mac_type, &vlan_mac_flags);
7910
7911 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7912 if (rc < 0)
7913 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7914
7915 return rc;
7916 }
7917
7918 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7919 {
7920 unsigned long ramrod_flags = 0;
7921
7922 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7923 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7924 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7925 "Ignoring Zero MAC for STORAGE SD mode\n");
7926 return 0;
7927 }
7928
7929 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7930
7931 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7932 /* Eth MAC is set on RSS leading client (fp[0]) */
7933 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7934 set, BNX2X_ETH_MAC, &ramrod_flags);
7935 }
7936
7937 int bnx2x_setup_leading(struct bnx2x *bp)
7938 {
7939 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7940 }
7941
7942 /**
7943 * bnx2x_set_int_mode - configure interrupt mode
7944 *
7945 * @bp: driver handle
7946 *
7947 * In case of MSI-X it will also try to enable MSI-X.
7948 */
7949 int bnx2x_set_int_mode(struct bnx2x *bp)
7950 {
7951 int rc = 0;
7952
7953 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7954 return -EINVAL;
7955
7956 switch (int_mode) {
7957 case BNX2X_INT_MODE_MSIX:
7958 /* attempt to enable msix */
7959 rc = bnx2x_enable_msix(bp);
7960
7961 /* msix attained */
7962 if (!rc)
7963 return 0;
7964
7965 /* vfs use only msix */
7966 if (rc && IS_VF(bp))
7967 return rc;
7968
7969 /* failed to enable multiple MSI-X */
7970 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7971 bp->num_queues,
7972 1 + bp->num_cnic_queues);
7973
7974 /* falling through... */
7975 case BNX2X_INT_MODE_MSI:
7976 bnx2x_enable_msi(bp);
7977
7978 /* falling through... */
7979 case BNX2X_INT_MODE_INTX:
7980 bp->num_ethernet_queues = 1;
7981 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7982 BNX2X_DEV_INFO("set number of queues to 1\n");
7983 break;
7984 default:
7985 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7986 return -EINVAL;
7987 }
7988 return 0;
7989 }
7990
7991 /* must be called prior to any HW initializations */
7992 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7993 {
7994 if (IS_SRIOV(bp))
7995 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
7996 return L2_ILT_LINES(bp);
7997 }
7998
7999 void bnx2x_ilt_set_info(struct bnx2x *bp)
8000 {
8001 struct ilt_client_info *ilt_client;
8002 struct bnx2x_ilt *ilt = BP_ILT(bp);
8003 u16 line = 0;
8004
8005 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8006 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8007
8008 /* CDU */
8009 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8010 ilt_client->client_num = ILT_CLIENT_CDU;
8011 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8012 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8013 ilt_client->start = line;
8014 line += bnx2x_cid_ilt_lines(bp);
8015
8016 if (CNIC_SUPPORT(bp))
8017 line += CNIC_ILT_LINES;
8018 ilt_client->end = line - 1;
8019
8020 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8021 ilt_client->start,
8022 ilt_client->end,
8023 ilt_client->page_size,
8024 ilt_client->flags,
8025 ilog2(ilt_client->page_size >> 12));
8026
8027 /* QM */
8028 if (QM_INIT(bp->qm_cid_count)) {
8029 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8030 ilt_client->client_num = ILT_CLIENT_QM;
8031 ilt_client->page_size = QM_ILT_PAGE_SZ;
8032 ilt_client->flags = 0;
8033 ilt_client->start = line;
8034
8035 /* 4 bytes for each cid */
8036 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8037 QM_ILT_PAGE_SZ);
8038
8039 ilt_client->end = line - 1;
8040
8041 DP(NETIF_MSG_IFUP,
8042 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8043 ilt_client->start,
8044 ilt_client->end,
8045 ilt_client->page_size,
8046 ilt_client->flags,
8047 ilog2(ilt_client->page_size >> 12));
8048
8049 }
8050
8051 if (CNIC_SUPPORT(bp)) {
8052 /* SRC */
8053 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8054 ilt_client->client_num = ILT_CLIENT_SRC;
8055 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8056 ilt_client->flags = 0;
8057 ilt_client->start = line;
8058 line += SRC_ILT_LINES;
8059 ilt_client->end = line - 1;
8060
8061 DP(NETIF_MSG_IFUP,
8062 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8063 ilt_client->start,
8064 ilt_client->end,
8065 ilt_client->page_size,
8066 ilt_client->flags,
8067 ilog2(ilt_client->page_size >> 12));
8068
8069 /* TM */
8070 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8071 ilt_client->client_num = ILT_CLIENT_TM;
8072 ilt_client->page_size = TM_ILT_PAGE_SZ;
8073 ilt_client->flags = 0;
8074 ilt_client->start = line;
8075 line += TM_ILT_LINES;
8076 ilt_client->end = line - 1;
8077
8078 DP(NETIF_MSG_IFUP,
8079 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8080 ilt_client->start,
8081 ilt_client->end,
8082 ilt_client->page_size,
8083 ilt_client->flags,
8084 ilog2(ilt_client->page_size >> 12));
8085 }
8086
8087 BUG_ON(line > ILT_MAX_LINES);
8088 }
8089
8090 /**
8091 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8092 *
8093 * @bp: driver handle
8094 * @fp: pointer to fastpath
8095 * @init_params: pointer to parameters structure
8096 *
8097 * parameters configured:
8098 * - HC configuration
8099 * - Queue's CDU context
8100 */
8101 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8102 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8103 {
8104
8105 u8 cos;
8106 int cxt_index, cxt_offset;
8107
8108 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8109 if (!IS_FCOE_FP(fp)) {
8110 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8111 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8112
8113 /* If HC is supporterd, enable host coalescing in the transition
8114 * to INIT state.
8115 */
8116 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8117 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8118
8119 /* HC rate */
8120 init_params->rx.hc_rate = bp->rx_ticks ?
8121 (1000000 / bp->rx_ticks) : 0;
8122 init_params->tx.hc_rate = bp->tx_ticks ?
8123 (1000000 / bp->tx_ticks) : 0;
8124
8125 /* FW SB ID */
8126 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8127 fp->fw_sb_id;
8128
8129 /*
8130 * CQ index among the SB indices: FCoE clients uses the default
8131 * SB, therefore it's different.
8132 */
8133 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8134 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8135 }
8136
8137 /* set maximum number of COSs supported by this queue */
8138 init_params->max_cos = fp->max_cos;
8139
8140 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8141 fp->index, init_params->max_cos);
8142
8143 /* set the context pointers queue object */
8144 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8145 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8146 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8147 ILT_PAGE_CIDS);
8148 init_params->cxts[cos] =
8149 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8150 }
8151 }
8152
8153 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8154 struct bnx2x_queue_state_params *q_params,
8155 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8156 int tx_index, bool leading)
8157 {
8158 memset(tx_only_params, 0, sizeof(*tx_only_params));
8159
8160 /* Set the command */
8161 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8162
8163 /* Set tx-only QUEUE flags: don't zero statistics */
8164 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8165
8166 /* choose the index of the cid to send the slow path on */
8167 tx_only_params->cid_index = tx_index;
8168
8169 /* Set general TX_ONLY_SETUP parameters */
8170 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8171
8172 /* Set Tx TX_ONLY_SETUP parameters */
8173 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8174
8175 DP(NETIF_MSG_IFUP,
8176 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8177 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8178 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8179 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8180
8181 /* send the ramrod */
8182 return bnx2x_queue_state_change(bp, q_params);
8183 }
8184
8185
8186 /**
8187 * bnx2x_setup_queue - setup queue
8188 *
8189 * @bp: driver handle
8190 * @fp: pointer to fastpath
8191 * @leading: is leading
8192 *
8193 * This function performs 2 steps in a Queue state machine
8194 * actually: 1) RESET->INIT 2) INIT->SETUP
8195 */
8196
8197 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8198 bool leading)
8199 {
8200 struct bnx2x_queue_state_params q_params = {NULL};
8201 struct bnx2x_queue_setup_params *setup_params =
8202 &q_params.params.setup;
8203 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8204 &q_params.params.tx_only;
8205 int rc;
8206 u8 tx_index;
8207
8208 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8209
8210 /* reset IGU state skip FCoE L2 queue */
8211 if (!IS_FCOE_FP(fp))
8212 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8213 IGU_INT_ENABLE, 0);
8214
8215 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8216 /* We want to wait for completion in this context */
8217 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8218
8219 /* Prepare the INIT parameters */
8220 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8221
8222 /* Set the command */
8223 q_params.cmd = BNX2X_Q_CMD_INIT;
8224
8225 /* Change the state to INIT */
8226 rc = bnx2x_queue_state_change(bp, &q_params);
8227 if (rc) {
8228 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8229 return rc;
8230 }
8231
8232 DP(NETIF_MSG_IFUP, "init complete\n");
8233
8234
8235 /* Now move the Queue to the SETUP state... */
8236 memset(setup_params, 0, sizeof(*setup_params));
8237
8238 /* Set QUEUE flags */
8239 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8240
8241 /* Set general SETUP parameters */
8242 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8243 FIRST_TX_COS_INDEX);
8244
8245 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8246 &setup_params->rxq_params);
8247
8248 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8249 FIRST_TX_COS_INDEX);
8250
8251 /* Set the command */
8252 q_params.cmd = BNX2X_Q_CMD_SETUP;
8253
8254 if (IS_FCOE_FP(fp))
8255 bp->fcoe_init = true;
8256
8257 /* Change the state to SETUP */
8258 rc = bnx2x_queue_state_change(bp, &q_params);
8259 if (rc) {
8260 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8261 return rc;
8262 }
8263
8264 /* loop through the relevant tx-only indices */
8265 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8266 tx_index < fp->max_cos;
8267 tx_index++) {
8268
8269 /* prepare and send tx-only ramrod*/
8270 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8271 tx_only_params, tx_index, leading);
8272 if (rc) {
8273 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8274 fp->index, tx_index);
8275 return rc;
8276 }
8277 }
8278
8279 return rc;
8280 }
8281
8282 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8283 {
8284 struct bnx2x_fastpath *fp = &bp->fp[index];
8285 struct bnx2x_fp_txdata *txdata;
8286 struct bnx2x_queue_state_params q_params = {NULL};
8287 int rc, tx_index;
8288
8289 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8290
8291 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8292 /* We want to wait for completion in this context */
8293 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8294
8295
8296 /* close tx-only connections */
8297 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8298 tx_index < fp->max_cos;
8299 tx_index++){
8300
8301 /* ascertain this is a normal queue*/
8302 txdata = fp->txdata_ptr[tx_index];
8303
8304 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8305 txdata->txq_index);
8306
8307 /* send halt terminate on tx-only connection */
8308 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8309 memset(&q_params.params.terminate, 0,
8310 sizeof(q_params.params.terminate));
8311 q_params.params.terminate.cid_index = tx_index;
8312
8313 rc = bnx2x_queue_state_change(bp, &q_params);
8314 if (rc)
8315 return rc;
8316
8317 /* send halt terminate on tx-only connection */
8318 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8319 memset(&q_params.params.cfc_del, 0,
8320 sizeof(q_params.params.cfc_del));
8321 q_params.params.cfc_del.cid_index = tx_index;
8322 rc = bnx2x_queue_state_change(bp, &q_params);
8323 if (rc)
8324 return rc;
8325 }
8326 /* Stop the primary connection: */
8327 /* ...halt the connection */
8328 q_params.cmd = BNX2X_Q_CMD_HALT;
8329 rc = bnx2x_queue_state_change(bp, &q_params);
8330 if (rc)
8331 return rc;
8332
8333 /* ...terminate the connection */
8334 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8335 memset(&q_params.params.terminate, 0,
8336 sizeof(q_params.params.terminate));
8337 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8338 rc = bnx2x_queue_state_change(bp, &q_params);
8339 if (rc)
8340 return rc;
8341 /* ...delete cfc entry */
8342 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8343 memset(&q_params.params.cfc_del, 0,
8344 sizeof(q_params.params.cfc_del));
8345 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8346 return bnx2x_queue_state_change(bp, &q_params);
8347 }
8348
8349
8350 static void bnx2x_reset_func(struct bnx2x *bp)
8351 {
8352 int port = BP_PORT(bp);
8353 int func = BP_FUNC(bp);
8354 int i;
8355
8356 /* Disable the function in the FW */
8357 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8358 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8359 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8360 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8361
8362 /* FP SBs */
8363 for_each_eth_queue(bp, i) {
8364 struct bnx2x_fastpath *fp = &bp->fp[i];
8365 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8366 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8367 SB_DISABLED);
8368 }
8369
8370 if (CNIC_LOADED(bp))
8371 /* CNIC SB */
8372 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8373 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8374 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8375
8376 /* SP SB */
8377 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8378 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8379 SB_DISABLED);
8380
8381 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8382 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8383 0);
8384
8385 /* Configure IGU */
8386 if (bp->common.int_block == INT_BLOCK_HC) {
8387 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8388 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8389 } else {
8390 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8391 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8392 }
8393
8394 if (CNIC_LOADED(bp)) {
8395 /* Disable Timer scan */
8396 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8397 /*
8398 * Wait for at least 10ms and up to 2 second for the timers
8399 * scan to complete
8400 */
8401 for (i = 0; i < 200; i++) {
8402 msleep(10);
8403 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8404 break;
8405 }
8406 }
8407 /* Clear ILT */
8408 bnx2x_clear_func_ilt(bp, func);
8409
8410 /* Timers workaround bug for E2: if this is vnic-3,
8411 * we need to set the entire ilt range for this timers.
8412 */
8413 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8414 struct ilt_client_info ilt_cli;
8415 /* use dummy TM client */
8416 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8417 ilt_cli.start = 0;
8418 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8419 ilt_cli.client_num = ILT_CLIENT_TM;
8420
8421 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8422 }
8423
8424 /* this assumes that reset_port() called before reset_func()*/
8425 if (!CHIP_IS_E1x(bp))
8426 bnx2x_pf_disable(bp);
8427
8428 bp->dmae_ready = 0;
8429 }
8430
8431 static void bnx2x_reset_port(struct bnx2x *bp)
8432 {
8433 int port = BP_PORT(bp);
8434 u32 val;
8435
8436 /* Reset physical Link */
8437 bnx2x__link_reset(bp);
8438
8439 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8440
8441 /* Do not rcv packets to BRB */
8442 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8443 /* Do not direct rcv packets that are not for MCP to the BRB */
8444 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8445 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8446
8447 /* Configure AEU */
8448 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8449
8450 msleep(100);
8451 /* Check for BRB port occupancy */
8452 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8453 if (val)
8454 DP(NETIF_MSG_IFDOWN,
8455 "BRB1 is not empty %d blocks are occupied\n", val);
8456
8457 /* TODO: Close Doorbell port? */
8458 }
8459
8460 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8461 {
8462 struct bnx2x_func_state_params func_params = {NULL};
8463
8464 /* Prepare parameters for function state transitions */
8465 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8466
8467 func_params.f_obj = &bp->func_obj;
8468 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8469
8470 func_params.params.hw_init.load_phase = load_code;
8471
8472 return bnx2x_func_state_change(bp, &func_params);
8473 }
8474
8475 static int bnx2x_func_stop(struct bnx2x *bp)
8476 {
8477 struct bnx2x_func_state_params func_params = {NULL};
8478 int rc;
8479
8480 /* Prepare parameters for function state transitions */
8481 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8482 func_params.f_obj = &bp->func_obj;
8483 func_params.cmd = BNX2X_F_CMD_STOP;
8484
8485 /*
8486 * Try to stop the function the 'good way'. If fails (in case
8487 * of a parity error during bnx2x_chip_cleanup()) and we are
8488 * not in a debug mode, perform a state transaction in order to
8489 * enable further HW_RESET transaction.
8490 */
8491 rc = bnx2x_func_state_change(bp, &func_params);
8492 if (rc) {
8493 #ifdef BNX2X_STOP_ON_ERROR
8494 return rc;
8495 #else
8496 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8497 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8498 return bnx2x_func_state_change(bp, &func_params);
8499 #endif
8500 }
8501
8502 return 0;
8503 }
8504
8505 /**
8506 * bnx2x_send_unload_req - request unload mode from the MCP.
8507 *
8508 * @bp: driver handle
8509 * @unload_mode: requested function's unload mode
8510 *
8511 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8512 */
8513 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8514 {
8515 u32 reset_code = 0;
8516 int port = BP_PORT(bp);
8517
8518 /* Select the UNLOAD request mode */
8519 if (unload_mode == UNLOAD_NORMAL)
8520 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8521
8522 else if (bp->flags & NO_WOL_FLAG)
8523 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8524
8525 else if (bp->wol) {
8526 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8527 u8 *mac_addr = bp->dev->dev_addr;
8528 u32 val;
8529 u16 pmc;
8530
8531 /* The mac address is written to entries 1-4 to
8532 * preserve entry 0 which is used by the PMF
8533 */
8534 u8 entry = (BP_VN(bp) + 1)*8;
8535
8536 val = (mac_addr[0] << 8) | mac_addr[1];
8537 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8538
8539 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8540 (mac_addr[4] << 8) | mac_addr[5];
8541 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8542
8543 /* Enable the PME and clear the status */
8544 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8545 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8546 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8547
8548 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8549
8550 } else
8551 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8552
8553 /* Send the request to the MCP */
8554 if (!BP_NOMCP(bp))
8555 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8556 else {
8557 int path = BP_PATH(bp);
8558
8559 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8560 path, load_count[path][0], load_count[path][1],
8561 load_count[path][2]);
8562 load_count[path][0]--;
8563 load_count[path][1 + port]--;
8564 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8565 path, load_count[path][0], load_count[path][1],
8566 load_count[path][2]);
8567 if (load_count[path][0] == 0)
8568 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8569 else if (load_count[path][1 + port] == 0)
8570 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8571 else
8572 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8573 }
8574
8575 return reset_code;
8576 }
8577
8578 /**
8579 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8580 *
8581 * @bp: driver handle
8582 * @keep_link: true iff link should be kept up
8583 */
8584 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8585 {
8586 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8587
8588 /* Report UNLOAD_DONE to MCP */
8589 if (!BP_NOMCP(bp))
8590 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8591 }
8592
8593 static int bnx2x_func_wait_started(struct bnx2x *bp)
8594 {
8595 int tout = 50;
8596 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8597
8598 if (!bp->port.pmf)
8599 return 0;
8600
8601 /*
8602 * (assumption: No Attention from MCP at this stage)
8603 * PMF probably in the middle of TXdisable/enable transaction
8604 * 1. Sync IRS for default SB
8605 * 2. Sync SP queue - this guarantes us that attention handling started
8606 * 3. Wait, that TXdisable/enable transaction completes
8607 *
8608 * 1+2 guranty that if DCBx attention was scheduled it already changed
8609 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8610 * received complettion for the transaction the state is TX_STOPPED.
8611 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8612 * transaction.
8613 */
8614
8615 /* make sure default SB ISR is done */
8616 if (msix)
8617 synchronize_irq(bp->msix_table[0].vector);
8618 else
8619 synchronize_irq(bp->pdev->irq);
8620
8621 flush_workqueue(bnx2x_wq);
8622
8623 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8624 BNX2X_F_STATE_STARTED && tout--)
8625 msleep(20);
8626
8627 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8628 BNX2X_F_STATE_STARTED) {
8629 #ifdef BNX2X_STOP_ON_ERROR
8630 BNX2X_ERR("Wrong function state\n");
8631 return -EBUSY;
8632 #else
8633 /*
8634 * Failed to complete the transaction in a "good way"
8635 * Force both transactions with CLR bit
8636 */
8637 struct bnx2x_func_state_params func_params = {NULL};
8638
8639 DP(NETIF_MSG_IFDOWN,
8640 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8641
8642 func_params.f_obj = &bp->func_obj;
8643 __set_bit(RAMROD_DRV_CLR_ONLY,
8644 &func_params.ramrod_flags);
8645
8646 /* STARTED-->TX_ST0PPED */
8647 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8648 bnx2x_func_state_change(bp, &func_params);
8649
8650 /* TX_ST0PPED-->STARTED */
8651 func_params.cmd = BNX2X_F_CMD_TX_START;
8652 return bnx2x_func_state_change(bp, &func_params);
8653 #endif
8654 }
8655
8656 return 0;
8657 }
8658
8659 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8660 {
8661 int port = BP_PORT(bp);
8662 int i, rc = 0;
8663 u8 cos;
8664 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8665 u32 reset_code;
8666
8667 /* Wait until tx fastpath tasks complete */
8668 for_each_tx_queue(bp, i) {
8669 struct bnx2x_fastpath *fp = &bp->fp[i];
8670
8671 for_each_cos_in_tx_queue(fp, cos)
8672 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8673 #ifdef BNX2X_STOP_ON_ERROR
8674 if (rc)
8675 return;
8676 #endif
8677 }
8678
8679 /* Give HW time to discard old tx messages */
8680 usleep_range(1000, 2000);
8681
8682 /* Clean all ETH MACs */
8683 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8684 false);
8685 if (rc < 0)
8686 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8687
8688 /* Clean up UC list */
8689 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8690 true);
8691 if (rc < 0)
8692 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8693 rc);
8694
8695 /* Disable LLH */
8696 if (!CHIP_IS_E1(bp))
8697 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8698
8699 /* Set "drop all" (stop Rx).
8700 * We need to take a netif_addr_lock() here in order to prevent
8701 * a race between the completion code and this code.
8702 */
8703 netif_addr_lock_bh(bp->dev);
8704 /* Schedule the rx_mode command */
8705 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8706 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8707 else
8708 bnx2x_set_storm_rx_mode(bp);
8709
8710 /* Cleanup multicast configuration */
8711 rparam.mcast_obj = &bp->mcast_obj;
8712 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8713 if (rc < 0)
8714 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8715
8716 netif_addr_unlock_bh(bp->dev);
8717
8718 bnx2x_iov_chip_cleanup(bp);
8719
8720
8721 /*
8722 * Send the UNLOAD_REQUEST to the MCP. This will return if
8723 * this function should perform FUNC, PORT or COMMON HW
8724 * reset.
8725 */
8726 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8727
8728 /*
8729 * (assumption: No Attention from MCP at this stage)
8730 * PMF probably in the middle of TXdisable/enable transaction
8731 */
8732 rc = bnx2x_func_wait_started(bp);
8733 if (rc) {
8734 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8735 #ifdef BNX2X_STOP_ON_ERROR
8736 return;
8737 #endif
8738 }
8739
8740 /* Close multi and leading connections
8741 * Completions for ramrods are collected in a synchronous way
8742 */
8743 for_each_eth_queue(bp, i)
8744 if (bnx2x_stop_queue(bp, i))
8745 #ifdef BNX2X_STOP_ON_ERROR
8746 return;
8747 #else
8748 goto unload_error;
8749 #endif
8750
8751 if (CNIC_LOADED(bp)) {
8752 for_each_cnic_queue(bp, i)
8753 if (bnx2x_stop_queue(bp, i))
8754 #ifdef BNX2X_STOP_ON_ERROR
8755 return;
8756 #else
8757 goto unload_error;
8758 #endif
8759 }
8760
8761 /* If SP settings didn't get completed so far - something
8762 * very wrong has happen.
8763 */
8764 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8765 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8766
8767 #ifndef BNX2X_STOP_ON_ERROR
8768 unload_error:
8769 #endif
8770 rc = bnx2x_func_stop(bp);
8771 if (rc) {
8772 BNX2X_ERR("Function stop failed!\n");
8773 #ifdef BNX2X_STOP_ON_ERROR
8774 return;
8775 #endif
8776 }
8777
8778 /* Disable HW interrupts, NAPI */
8779 bnx2x_netif_stop(bp, 1);
8780 /* Delete all NAPI objects */
8781 bnx2x_del_all_napi(bp);
8782 if (CNIC_LOADED(bp))
8783 bnx2x_del_all_napi_cnic(bp);
8784
8785 /* Release IRQs */
8786 bnx2x_free_irq(bp);
8787
8788 /* Reset the chip */
8789 rc = bnx2x_reset_hw(bp, reset_code);
8790 if (rc)
8791 BNX2X_ERR("HW_RESET failed\n");
8792
8793
8794 /* Report UNLOAD_DONE to MCP */
8795 bnx2x_send_unload_done(bp, keep_link);
8796 }
8797
8798 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8799 {
8800 u32 val;
8801
8802 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8803
8804 if (CHIP_IS_E1(bp)) {
8805 int port = BP_PORT(bp);
8806 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8807 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8808
8809 val = REG_RD(bp, addr);
8810 val &= ~(0x300);
8811 REG_WR(bp, addr, val);
8812 } else {
8813 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8814 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8815 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8816 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8817 }
8818 }
8819
8820 /* Close gates #2, #3 and #4: */
8821 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8822 {
8823 u32 val;
8824
8825 /* Gates #2 and #4a are closed/opened for "not E1" only */
8826 if (!CHIP_IS_E1(bp)) {
8827 /* #4 */
8828 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8829 /* #2 */
8830 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8831 }
8832
8833 /* #3 */
8834 if (CHIP_IS_E1x(bp)) {
8835 /* Prevent interrupts from HC on both ports */
8836 val = REG_RD(bp, HC_REG_CONFIG_1);
8837 REG_WR(bp, HC_REG_CONFIG_1,
8838 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8839 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8840
8841 val = REG_RD(bp, HC_REG_CONFIG_0);
8842 REG_WR(bp, HC_REG_CONFIG_0,
8843 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8844 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8845 } else {
8846 /* Prevent incoming interrupts in IGU */
8847 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8848
8849 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8850 (!close) ?
8851 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8852 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8853 }
8854
8855 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8856 close ? "closing" : "opening");
8857 mmiowb();
8858 }
8859
8860 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8861
8862 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8863 {
8864 /* Do some magic... */
8865 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8866 *magic_val = val & SHARED_MF_CLP_MAGIC;
8867 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8868 }
8869
8870 /**
8871 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8872 *
8873 * @bp: driver handle
8874 * @magic_val: old value of the `magic' bit.
8875 */
8876 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8877 {
8878 /* Restore the `magic' bit value... */
8879 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8880 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8881 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8882 }
8883
8884 /**
8885 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8886 *
8887 * @bp: driver handle
8888 * @magic_val: old value of 'magic' bit.
8889 *
8890 * Takes care of CLP configurations.
8891 */
8892 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8893 {
8894 u32 shmem;
8895 u32 validity_offset;
8896
8897 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8898
8899 /* Set `magic' bit in order to save MF config */
8900 if (!CHIP_IS_E1(bp))
8901 bnx2x_clp_reset_prep(bp, magic_val);
8902
8903 /* Get shmem offset */
8904 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8905 validity_offset =
8906 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8907
8908 /* Clear validity map flags */
8909 if (shmem > 0)
8910 REG_WR(bp, shmem + validity_offset, 0);
8911 }
8912
8913 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8914 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8915
8916 /**
8917 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8918 *
8919 * @bp: driver handle
8920 */
8921 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8922 {
8923 /* special handling for emulation and FPGA,
8924 wait 10 times longer */
8925 if (CHIP_REV_IS_SLOW(bp))
8926 msleep(MCP_ONE_TIMEOUT*10);
8927 else
8928 msleep(MCP_ONE_TIMEOUT);
8929 }
8930
8931 /*
8932 * initializes bp->common.shmem_base and waits for validity signature to appear
8933 */
8934 static int bnx2x_init_shmem(struct bnx2x *bp)
8935 {
8936 int cnt = 0;
8937 u32 val = 0;
8938
8939 do {
8940 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8941 if (bp->common.shmem_base) {
8942 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8943 if (val & SHR_MEM_VALIDITY_MB)
8944 return 0;
8945 }
8946
8947 bnx2x_mcp_wait_one(bp);
8948
8949 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8950
8951 BNX2X_ERR("BAD MCP validity signature\n");
8952
8953 return -ENODEV;
8954 }
8955
8956 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8957 {
8958 int rc = bnx2x_init_shmem(bp);
8959
8960 /* Restore the `magic' bit value */
8961 if (!CHIP_IS_E1(bp))
8962 bnx2x_clp_reset_done(bp, magic_val);
8963
8964 return rc;
8965 }
8966
8967 static void bnx2x_pxp_prep(struct bnx2x *bp)
8968 {
8969 if (!CHIP_IS_E1(bp)) {
8970 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8971 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8972 mmiowb();
8973 }
8974 }
8975
8976 /*
8977 * Reset the whole chip except for:
8978 * - PCIE core
8979 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8980 * one reset bit)
8981 * - IGU
8982 * - MISC (including AEU)
8983 * - GRC
8984 * - RBCN, RBCP
8985 */
8986 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8987 {
8988 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8989 u32 global_bits2, stay_reset2;
8990
8991 /*
8992 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8993 * (per chip) blocks.
8994 */
8995 global_bits2 =
8996 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8997 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8998
8999 /* Don't reset the following blocks.
9000 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9001 * reset, as in 4 port device they might still be owned
9002 * by the MCP (there is only one leader per path).
9003 */
9004 not_reset_mask1 =
9005 MISC_REGISTERS_RESET_REG_1_RST_HC |
9006 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9007 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9008
9009 not_reset_mask2 =
9010 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9011 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9012 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9013 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9014 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9015 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9016 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9017 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9018 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9019 MISC_REGISTERS_RESET_REG_2_PGLC |
9020 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9021 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9022 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9023 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9024 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9025 MISC_REGISTERS_RESET_REG_2_UMAC1;
9026
9027 /*
9028 * Keep the following blocks in reset:
9029 * - all xxMACs are handled by the bnx2x_link code.
9030 */
9031 stay_reset2 =
9032 MISC_REGISTERS_RESET_REG_2_XMAC |
9033 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9034
9035 /* Full reset masks according to the chip */
9036 reset_mask1 = 0xffffffff;
9037
9038 if (CHIP_IS_E1(bp))
9039 reset_mask2 = 0xffff;
9040 else if (CHIP_IS_E1H(bp))
9041 reset_mask2 = 0x1ffff;
9042 else if (CHIP_IS_E2(bp))
9043 reset_mask2 = 0xfffff;
9044 else /* CHIP_IS_E3 */
9045 reset_mask2 = 0x3ffffff;
9046
9047 /* Don't reset global blocks unless we need to */
9048 if (!global)
9049 reset_mask2 &= ~global_bits2;
9050
9051 /*
9052 * In case of attention in the QM, we need to reset PXP
9053 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9054 * because otherwise QM reset would release 'close the gates' shortly
9055 * before resetting the PXP, then the PSWRQ would send a write
9056 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9057 * read the payload data from PSWWR, but PSWWR would not
9058 * respond. The write queue in PGLUE would stuck, dmae commands
9059 * would not return. Therefore it's important to reset the second
9060 * reset register (containing the
9061 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9062 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9063 * bit).
9064 */
9065 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9066 reset_mask2 & (~not_reset_mask2));
9067
9068 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9069 reset_mask1 & (~not_reset_mask1));
9070
9071 barrier();
9072 mmiowb();
9073
9074 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9075 reset_mask2 & (~stay_reset2));
9076
9077 barrier();
9078 mmiowb();
9079
9080 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9081 mmiowb();
9082 }
9083
9084 /**
9085 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9086 * It should get cleared in no more than 1s.
9087 *
9088 * @bp: driver handle
9089 *
9090 * It should get cleared in no more than 1s. Returns 0 if
9091 * pending writes bit gets cleared.
9092 */
9093 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9094 {
9095 u32 cnt = 1000;
9096 u32 pend_bits = 0;
9097
9098 do {
9099 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9100
9101 if (pend_bits == 0)
9102 break;
9103
9104 usleep_range(1000, 2000);
9105 } while (cnt-- > 0);
9106
9107 if (cnt <= 0) {
9108 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9109 pend_bits);
9110 return -EBUSY;
9111 }
9112
9113 return 0;
9114 }
9115
9116 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9117 {
9118 int cnt = 1000;
9119 u32 val = 0;
9120 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9121 u32 tags_63_32 = 0;
9122
9123 /* Empty the Tetris buffer, wait for 1s */
9124 do {
9125 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9126 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9127 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9128 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9129 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9130 if (CHIP_IS_E3(bp))
9131 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9132
9133 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9134 ((port_is_idle_0 & 0x1) == 0x1) &&
9135 ((port_is_idle_1 & 0x1) == 0x1) &&
9136 (pgl_exp_rom2 == 0xffffffff) &&
9137 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9138 break;
9139 usleep_range(1000, 2000);
9140 } while (cnt-- > 0);
9141
9142 if (cnt <= 0) {
9143 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9144 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9145 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9146 pgl_exp_rom2);
9147 return -EAGAIN;
9148 }
9149
9150 barrier();
9151
9152 /* Close gates #2, #3 and #4 */
9153 bnx2x_set_234_gates(bp, true);
9154
9155 /* Poll for IGU VQs for 57712 and newer chips */
9156 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9157 return -EAGAIN;
9158
9159
9160 /* TBD: Indicate that "process kill" is in progress to MCP */
9161
9162 /* Clear "unprepared" bit */
9163 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9164 barrier();
9165
9166 /* Make sure all is written to the chip before the reset */
9167 mmiowb();
9168
9169 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9170 * PSWHST, GRC and PSWRD Tetris buffer.
9171 */
9172 usleep_range(1000, 2000);
9173
9174 /* Prepare to chip reset: */
9175 /* MCP */
9176 if (global)
9177 bnx2x_reset_mcp_prep(bp, &val);
9178
9179 /* PXP */
9180 bnx2x_pxp_prep(bp);
9181 barrier();
9182
9183 /* reset the chip */
9184 bnx2x_process_kill_chip_reset(bp, global);
9185 barrier();
9186
9187 /* Recover after reset: */
9188 /* MCP */
9189 if (global && bnx2x_reset_mcp_comp(bp, val))
9190 return -EAGAIN;
9191
9192 /* TBD: Add resetting the NO_MCP mode DB here */
9193
9194 /* Open the gates #2, #3 and #4 */
9195 bnx2x_set_234_gates(bp, false);
9196
9197 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9198 * reset state, re-enable attentions. */
9199
9200 return 0;
9201 }
9202
9203 static int bnx2x_leader_reset(struct bnx2x *bp)
9204 {
9205 int rc = 0;
9206 bool global = bnx2x_reset_is_global(bp);
9207 u32 load_code;
9208
9209 /* if not going to reset MCP - load "fake" driver to reset HW while
9210 * driver is owner of the HW
9211 */
9212 if (!global && !BP_NOMCP(bp)) {
9213 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9214 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9215 if (!load_code) {
9216 BNX2X_ERR("MCP response failure, aborting\n");
9217 rc = -EAGAIN;
9218 goto exit_leader_reset;
9219 }
9220 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9221 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9222 BNX2X_ERR("MCP unexpected resp, aborting\n");
9223 rc = -EAGAIN;
9224 goto exit_leader_reset2;
9225 }
9226 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9227 if (!load_code) {
9228 BNX2X_ERR("MCP response failure, aborting\n");
9229 rc = -EAGAIN;
9230 goto exit_leader_reset2;
9231 }
9232 }
9233
9234 /* Try to recover after the failure */
9235 if (bnx2x_process_kill(bp, global)) {
9236 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9237 BP_PATH(bp));
9238 rc = -EAGAIN;
9239 goto exit_leader_reset2;
9240 }
9241
9242 /*
9243 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9244 * state.
9245 */
9246 bnx2x_set_reset_done(bp);
9247 if (global)
9248 bnx2x_clear_reset_global(bp);
9249
9250 exit_leader_reset2:
9251 /* unload "fake driver" if it was loaded */
9252 if (!global && !BP_NOMCP(bp)) {
9253 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9254 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9255 }
9256 exit_leader_reset:
9257 bp->is_leader = 0;
9258 bnx2x_release_leader_lock(bp);
9259 smp_mb();
9260 return rc;
9261 }
9262
9263 static void bnx2x_recovery_failed(struct bnx2x *bp)
9264 {
9265 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9266
9267 /* Disconnect this device */
9268 netif_device_detach(bp->dev);
9269
9270 /*
9271 * Block ifup for all function on this engine until "process kill"
9272 * or power cycle.
9273 */
9274 bnx2x_set_reset_in_progress(bp);
9275
9276 /* Shut down the power */
9277 bnx2x_set_power_state(bp, PCI_D3hot);
9278
9279 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9280
9281 smp_mb();
9282 }
9283
9284 /*
9285 * Assumption: runs under rtnl lock. This together with the fact
9286 * that it's called only from bnx2x_sp_rtnl() ensure that it
9287 * will never be called when netif_running(bp->dev) is false.
9288 */
9289 static void bnx2x_parity_recover(struct bnx2x *bp)
9290 {
9291 bool global = false;
9292 u32 error_recovered, error_unrecovered;
9293 bool is_parity;
9294
9295 DP(NETIF_MSG_HW, "Handling parity\n");
9296 while (1) {
9297 switch (bp->recovery_state) {
9298 case BNX2X_RECOVERY_INIT:
9299 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9300 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9301 WARN_ON(!is_parity);
9302
9303 /* Try to get a LEADER_LOCK HW lock */
9304 if (bnx2x_trylock_leader_lock(bp)) {
9305 bnx2x_set_reset_in_progress(bp);
9306 /*
9307 * Check if there is a global attention and if
9308 * there was a global attention, set the global
9309 * reset bit.
9310 */
9311
9312 if (global)
9313 bnx2x_set_reset_global(bp);
9314
9315 bp->is_leader = 1;
9316 }
9317
9318 /* Stop the driver */
9319 /* If interface has been removed - break */
9320 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9321 return;
9322
9323 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9324
9325 /* Ensure "is_leader", MCP command sequence and
9326 * "recovery_state" update values are seen on other
9327 * CPUs.
9328 */
9329 smp_mb();
9330 break;
9331
9332 case BNX2X_RECOVERY_WAIT:
9333 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9334 if (bp->is_leader) {
9335 int other_engine = BP_PATH(bp) ? 0 : 1;
9336 bool other_load_status =
9337 bnx2x_get_load_status(bp, other_engine);
9338 bool load_status =
9339 bnx2x_get_load_status(bp, BP_PATH(bp));
9340 global = bnx2x_reset_is_global(bp);
9341
9342 /*
9343 * In case of a parity in a global block, let
9344 * the first leader that performs a
9345 * leader_reset() reset the global blocks in
9346 * order to clear global attentions. Otherwise
9347 * the the gates will remain closed for that
9348 * engine.
9349 */
9350 if (load_status ||
9351 (global && other_load_status)) {
9352 /* Wait until all other functions get
9353 * down.
9354 */
9355 schedule_delayed_work(&bp->sp_rtnl_task,
9356 HZ/10);
9357 return;
9358 } else {
9359 /* If all other functions got down -
9360 * try to bring the chip back to
9361 * normal. In any case it's an exit
9362 * point for a leader.
9363 */
9364 if (bnx2x_leader_reset(bp)) {
9365 bnx2x_recovery_failed(bp);
9366 return;
9367 }
9368
9369 /* If we are here, means that the
9370 * leader has succeeded and doesn't
9371 * want to be a leader any more. Try
9372 * to continue as a none-leader.
9373 */
9374 break;
9375 }
9376 } else { /* non-leader */
9377 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9378 /* Try to get a LEADER_LOCK HW lock as
9379 * long as a former leader may have
9380 * been unloaded by the user or
9381 * released a leadership by another
9382 * reason.
9383 */
9384 if (bnx2x_trylock_leader_lock(bp)) {
9385 /* I'm a leader now! Restart a
9386 * switch case.
9387 */
9388 bp->is_leader = 1;
9389 break;
9390 }
9391
9392 schedule_delayed_work(&bp->sp_rtnl_task,
9393 HZ/10);
9394 return;
9395
9396 } else {
9397 /*
9398 * If there was a global attention, wait
9399 * for it to be cleared.
9400 */
9401 if (bnx2x_reset_is_global(bp)) {
9402 schedule_delayed_work(
9403 &bp->sp_rtnl_task,
9404 HZ/10);
9405 return;
9406 }
9407
9408 error_recovered =
9409 bp->eth_stats.recoverable_error;
9410 error_unrecovered =
9411 bp->eth_stats.unrecoverable_error;
9412 bp->recovery_state =
9413 BNX2X_RECOVERY_NIC_LOADING;
9414 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9415 error_unrecovered++;
9416 netdev_err(bp->dev,
9417 "Recovery failed. Power cycle needed\n");
9418 /* Disconnect this device */
9419 netif_device_detach(bp->dev);
9420 /* Shut down the power */
9421 bnx2x_set_power_state(
9422 bp, PCI_D3hot);
9423 smp_mb();
9424 } else {
9425 bp->recovery_state =
9426 BNX2X_RECOVERY_DONE;
9427 error_recovered++;
9428 smp_mb();
9429 }
9430 bp->eth_stats.recoverable_error =
9431 error_recovered;
9432 bp->eth_stats.unrecoverable_error =
9433 error_unrecovered;
9434
9435 return;
9436 }
9437 }
9438 default:
9439 return;
9440 }
9441 }
9442 }
9443
9444 static int bnx2x_close(struct net_device *dev);
9445
9446 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9447 * scheduled on a general queue in order to prevent a dead lock.
9448 */
9449 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9450 {
9451 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9452
9453 rtnl_lock();
9454
9455 if (!netif_running(bp->dev)) {
9456 rtnl_unlock();
9457 return;
9458 }
9459
9460 /* if stop on error is defined no recovery flows should be executed */
9461 #ifdef BNX2X_STOP_ON_ERROR
9462 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9463 "you will need to reboot when done\n");
9464 goto sp_rtnl_not_reset;
9465 #endif
9466
9467 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9468 /*
9469 * Clear all pending SP commands as we are going to reset the
9470 * function anyway.
9471 */
9472 bp->sp_rtnl_state = 0;
9473 smp_mb();
9474
9475 bnx2x_parity_recover(bp);
9476
9477 rtnl_unlock();
9478 return;
9479 }
9480
9481 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9482 /*
9483 * Clear all pending SP commands as we are going to reset the
9484 * function anyway.
9485 */
9486 bp->sp_rtnl_state = 0;
9487 smp_mb();
9488
9489 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9490 bnx2x_nic_load(bp, LOAD_NORMAL);
9491
9492 rtnl_unlock();
9493 return;
9494 }
9495 #ifdef BNX2X_STOP_ON_ERROR
9496 sp_rtnl_not_reset:
9497 #endif
9498 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9499 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9500 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9501 bnx2x_after_function_update(bp);
9502 /*
9503 * in case of fan failure we need to reset id if the "stop on error"
9504 * debug flag is set, since we trying to prevent permanent overheating
9505 * damage
9506 */
9507 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9508 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9509 netif_device_detach(bp->dev);
9510 bnx2x_close(bp->dev);
9511 rtnl_unlock();
9512 return;
9513 }
9514
9515 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9516 DP(BNX2X_MSG_SP,
9517 "sending set mcast vf pf channel message from rtnl sp-task\n");
9518 bnx2x_vfpf_set_mcast(bp->dev);
9519 }
9520
9521 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9522 &bp->sp_rtnl_state)) {
9523 DP(BNX2X_MSG_SP,
9524 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9525 bnx2x_vfpf_storm_rx_mode(bp);
9526 }
9527
9528 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9529 * can be called from other contexts as well)
9530 */
9531 rtnl_unlock();
9532
9533 /* enable SR-IOV if applicable */
9534 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9535 &bp->sp_rtnl_state))
9536 bnx2x_enable_sriov(bp);
9537 }
9538
9539 static void bnx2x_period_task(struct work_struct *work)
9540 {
9541 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9542
9543 if (!netif_running(bp->dev))
9544 goto period_task_exit;
9545
9546 if (CHIP_REV_IS_SLOW(bp)) {
9547 BNX2X_ERR("period task called on emulation, ignoring\n");
9548 goto period_task_exit;
9549 }
9550
9551 bnx2x_acquire_phy_lock(bp);
9552 /*
9553 * The barrier is needed to ensure the ordering between the writing to
9554 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9555 * the reading here.
9556 */
9557 smp_mb();
9558 if (bp->port.pmf) {
9559 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9560
9561 /* Re-queue task in 1 sec */
9562 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9563 }
9564
9565 bnx2x_release_phy_lock(bp);
9566 period_task_exit:
9567 return;
9568 }
9569
9570 /*
9571 * Init service functions
9572 */
9573
9574 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9575 {
9576 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9577 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9578 return base + (BP_ABS_FUNC(bp)) * stride;
9579 }
9580
9581 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9582 struct bnx2x_mac_vals *vals)
9583 {
9584 u32 val, base_addr, offset, mask, reset_reg;
9585 bool mac_stopped = false;
9586 u8 port = BP_PORT(bp);
9587
9588 /* reset addresses as they also mark which values were changed */
9589 vals->bmac_addr = 0;
9590 vals->umac_addr = 0;
9591 vals->xmac_addr = 0;
9592 vals->emac_addr = 0;
9593
9594 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9595
9596 if (!CHIP_IS_E3(bp)) {
9597 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9598 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9599 if ((mask & reset_reg) && val) {
9600 u32 wb_data[2];
9601 BNX2X_DEV_INFO("Disable bmac Rx\n");
9602 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9603 : NIG_REG_INGRESS_BMAC0_MEM;
9604 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9605 : BIGMAC_REGISTER_BMAC_CONTROL;
9606
9607 /*
9608 * use rd/wr since we cannot use dmae. This is safe
9609 * since MCP won't access the bus due to the request
9610 * to unload, and no function on the path can be
9611 * loaded at this time.
9612 */
9613 wb_data[0] = REG_RD(bp, base_addr + offset);
9614 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9615 vals->bmac_addr = base_addr + offset;
9616 vals->bmac_val[0] = wb_data[0];
9617 vals->bmac_val[1] = wb_data[1];
9618 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9619 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9620 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9621
9622 }
9623 BNX2X_DEV_INFO("Disable emac Rx\n");
9624 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9625 vals->emac_val = REG_RD(bp, vals->emac_addr);
9626 REG_WR(bp, vals->emac_addr, 0);
9627 mac_stopped = true;
9628 } else {
9629 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9630 BNX2X_DEV_INFO("Disable xmac Rx\n");
9631 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9632 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9633 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9634 val & ~(1 << 1));
9635 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9636 val | (1 << 1));
9637 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9638 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9639 REG_WR(bp, vals->xmac_addr, 0);
9640 mac_stopped = true;
9641 }
9642 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9643 if (mask & reset_reg) {
9644 BNX2X_DEV_INFO("Disable umac Rx\n");
9645 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9646 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9647 vals->umac_val = REG_RD(bp, vals->umac_addr);
9648 REG_WR(bp, vals->umac_addr, 0);
9649 mac_stopped = true;
9650 }
9651 }
9652
9653 if (mac_stopped)
9654 msleep(20);
9655
9656 }
9657
9658 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9659 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9660 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9661 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9662
9663 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9664 {
9665 u16 rcq, bd;
9666 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9667
9668 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9669 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9670
9671 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9672 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9673
9674 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9675 port, bd, rcq);
9676 }
9677
9678 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9679 {
9680 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9681 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9682 if (!rc) {
9683 BNX2X_ERR("MCP response failure, aborting\n");
9684 return -EBUSY;
9685 }
9686
9687 return 0;
9688 }
9689
9690 static struct bnx2x_prev_path_list *
9691 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9692 {
9693 struct bnx2x_prev_path_list *tmp_list;
9694
9695 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9696 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9697 bp->pdev->bus->number == tmp_list->bus &&
9698 BP_PATH(bp) == tmp_list->path)
9699 return tmp_list;
9700
9701 return NULL;
9702 }
9703
9704 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9705 {
9706 struct bnx2x_prev_path_list *tmp_list;
9707 int rc = false;
9708
9709 if (down_trylock(&bnx2x_prev_sem))
9710 return false;
9711
9712 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9713 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9714 bp->pdev->bus->number == tmp_list->bus &&
9715 BP_PATH(bp) == tmp_list->path) {
9716 rc = true;
9717 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9718 BP_PATH(bp));
9719 break;
9720 }
9721 }
9722
9723 up(&bnx2x_prev_sem);
9724
9725 return rc;
9726 }
9727
9728 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9729 {
9730 struct bnx2x_prev_path_list *tmp_list;
9731 int rc;
9732
9733 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9734 if (!tmp_list) {
9735 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9736 return -ENOMEM;
9737 }
9738
9739 tmp_list->bus = bp->pdev->bus->number;
9740 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9741 tmp_list->path = BP_PATH(bp);
9742 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9743
9744 rc = down_interruptible(&bnx2x_prev_sem);
9745 if (rc) {
9746 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9747 kfree(tmp_list);
9748 } else {
9749 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9750 BP_PATH(bp));
9751 list_add(&tmp_list->list, &bnx2x_prev_list);
9752 up(&bnx2x_prev_sem);
9753 }
9754
9755 return rc;
9756 }
9757
9758 static int bnx2x_do_flr(struct bnx2x *bp)
9759 {
9760 int i;
9761 u16 status;
9762 struct pci_dev *dev = bp->pdev;
9763
9764
9765 if (CHIP_IS_E1x(bp)) {
9766 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9767 return -EINVAL;
9768 }
9769
9770 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9771 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9772 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9773 bp->common.bc_ver);
9774 return -EINVAL;
9775 }
9776
9777 /* Wait for Transaction Pending bit clean */
9778 for (i = 0; i < 4; i++) {
9779 if (i)
9780 msleep((1 << (i - 1)) * 100);
9781
9782 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9783 if (!(status & PCI_EXP_DEVSTA_TRPND))
9784 goto clear;
9785 }
9786
9787 dev_err(&dev->dev,
9788 "transaction is not cleared; proceeding with reset anyway\n");
9789
9790 clear:
9791
9792 BNX2X_DEV_INFO("Initiating FLR\n");
9793 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9794
9795 return 0;
9796 }
9797
9798 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9799 {
9800 int rc;
9801
9802 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9803
9804 /* Test if previous unload process was already finished for this path */
9805 if (bnx2x_prev_is_path_marked(bp))
9806 return bnx2x_prev_mcp_done(bp);
9807
9808 BNX2X_DEV_INFO("Path is unmarked\n");
9809
9810 /* If function has FLR capabilities, and existing FW version matches
9811 * the one required, then FLR will be sufficient to clean any residue
9812 * left by previous driver
9813 */
9814 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9815
9816 if (!rc) {
9817 /* fw version is good */
9818 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9819 rc = bnx2x_do_flr(bp);
9820 }
9821
9822 if (!rc) {
9823 /* FLR was performed */
9824 BNX2X_DEV_INFO("FLR successful\n");
9825 return 0;
9826 }
9827
9828 BNX2X_DEV_INFO("Could not FLR\n");
9829
9830 /* Close the MCP request, return failure*/
9831 rc = bnx2x_prev_mcp_done(bp);
9832 if (!rc)
9833 rc = BNX2X_PREV_WAIT_NEEDED;
9834
9835 return rc;
9836 }
9837
9838 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9839 {
9840 u32 reset_reg, tmp_reg = 0, rc;
9841 bool prev_undi = false;
9842 struct bnx2x_mac_vals mac_vals;
9843
9844 /* It is possible a previous function received 'common' answer,
9845 * but hasn't loaded yet, therefore creating a scenario of
9846 * multiple functions receiving 'common' on the same path.
9847 */
9848 BNX2X_DEV_INFO("Common unload Flow\n");
9849
9850 memset(&mac_vals, 0, sizeof(mac_vals));
9851
9852 if (bnx2x_prev_is_path_marked(bp))
9853 return bnx2x_prev_mcp_done(bp);
9854
9855 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9856
9857 /* Reset should be performed after BRB is emptied */
9858 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9859 u32 timer_count = 1000;
9860
9861 /* Close the MAC Rx to prevent BRB from filling up */
9862 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9863
9864 /* close LLH filters towards the BRB */
9865 bnx2x_set_rx_filter(&bp->link_params, 0);
9866
9867 /* Check if the UNDI driver was previously loaded
9868 * UNDI driver initializes CID offset for normal bell to 0x7
9869 */
9870 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9871 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9872 if (tmp_reg == 0x7) {
9873 BNX2X_DEV_INFO("UNDI previously loaded\n");
9874 prev_undi = true;
9875 /* clear the UNDI indication */
9876 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9877 /* clear possible idle check errors */
9878 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9879 }
9880 }
9881 /* wait until BRB is empty */
9882 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9883 while (timer_count) {
9884 u32 prev_brb = tmp_reg;
9885
9886 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9887 if (!tmp_reg)
9888 break;
9889
9890 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9891
9892 /* reset timer as long as BRB actually gets emptied */
9893 if (prev_brb > tmp_reg)
9894 timer_count = 1000;
9895 else
9896 timer_count--;
9897
9898 /* If UNDI resides in memory, manually increment it */
9899 if (prev_undi)
9900 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9901
9902 udelay(10);
9903 }
9904
9905 if (!timer_count)
9906 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9907
9908 }
9909
9910 /* No packets are in the pipeline, path is ready for reset */
9911 bnx2x_reset_common(bp);
9912
9913 if (mac_vals.xmac_addr)
9914 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9915 if (mac_vals.umac_addr)
9916 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9917 if (mac_vals.emac_addr)
9918 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9919 if (mac_vals.bmac_addr) {
9920 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9921 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9922 }
9923
9924 rc = bnx2x_prev_mark_path(bp, prev_undi);
9925 if (rc) {
9926 bnx2x_prev_mcp_done(bp);
9927 return rc;
9928 }
9929
9930 return bnx2x_prev_mcp_done(bp);
9931 }
9932
9933 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9934 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9935 * the addresses of the transaction, resulting in was-error bit set in the pci
9936 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9937 * to clear the interrupt which detected this from the pglueb and the was done
9938 * bit
9939 */
9940 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9941 {
9942 if (!CHIP_IS_E1x(bp)) {
9943 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9944 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9945 DP(BNX2X_MSG_SP,
9946 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
9947 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
9948 1 << BP_FUNC(bp));
9949 }
9950 }
9951 }
9952
9953 static int bnx2x_prev_unload(struct bnx2x *bp)
9954 {
9955 int time_counter = 10;
9956 u32 rc, fw, hw_lock_reg, hw_lock_val;
9957 struct bnx2x_prev_path_list *prev_list;
9958 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9959
9960 /* clear hw from errors which may have resulted from an interrupted
9961 * dmae transaction.
9962 */
9963 bnx2x_prev_interrupted_dmae(bp);
9964
9965 /* Release previously held locks */
9966 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9967 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9968 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9969
9970 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9971 if (hw_lock_val) {
9972 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9973 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9974 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9975 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9976 }
9977
9978 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9979 REG_WR(bp, hw_lock_reg, 0xffffffff);
9980 } else
9981 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9982
9983 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9984 BNX2X_DEV_INFO("Release previously held alr\n");
9985 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9986 }
9987
9988 do {
9989 /* Lock MCP using an unload request */
9990 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9991 if (!fw) {
9992 BNX2X_ERR("MCP response failure, aborting\n");
9993 rc = -EBUSY;
9994 break;
9995 }
9996
9997 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9998 rc = bnx2x_prev_unload_common(bp);
9999 break;
10000 }
10001
10002 /* non-common reply from MCP night require looping */
10003 rc = bnx2x_prev_unload_uncommon(bp);
10004 if (rc != BNX2X_PREV_WAIT_NEEDED)
10005 break;
10006
10007 msleep(20);
10008 } while (--time_counter);
10009
10010 if (!time_counter || rc) {
10011 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10012 rc = -EBUSY;
10013 }
10014
10015 /* Mark function if its port was used to boot from SAN */
10016 prev_list = bnx2x_prev_path_get_entry(bp);
10017 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10018 bp->link_params.feature_config_flags |=
10019 FEATURE_CONFIG_BOOT_FROM_SAN;
10020
10021 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10022
10023 return rc;
10024 }
10025
10026 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10027 {
10028 u32 val, val2, val3, val4, id, boot_mode;
10029 u16 pmc;
10030
10031 /* Get the chip revision id and number. */
10032 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10033 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10034 id = ((val & 0xffff) << 16);
10035 val = REG_RD(bp, MISC_REG_CHIP_REV);
10036 id |= ((val & 0xf) << 12);
10037 val = REG_RD(bp, MISC_REG_CHIP_METAL);
10038 id |= ((val & 0xff) << 4);
10039 val = REG_RD(bp, MISC_REG_BOND_ID);
10040 id |= (val & 0xf);
10041 bp->common.chip_id = id;
10042
10043 /* force 57811 according to MISC register */
10044 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10045 if (CHIP_IS_57810(bp))
10046 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10047 (bp->common.chip_id & 0x0000FFFF);
10048 else if (CHIP_IS_57810_MF(bp))
10049 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10050 (bp->common.chip_id & 0x0000FFFF);
10051 bp->common.chip_id |= 0x1;
10052 }
10053
10054 /* Set doorbell size */
10055 bp->db_size = (1 << BNX2X_DB_SHIFT);
10056
10057 if (!CHIP_IS_E1x(bp)) {
10058 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10059 if ((val & 1) == 0)
10060 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10061 else
10062 val = (val >> 1) & 1;
10063 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10064 "2_PORT_MODE");
10065 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10066 CHIP_2_PORT_MODE;
10067
10068 if (CHIP_MODE_IS_4_PORT(bp))
10069 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10070 else
10071 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10072 } else {
10073 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10074 bp->pfid = bp->pf_num; /* 0..7 */
10075 }
10076
10077 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10078
10079 bp->link_params.chip_id = bp->common.chip_id;
10080 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10081
10082 val = (REG_RD(bp, 0x2874) & 0x55);
10083 if ((bp->common.chip_id & 0x1) ||
10084 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10085 bp->flags |= ONE_PORT_FLAG;
10086 BNX2X_DEV_INFO("single port device\n");
10087 }
10088
10089 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10090 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10091 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10092 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10093 bp->common.flash_size, bp->common.flash_size);
10094
10095 bnx2x_init_shmem(bp);
10096
10097
10098
10099 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10100 MISC_REG_GENERIC_CR_1 :
10101 MISC_REG_GENERIC_CR_0));
10102
10103 bp->link_params.shmem_base = bp->common.shmem_base;
10104 bp->link_params.shmem2_base = bp->common.shmem2_base;
10105 if (SHMEM2_RD(bp, size) >
10106 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10107 bp->link_params.lfa_base =
10108 REG_RD(bp, bp->common.shmem2_base +
10109 (u32)offsetof(struct shmem2_region,
10110 lfa_host_addr[BP_PORT(bp)]));
10111 else
10112 bp->link_params.lfa_base = 0;
10113 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10114 bp->common.shmem_base, bp->common.shmem2_base);
10115
10116 if (!bp->common.shmem_base) {
10117 BNX2X_DEV_INFO("MCP not active\n");
10118 bp->flags |= NO_MCP_FLAG;
10119 return;
10120 }
10121
10122 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10123 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10124
10125 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10126 SHARED_HW_CFG_LED_MODE_MASK) >>
10127 SHARED_HW_CFG_LED_MODE_SHIFT);
10128
10129 bp->link_params.feature_config_flags = 0;
10130 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10131 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10132 bp->link_params.feature_config_flags |=
10133 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10134 else
10135 bp->link_params.feature_config_flags &=
10136 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10137
10138 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10139 bp->common.bc_ver = val;
10140 BNX2X_DEV_INFO("bc_ver %X\n", val);
10141 if (val < BNX2X_BC_VER) {
10142 /* for now only warn
10143 * later we might need to enforce this */
10144 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10145 BNX2X_BC_VER, val);
10146 }
10147 bp->link_params.feature_config_flags |=
10148 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10149 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10150
10151 bp->link_params.feature_config_flags |=
10152 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10153 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10154 bp->link_params.feature_config_flags |=
10155 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10156 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10157 bp->link_params.feature_config_flags |=
10158 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10159 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10160
10161 bp->link_params.feature_config_flags |=
10162 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10163 FEATURE_CONFIG_MT_SUPPORT : 0;
10164
10165 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10166 BC_SUPPORTS_PFC_STATS : 0;
10167
10168 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10169 BC_SUPPORTS_FCOE_FEATURES : 0;
10170
10171 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10172 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10173 boot_mode = SHMEM_RD(bp,
10174 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10175 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10176 switch (boot_mode) {
10177 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10178 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10179 break;
10180 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10181 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10182 break;
10183 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10184 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10185 break;
10186 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10187 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10188 break;
10189 }
10190
10191 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10192 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10193
10194 BNX2X_DEV_INFO("%sWoL capable\n",
10195 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10196
10197 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10198 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10199 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10200 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10201
10202 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10203 val, val2, val3, val4);
10204 }
10205
10206 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10207 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10208
10209 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10210 {
10211 int pfid = BP_FUNC(bp);
10212 int igu_sb_id;
10213 u32 val;
10214 u8 fid, igu_sb_cnt = 0;
10215
10216 bp->igu_base_sb = 0xff;
10217 if (CHIP_INT_MODE_IS_BC(bp)) {
10218 int vn = BP_VN(bp);
10219 igu_sb_cnt = bp->igu_sb_cnt;
10220 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10221 FP_SB_MAX_E1x;
10222
10223 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10224 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10225
10226 return 0;
10227 }
10228
10229 /* IGU in normal mode - read CAM */
10230 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10231 igu_sb_id++) {
10232 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10233 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10234 continue;
10235 fid = IGU_FID(val);
10236 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10237 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10238 continue;
10239 if (IGU_VEC(val) == 0)
10240 /* default status block */
10241 bp->igu_dsb_id = igu_sb_id;
10242 else {
10243 if (bp->igu_base_sb == 0xff)
10244 bp->igu_base_sb = igu_sb_id;
10245 igu_sb_cnt++;
10246 }
10247 }
10248 }
10249
10250 #ifdef CONFIG_PCI_MSI
10251 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10252 * optional that number of CAM entries will not be equal to the value
10253 * advertised in PCI.
10254 * Driver should use the minimal value of both as the actual status
10255 * block count
10256 */
10257 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10258 #endif
10259
10260 if (igu_sb_cnt == 0) {
10261 BNX2X_ERR("CAM configuration error\n");
10262 return -EINVAL;
10263 }
10264
10265 return 0;
10266 }
10267
10268 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10269 {
10270 int cfg_size = 0, idx, port = BP_PORT(bp);
10271
10272 /* Aggregation of supported attributes of all external phys */
10273 bp->port.supported[0] = 0;
10274 bp->port.supported[1] = 0;
10275 switch (bp->link_params.num_phys) {
10276 case 1:
10277 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10278 cfg_size = 1;
10279 break;
10280 case 2:
10281 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10282 cfg_size = 1;
10283 break;
10284 case 3:
10285 if (bp->link_params.multi_phy_config &
10286 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10287 bp->port.supported[1] =
10288 bp->link_params.phy[EXT_PHY1].supported;
10289 bp->port.supported[0] =
10290 bp->link_params.phy[EXT_PHY2].supported;
10291 } else {
10292 bp->port.supported[0] =
10293 bp->link_params.phy[EXT_PHY1].supported;
10294 bp->port.supported[1] =
10295 bp->link_params.phy[EXT_PHY2].supported;
10296 }
10297 cfg_size = 2;
10298 break;
10299 }
10300
10301 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10302 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10303 SHMEM_RD(bp,
10304 dev_info.port_hw_config[port].external_phy_config),
10305 SHMEM_RD(bp,
10306 dev_info.port_hw_config[port].external_phy_config2));
10307 return;
10308 }
10309
10310 if (CHIP_IS_E3(bp))
10311 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10312 else {
10313 switch (switch_cfg) {
10314 case SWITCH_CFG_1G:
10315 bp->port.phy_addr = REG_RD(
10316 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10317 break;
10318 case SWITCH_CFG_10G:
10319 bp->port.phy_addr = REG_RD(
10320 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10321 break;
10322 default:
10323 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10324 bp->port.link_config[0]);
10325 return;
10326 }
10327 }
10328 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10329 /* mask what we support according to speed_cap_mask per configuration */
10330 for (idx = 0; idx < cfg_size; idx++) {
10331 if (!(bp->link_params.speed_cap_mask[idx] &
10332 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10333 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10334
10335 if (!(bp->link_params.speed_cap_mask[idx] &
10336 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10337 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10338
10339 if (!(bp->link_params.speed_cap_mask[idx] &
10340 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10341 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10342
10343 if (!(bp->link_params.speed_cap_mask[idx] &
10344 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10345 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10346
10347 if (!(bp->link_params.speed_cap_mask[idx] &
10348 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10349 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10350 SUPPORTED_1000baseT_Full);
10351
10352 if (!(bp->link_params.speed_cap_mask[idx] &
10353 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10354 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10355
10356 if (!(bp->link_params.speed_cap_mask[idx] &
10357 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10358 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10359
10360 }
10361
10362 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10363 bp->port.supported[1]);
10364 }
10365
10366 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10367 {
10368 u32 link_config, idx, cfg_size = 0;
10369 bp->port.advertising[0] = 0;
10370 bp->port.advertising[1] = 0;
10371 switch (bp->link_params.num_phys) {
10372 case 1:
10373 case 2:
10374 cfg_size = 1;
10375 break;
10376 case 3:
10377 cfg_size = 2;
10378 break;
10379 }
10380 for (idx = 0; idx < cfg_size; idx++) {
10381 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10382 link_config = bp->port.link_config[idx];
10383 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10384 case PORT_FEATURE_LINK_SPEED_AUTO:
10385 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10386 bp->link_params.req_line_speed[idx] =
10387 SPEED_AUTO_NEG;
10388 bp->port.advertising[idx] |=
10389 bp->port.supported[idx];
10390 if (bp->link_params.phy[EXT_PHY1].type ==
10391 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10392 bp->port.advertising[idx] |=
10393 (SUPPORTED_100baseT_Half |
10394 SUPPORTED_100baseT_Full);
10395 } else {
10396 /* force 10G, no AN */
10397 bp->link_params.req_line_speed[idx] =
10398 SPEED_10000;
10399 bp->port.advertising[idx] |=
10400 (ADVERTISED_10000baseT_Full |
10401 ADVERTISED_FIBRE);
10402 continue;
10403 }
10404 break;
10405
10406 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10407 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10408 bp->link_params.req_line_speed[idx] =
10409 SPEED_10;
10410 bp->port.advertising[idx] |=
10411 (ADVERTISED_10baseT_Full |
10412 ADVERTISED_TP);
10413 } else {
10414 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10415 link_config,
10416 bp->link_params.speed_cap_mask[idx]);
10417 return;
10418 }
10419 break;
10420
10421 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10422 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10423 bp->link_params.req_line_speed[idx] =
10424 SPEED_10;
10425 bp->link_params.req_duplex[idx] =
10426 DUPLEX_HALF;
10427 bp->port.advertising[idx] |=
10428 (ADVERTISED_10baseT_Half |
10429 ADVERTISED_TP);
10430 } else {
10431 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10432 link_config,
10433 bp->link_params.speed_cap_mask[idx]);
10434 return;
10435 }
10436 break;
10437
10438 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10439 if (bp->port.supported[idx] &
10440 SUPPORTED_100baseT_Full) {
10441 bp->link_params.req_line_speed[idx] =
10442 SPEED_100;
10443 bp->port.advertising[idx] |=
10444 (ADVERTISED_100baseT_Full |
10445 ADVERTISED_TP);
10446 } else {
10447 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10448 link_config,
10449 bp->link_params.speed_cap_mask[idx]);
10450 return;
10451 }
10452 break;
10453
10454 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10455 if (bp->port.supported[idx] &
10456 SUPPORTED_100baseT_Half) {
10457 bp->link_params.req_line_speed[idx] =
10458 SPEED_100;
10459 bp->link_params.req_duplex[idx] =
10460 DUPLEX_HALF;
10461 bp->port.advertising[idx] |=
10462 (ADVERTISED_100baseT_Half |
10463 ADVERTISED_TP);
10464 } else {
10465 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10466 link_config,
10467 bp->link_params.speed_cap_mask[idx]);
10468 return;
10469 }
10470 break;
10471
10472 case PORT_FEATURE_LINK_SPEED_1G:
10473 if (bp->port.supported[idx] &
10474 SUPPORTED_1000baseT_Full) {
10475 bp->link_params.req_line_speed[idx] =
10476 SPEED_1000;
10477 bp->port.advertising[idx] |=
10478 (ADVERTISED_1000baseT_Full |
10479 ADVERTISED_TP);
10480 } else {
10481 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10482 link_config,
10483 bp->link_params.speed_cap_mask[idx]);
10484 return;
10485 }
10486 break;
10487
10488 case PORT_FEATURE_LINK_SPEED_2_5G:
10489 if (bp->port.supported[idx] &
10490 SUPPORTED_2500baseX_Full) {
10491 bp->link_params.req_line_speed[idx] =
10492 SPEED_2500;
10493 bp->port.advertising[idx] |=
10494 (ADVERTISED_2500baseX_Full |
10495 ADVERTISED_TP);
10496 } else {
10497 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10498 link_config,
10499 bp->link_params.speed_cap_mask[idx]);
10500 return;
10501 }
10502 break;
10503
10504 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10505 if (bp->port.supported[idx] &
10506 SUPPORTED_10000baseT_Full) {
10507 bp->link_params.req_line_speed[idx] =
10508 SPEED_10000;
10509 bp->port.advertising[idx] |=
10510 (ADVERTISED_10000baseT_Full |
10511 ADVERTISED_FIBRE);
10512 } else {
10513 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10514 link_config,
10515 bp->link_params.speed_cap_mask[idx]);
10516 return;
10517 }
10518 break;
10519 case PORT_FEATURE_LINK_SPEED_20G:
10520 bp->link_params.req_line_speed[idx] = SPEED_20000;
10521
10522 break;
10523 default:
10524 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10525 link_config);
10526 bp->link_params.req_line_speed[idx] =
10527 SPEED_AUTO_NEG;
10528 bp->port.advertising[idx] =
10529 bp->port.supported[idx];
10530 break;
10531 }
10532
10533 bp->link_params.req_flow_ctrl[idx] = (link_config &
10534 PORT_FEATURE_FLOW_CONTROL_MASK);
10535 if (bp->link_params.req_flow_ctrl[idx] ==
10536 BNX2X_FLOW_CTRL_AUTO) {
10537 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10538 bp->link_params.req_flow_ctrl[idx] =
10539 BNX2X_FLOW_CTRL_NONE;
10540 else
10541 bnx2x_set_requested_fc(bp);
10542 }
10543
10544 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10545 bp->link_params.req_line_speed[idx],
10546 bp->link_params.req_duplex[idx],
10547 bp->link_params.req_flow_ctrl[idx],
10548 bp->port.advertising[idx]);
10549 }
10550 }
10551
10552 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10553 {
10554 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10555 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10556 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10557 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10558 }
10559
10560 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10561 {
10562 int port = BP_PORT(bp);
10563 u32 config;
10564 u32 ext_phy_type, ext_phy_config, eee_mode;
10565
10566 bp->link_params.bp = bp;
10567 bp->link_params.port = port;
10568
10569 bp->link_params.lane_config =
10570 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10571
10572 bp->link_params.speed_cap_mask[0] =
10573 SHMEM_RD(bp,
10574 dev_info.port_hw_config[port].speed_capability_mask);
10575 bp->link_params.speed_cap_mask[1] =
10576 SHMEM_RD(bp,
10577 dev_info.port_hw_config[port].speed_capability_mask2);
10578 bp->port.link_config[0] =
10579 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10580
10581 bp->port.link_config[1] =
10582 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10583
10584 bp->link_params.multi_phy_config =
10585 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10586 /* If the device is capable of WoL, set the default state according
10587 * to the HW
10588 */
10589 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10590 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10591 (config & PORT_FEATURE_WOL_ENABLED));
10592
10593 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10594 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10595 bp->flags |= NO_ISCSI_FLAG;
10596 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10597 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10598 bp->flags |= NO_FCOE_FLAG;
10599
10600 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10601 bp->link_params.lane_config,
10602 bp->link_params.speed_cap_mask[0],
10603 bp->port.link_config[0]);
10604
10605 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10606 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10607 bnx2x_phy_probe(&bp->link_params);
10608 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10609
10610 bnx2x_link_settings_requested(bp);
10611
10612 /*
10613 * If connected directly, work with the internal PHY, otherwise, work
10614 * with the external PHY
10615 */
10616 ext_phy_config =
10617 SHMEM_RD(bp,
10618 dev_info.port_hw_config[port].external_phy_config);
10619 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10620 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10621 bp->mdio.prtad = bp->port.phy_addr;
10622
10623 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10624 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10625 bp->mdio.prtad =
10626 XGXS_EXT_PHY_ADDR(ext_phy_config);
10627
10628 /* Configure link feature according to nvram value */
10629 eee_mode = (((SHMEM_RD(bp, dev_info.
10630 port_feature_config[port].eee_power_mode)) &
10631 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10632 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10633 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10634 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10635 EEE_MODE_ENABLE_LPI |
10636 EEE_MODE_OUTPUT_TIME;
10637 } else {
10638 bp->link_params.eee_mode = 0;
10639 }
10640 }
10641
10642 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10643 {
10644 u32 no_flags = NO_ISCSI_FLAG;
10645 int port = BP_PORT(bp);
10646 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10647 drv_lic_key[port].max_iscsi_conn);
10648
10649 if (!CNIC_SUPPORT(bp)) {
10650 bp->flags |= no_flags;
10651 return;
10652 }
10653
10654 /* Get the number of maximum allowed iSCSI connections */
10655 bp->cnic_eth_dev.max_iscsi_conn =
10656 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10657 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10658
10659 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10660 bp->cnic_eth_dev.max_iscsi_conn);
10661
10662 /*
10663 * If maximum allowed number of connections is zero -
10664 * disable the feature.
10665 */
10666 if (!bp->cnic_eth_dev.max_iscsi_conn)
10667 bp->flags |= no_flags;
10668
10669 }
10670
10671 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10672 {
10673 /* Port info */
10674 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10675 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10676 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10677 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10678
10679 /* Node info */
10680 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10681 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10682 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10683 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10684 }
10685 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10686 {
10687 int port = BP_PORT(bp);
10688 int func = BP_ABS_FUNC(bp);
10689 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10690 drv_lic_key[port].max_fcoe_conn);
10691
10692 if (!CNIC_SUPPORT(bp)) {
10693 bp->flags |= NO_FCOE_FLAG;
10694 return;
10695 }
10696
10697 /* Get the number of maximum allowed FCoE connections */
10698 bp->cnic_eth_dev.max_fcoe_conn =
10699 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10700 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10701
10702 /* Read the WWN: */
10703 if (!IS_MF(bp)) {
10704 /* Port info */
10705 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10706 SHMEM_RD(bp,
10707 dev_info.port_hw_config[port].
10708 fcoe_wwn_port_name_upper);
10709 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10710 SHMEM_RD(bp,
10711 dev_info.port_hw_config[port].
10712 fcoe_wwn_port_name_lower);
10713
10714 /* Node info */
10715 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10716 SHMEM_RD(bp,
10717 dev_info.port_hw_config[port].
10718 fcoe_wwn_node_name_upper);
10719 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10720 SHMEM_RD(bp,
10721 dev_info.port_hw_config[port].
10722 fcoe_wwn_node_name_lower);
10723 } else if (!IS_MF_SD(bp)) {
10724 /*
10725 * Read the WWN info only if the FCoE feature is enabled for
10726 * this function.
10727 */
10728 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10729 bnx2x_get_ext_wwn_info(bp, func);
10730
10731 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10732 bnx2x_get_ext_wwn_info(bp, func);
10733 }
10734
10735 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10736
10737 /*
10738 * If maximum allowed number of connections is zero -
10739 * disable the feature.
10740 */
10741 if (!bp->cnic_eth_dev.max_fcoe_conn)
10742 bp->flags |= NO_FCOE_FLAG;
10743 }
10744
10745 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10746 {
10747 /*
10748 * iSCSI may be dynamically disabled but reading
10749 * info here we will decrease memory usage by driver
10750 * if the feature is disabled for good
10751 */
10752 bnx2x_get_iscsi_info(bp);
10753 bnx2x_get_fcoe_info(bp);
10754 }
10755
10756 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10757 {
10758 u32 val, val2;
10759 int func = BP_ABS_FUNC(bp);
10760 int port = BP_PORT(bp);
10761 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10762 u8 *fip_mac = bp->fip_mac;
10763
10764 if (IS_MF(bp)) {
10765 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10766 * FCoE MAC then the appropriate feature should be disabled.
10767 * In non SD mode features configuration comes from struct
10768 * func_ext_config.
10769 */
10770 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10771 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10772 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10773 val2 = MF_CFG_RD(bp, func_ext_config[func].
10774 iscsi_mac_addr_upper);
10775 val = MF_CFG_RD(bp, func_ext_config[func].
10776 iscsi_mac_addr_lower);
10777 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10778 BNX2X_DEV_INFO
10779 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10780 } else {
10781 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10782 }
10783
10784 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10785 val2 = MF_CFG_RD(bp, func_ext_config[func].
10786 fcoe_mac_addr_upper);
10787 val = MF_CFG_RD(bp, func_ext_config[func].
10788 fcoe_mac_addr_lower);
10789 bnx2x_set_mac_buf(fip_mac, val, val2);
10790 BNX2X_DEV_INFO
10791 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10792 } else {
10793 bp->flags |= NO_FCOE_FLAG;
10794 }
10795
10796 bp->mf_ext_config = cfg;
10797
10798 } else { /* SD MODE */
10799 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10800 /* use primary mac as iscsi mac */
10801 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10802
10803 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10804 BNX2X_DEV_INFO
10805 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10806 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10807 /* use primary mac as fip mac */
10808 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10809 BNX2X_DEV_INFO("SD FCoE MODE\n");
10810 BNX2X_DEV_INFO
10811 ("Read FIP MAC: %pM\n", fip_mac);
10812 }
10813 }
10814
10815 if (IS_MF_STORAGE_SD(bp))
10816 /* Zero primary MAC configuration */
10817 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10818
10819 if (IS_MF_FCOE_AFEX(bp) || IS_MF_FCOE_SD(bp))
10820 /* use FIP MAC as primary MAC */
10821 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10822
10823 } else {
10824 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10825 iscsi_mac_upper);
10826 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10827 iscsi_mac_lower);
10828 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10829
10830 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10831 fcoe_fip_mac_upper);
10832 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10833 fcoe_fip_mac_lower);
10834 bnx2x_set_mac_buf(fip_mac, val, val2);
10835 }
10836
10837 /* Disable iSCSI OOO if MAC configuration is invalid. */
10838 if (!is_valid_ether_addr(iscsi_mac)) {
10839 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10840 memset(iscsi_mac, 0, ETH_ALEN);
10841 }
10842
10843 /* Disable FCoE if MAC configuration is invalid. */
10844 if (!is_valid_ether_addr(fip_mac)) {
10845 bp->flags |= NO_FCOE_FLAG;
10846 memset(bp->fip_mac, 0, ETH_ALEN);
10847 }
10848 }
10849
10850 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10851 {
10852 u32 val, val2;
10853 int func = BP_ABS_FUNC(bp);
10854 int port = BP_PORT(bp);
10855
10856 /* Zero primary MAC configuration */
10857 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10858
10859 if (BP_NOMCP(bp)) {
10860 BNX2X_ERROR("warning: random MAC workaround active\n");
10861 eth_hw_addr_random(bp->dev);
10862 } else if (IS_MF(bp)) {
10863 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10864 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10865 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10866 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10867 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10868
10869 if (CNIC_SUPPORT(bp))
10870 bnx2x_get_cnic_mac_hwinfo(bp);
10871 } else {
10872 /* in SF read MACs from port configuration */
10873 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10874 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10875 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10876
10877 if (CNIC_SUPPORT(bp))
10878 bnx2x_get_cnic_mac_hwinfo(bp);
10879 }
10880
10881 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10882
10883 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10884 dev_err(&bp->pdev->dev,
10885 "bad Ethernet MAC address configuration: %pM\n"
10886 "change it manually before bringing up the appropriate network interface\n",
10887 bp->dev->dev_addr);
10888 }
10889
10890 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10891 {
10892 int tmp;
10893 u32 cfg;
10894
10895 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10896 /* Take function: tmp = func */
10897 tmp = BP_ABS_FUNC(bp);
10898 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10899 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10900 } else {
10901 /* Take port: tmp = port */
10902 tmp = BP_PORT(bp);
10903 cfg = SHMEM_RD(bp,
10904 dev_info.port_hw_config[tmp].generic_features);
10905 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10906 }
10907 return cfg;
10908 }
10909
10910 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10911 {
10912 int /*abs*/func = BP_ABS_FUNC(bp);
10913 int vn;
10914 u32 val = 0;
10915 int rc = 0;
10916
10917 bnx2x_get_common_hwinfo(bp);
10918
10919 /*
10920 * initialize IGU parameters
10921 */
10922 if (CHIP_IS_E1x(bp)) {
10923 bp->common.int_block = INT_BLOCK_HC;
10924
10925 bp->igu_dsb_id = DEF_SB_IGU_ID;
10926 bp->igu_base_sb = 0;
10927 } else {
10928 bp->common.int_block = INT_BLOCK_IGU;
10929
10930 /* do not allow device reset during IGU info preocessing */
10931 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10932
10933 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10934
10935 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10936 int tout = 5000;
10937
10938 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10939
10940 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10941 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10942 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10943
10944 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10945 tout--;
10946 usleep_range(1000, 2000);
10947 }
10948
10949 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10950 dev_err(&bp->pdev->dev,
10951 "FORCING Normal Mode failed!!!\n");
10952 bnx2x_release_hw_lock(bp,
10953 HW_LOCK_RESOURCE_RESET);
10954 return -EPERM;
10955 }
10956 }
10957
10958 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10959 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10960 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10961 } else
10962 BNX2X_DEV_INFO("IGU Normal Mode\n");
10963
10964 rc = bnx2x_get_igu_cam_info(bp);
10965 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10966 if (rc)
10967 return rc;
10968 }
10969
10970 /*
10971 * set base FW non-default (fast path) status block id, this value is
10972 * used to initialize the fw_sb_id saved on the fp/queue structure to
10973 * determine the id used by the FW.
10974 */
10975 if (CHIP_IS_E1x(bp))
10976 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10977 else /*
10978 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10979 * the same queue are indicated on the same IGU SB). So we prefer
10980 * FW and IGU SBs to be the same value.
10981 */
10982 bp->base_fw_ndsb = bp->igu_base_sb;
10983
10984 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10985 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10986 bp->igu_sb_cnt, bp->base_fw_ndsb);
10987
10988 /*
10989 * Initialize MF configuration
10990 */
10991
10992 bp->mf_ov = 0;
10993 bp->mf_mode = 0;
10994 vn = BP_VN(bp);
10995
10996 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10997 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10998 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10999 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11000
11001 if (SHMEM2_HAS(bp, mf_cfg_addr))
11002 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11003 else
11004 bp->common.mf_cfg_base = bp->common.shmem_base +
11005 offsetof(struct shmem_region, func_mb) +
11006 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11007 /*
11008 * get mf configuration:
11009 * 1. existence of MF configuration
11010 * 2. MAC address must be legal (check only upper bytes)
11011 * for Switch-Independent mode;
11012 * OVLAN must be legal for Switch-Dependent mode
11013 * 3. SF_MODE configures specific MF mode
11014 */
11015 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11016 /* get mf configuration */
11017 val = SHMEM_RD(bp,
11018 dev_info.shared_feature_config.config);
11019 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11020
11021 switch (val) {
11022 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11023 val = MF_CFG_RD(bp, func_mf_config[func].
11024 mac_upper);
11025 /* check for legal mac (upper bytes)*/
11026 if (val != 0xffff) {
11027 bp->mf_mode = MULTI_FUNCTION_SI;
11028 bp->mf_config[vn] = MF_CFG_RD(bp,
11029 func_mf_config[func].config);
11030 } else
11031 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11032 break;
11033 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11034 if ((!CHIP_IS_E1x(bp)) &&
11035 (MF_CFG_RD(bp, func_mf_config[func].
11036 mac_upper) != 0xffff) &&
11037 (SHMEM2_HAS(bp,
11038 afex_driver_support))) {
11039 bp->mf_mode = MULTI_FUNCTION_AFEX;
11040 bp->mf_config[vn] = MF_CFG_RD(bp,
11041 func_mf_config[func].config);
11042 } else {
11043 BNX2X_DEV_INFO("can not configure afex mode\n");
11044 }
11045 break;
11046 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11047 /* get OV configuration */
11048 val = MF_CFG_RD(bp,
11049 func_mf_config[FUNC_0].e1hov_tag);
11050 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11051
11052 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11053 bp->mf_mode = MULTI_FUNCTION_SD;
11054 bp->mf_config[vn] = MF_CFG_RD(bp,
11055 func_mf_config[func].config);
11056 } else
11057 BNX2X_DEV_INFO("illegal OV for SD\n");
11058 break;
11059 default:
11060 /* Unknown configuration: reset mf_config */
11061 bp->mf_config[vn] = 0;
11062 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11063 }
11064 }
11065
11066 BNX2X_DEV_INFO("%s function mode\n",
11067 IS_MF(bp) ? "multi" : "single");
11068
11069 switch (bp->mf_mode) {
11070 case MULTI_FUNCTION_SD:
11071 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11072 FUNC_MF_CFG_E1HOV_TAG_MASK;
11073 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11074 bp->mf_ov = val;
11075 bp->path_has_ovlan = true;
11076
11077 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11078 func, bp->mf_ov, bp->mf_ov);
11079 } else {
11080 dev_err(&bp->pdev->dev,
11081 "No valid MF OV for func %d, aborting\n",
11082 func);
11083 return -EPERM;
11084 }
11085 break;
11086 case MULTI_FUNCTION_AFEX:
11087 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11088 break;
11089 case MULTI_FUNCTION_SI:
11090 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11091 func);
11092 break;
11093 default:
11094 if (vn) {
11095 dev_err(&bp->pdev->dev,
11096 "VN %d is in a single function mode, aborting\n",
11097 vn);
11098 return -EPERM;
11099 }
11100 break;
11101 }
11102
11103 /* check if other port on the path needs ovlan:
11104 * Since MF configuration is shared between ports
11105 * Possible mixed modes are only
11106 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11107 */
11108 if (CHIP_MODE_IS_4_PORT(bp) &&
11109 !bp->path_has_ovlan &&
11110 !IS_MF(bp) &&
11111 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11112 u8 other_port = !BP_PORT(bp);
11113 u8 other_func = BP_PATH(bp) + 2*other_port;
11114 val = MF_CFG_RD(bp,
11115 func_mf_config[other_func].e1hov_tag);
11116 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11117 bp->path_has_ovlan = true;
11118 }
11119 }
11120
11121 /* adjust igu_sb_cnt to MF for E1x */
11122 if (CHIP_IS_E1x(bp) && IS_MF(bp))
11123 bp->igu_sb_cnt /= E1HVN_MAX;
11124
11125 /* port info */
11126 bnx2x_get_port_hwinfo(bp);
11127
11128 /* Get MAC addresses */
11129 bnx2x_get_mac_hwinfo(bp);
11130
11131 bnx2x_get_cnic_info(bp);
11132
11133 return rc;
11134 }
11135
11136 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11137 {
11138 int cnt, i, block_end, rodi;
11139 char vpd_start[BNX2X_VPD_LEN+1];
11140 char str_id_reg[VENDOR_ID_LEN+1];
11141 char str_id_cap[VENDOR_ID_LEN+1];
11142 char *vpd_data;
11143 char *vpd_extended_data = NULL;
11144 u8 len;
11145
11146 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11147 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11148
11149 if (cnt < BNX2X_VPD_LEN)
11150 goto out_not_found;
11151
11152 /* VPD RO tag should be first tag after identifier string, hence
11153 * we should be able to find it in first BNX2X_VPD_LEN chars
11154 */
11155 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11156 PCI_VPD_LRDT_RO_DATA);
11157 if (i < 0)
11158 goto out_not_found;
11159
11160 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11161 pci_vpd_lrdt_size(&vpd_start[i]);
11162
11163 i += PCI_VPD_LRDT_TAG_SIZE;
11164
11165 if (block_end > BNX2X_VPD_LEN) {
11166 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11167 if (vpd_extended_data == NULL)
11168 goto out_not_found;
11169
11170 /* read rest of vpd image into vpd_extended_data */
11171 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11172 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11173 block_end - BNX2X_VPD_LEN,
11174 vpd_extended_data + BNX2X_VPD_LEN);
11175 if (cnt < (block_end - BNX2X_VPD_LEN))
11176 goto out_not_found;
11177 vpd_data = vpd_extended_data;
11178 } else
11179 vpd_data = vpd_start;
11180
11181 /* now vpd_data holds full vpd content in both cases */
11182
11183 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11184 PCI_VPD_RO_KEYWORD_MFR_ID);
11185 if (rodi < 0)
11186 goto out_not_found;
11187
11188 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11189
11190 if (len != VENDOR_ID_LEN)
11191 goto out_not_found;
11192
11193 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11194
11195 /* vendor specific info */
11196 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11197 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11198 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11199 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11200
11201 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11202 PCI_VPD_RO_KEYWORD_VENDOR0);
11203 if (rodi >= 0) {
11204 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11205
11206 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11207
11208 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11209 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11210 bp->fw_ver[len] = ' ';
11211 }
11212 }
11213 kfree(vpd_extended_data);
11214 return;
11215 }
11216 out_not_found:
11217 kfree(vpd_extended_data);
11218 return;
11219 }
11220
11221 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11222 {
11223 u32 flags = 0;
11224
11225 if (CHIP_REV_IS_FPGA(bp))
11226 SET_FLAGS(flags, MODE_FPGA);
11227 else if (CHIP_REV_IS_EMUL(bp))
11228 SET_FLAGS(flags, MODE_EMUL);
11229 else
11230 SET_FLAGS(flags, MODE_ASIC);
11231
11232 if (CHIP_MODE_IS_4_PORT(bp))
11233 SET_FLAGS(flags, MODE_PORT4);
11234 else
11235 SET_FLAGS(flags, MODE_PORT2);
11236
11237 if (CHIP_IS_E2(bp))
11238 SET_FLAGS(flags, MODE_E2);
11239 else if (CHIP_IS_E3(bp)) {
11240 SET_FLAGS(flags, MODE_E3);
11241 if (CHIP_REV(bp) == CHIP_REV_Ax)
11242 SET_FLAGS(flags, MODE_E3_A0);
11243 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11244 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11245 }
11246
11247 if (IS_MF(bp)) {
11248 SET_FLAGS(flags, MODE_MF);
11249 switch (bp->mf_mode) {
11250 case MULTI_FUNCTION_SD:
11251 SET_FLAGS(flags, MODE_MF_SD);
11252 break;
11253 case MULTI_FUNCTION_SI:
11254 SET_FLAGS(flags, MODE_MF_SI);
11255 break;
11256 case MULTI_FUNCTION_AFEX:
11257 SET_FLAGS(flags, MODE_MF_AFEX);
11258 break;
11259 }
11260 } else
11261 SET_FLAGS(flags, MODE_SF);
11262
11263 #if defined(__LITTLE_ENDIAN)
11264 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11265 #else /*(__BIG_ENDIAN)*/
11266 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11267 #endif
11268 INIT_MODE_FLAGS(bp) = flags;
11269 }
11270
11271 static int bnx2x_init_bp(struct bnx2x *bp)
11272 {
11273 int func;
11274 int rc;
11275
11276 mutex_init(&bp->port.phy_mutex);
11277 mutex_init(&bp->fw_mb_mutex);
11278 spin_lock_init(&bp->stats_lock);
11279
11280
11281 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11282 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11283 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11284 if (IS_PF(bp)) {
11285 rc = bnx2x_get_hwinfo(bp);
11286 if (rc)
11287 return rc;
11288 } else {
11289 random_ether_addr(bp->dev->dev_addr);
11290 }
11291
11292 bnx2x_set_modes_bitmap(bp);
11293
11294 rc = bnx2x_alloc_mem_bp(bp);
11295 if (rc)
11296 return rc;
11297
11298 bnx2x_read_fwinfo(bp);
11299
11300 func = BP_FUNC(bp);
11301
11302 /* need to reset chip if undi was active */
11303 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11304 /* init fw_seq */
11305 bp->fw_seq =
11306 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11307 DRV_MSG_SEQ_NUMBER_MASK;
11308 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11309
11310 bnx2x_prev_unload(bp);
11311 }
11312
11313
11314 if (CHIP_REV_IS_FPGA(bp))
11315 dev_err(&bp->pdev->dev, "FPGA detected\n");
11316
11317 if (BP_NOMCP(bp) && (func == 0))
11318 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11319
11320 bp->disable_tpa = disable_tpa;
11321 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11322
11323 /* Set TPA flags */
11324 if (bp->disable_tpa) {
11325 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11326 bp->dev->features &= ~NETIF_F_LRO;
11327 } else {
11328 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11329 bp->dev->features |= NETIF_F_LRO;
11330 }
11331
11332 if (CHIP_IS_E1(bp))
11333 bp->dropless_fc = 0;
11334 else
11335 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11336
11337 bp->mrrs = mrrs;
11338
11339 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11340 if (IS_VF(bp))
11341 bp->rx_ring_size = MAX_RX_AVAIL;
11342
11343 /* make sure that the numbers are in the right granularity */
11344 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11345 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11346
11347 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11348
11349 init_timer(&bp->timer);
11350 bp->timer.expires = jiffies + bp->current_interval;
11351 bp->timer.data = (unsigned long) bp;
11352 bp->timer.function = bnx2x_timer;
11353
11354 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11355 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11356 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11357 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11358 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11359 bnx2x_dcbx_init_params(bp);
11360 } else {
11361 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11362 }
11363
11364 if (CHIP_IS_E1x(bp))
11365 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11366 else
11367 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11368
11369 /* multiple tx priority */
11370 if (IS_VF(bp))
11371 bp->max_cos = 1;
11372 else if (CHIP_IS_E1x(bp))
11373 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11374 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11375 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11376 else if (CHIP_IS_E3B0(bp))
11377 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11378 else
11379 BNX2X_ERR("unknown chip %x revision %x\n",
11380 CHIP_NUM(bp), CHIP_REV(bp));
11381 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11382
11383 /* We need at least one default status block for slow-path events,
11384 * second status block for the L2 queue, and a third status block for
11385 * CNIC if supproted.
11386 */
11387 if (CNIC_SUPPORT(bp))
11388 bp->min_msix_vec_cnt = 3;
11389 else
11390 bp->min_msix_vec_cnt = 2;
11391 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11392
11393 return rc;
11394 }
11395
11396
11397 /****************************************************************************
11398 * General service functions
11399 ****************************************************************************/
11400
11401 /*
11402 * net_device service functions
11403 */
11404
11405 static int bnx2x_open_epilog(struct bnx2x *bp)
11406 {
11407 /* Enable sriov via delayed work. This must be done via delayed work
11408 * because it causes the probe of the vf devices to be run, which invoke
11409 * register_netdevice which must have rtnl lock taken. As we are holding
11410 * the lock right now, that could only work if the probe would not take
11411 * the lock. However, as the probe of the vf may be called from other
11412 * contexts as well (such as passthrough to vm failes) it can't assume
11413 * the lock is being held for it. Using delayed work here allows the
11414 * probe code to simply take the lock (i.e. wait for it to be released
11415 * if it is being held).
11416 */
11417 smp_mb__before_clear_bit();
11418 set_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, &bp->sp_rtnl_state);
11419 smp_mb__after_clear_bit();
11420 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11421
11422 return 0;
11423 }
11424
11425 /* called with rtnl_lock */
11426 static int bnx2x_open(struct net_device *dev)
11427 {
11428 struct bnx2x *bp = netdev_priv(dev);
11429 bool global = false;
11430 int other_engine = BP_PATH(bp) ? 0 : 1;
11431 bool other_load_status, load_status;
11432 int rc;
11433
11434 bp->stats_init = true;
11435
11436 netif_carrier_off(dev);
11437
11438 bnx2x_set_power_state(bp, PCI_D0);
11439
11440 /* If parity had happen during the unload, then attentions
11441 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11442 * want the first function loaded on the current engine to
11443 * complete the recovery.
11444 * Parity recovery is only relevant for PF driver.
11445 */
11446 if (IS_PF(bp)) {
11447 other_load_status = bnx2x_get_load_status(bp, other_engine);
11448 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11449 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11450 bnx2x_chk_parity_attn(bp, &global, true)) {
11451 do {
11452 /* If there are attentions and they are in a
11453 * global blocks, set the GLOBAL_RESET bit
11454 * regardless whether it will be this function
11455 * that will complete the recovery or not.
11456 */
11457 if (global)
11458 bnx2x_set_reset_global(bp);
11459
11460 /* Only the first function on the current
11461 * engine should try to recover in open. In case
11462 * of attentions in global blocks only the first
11463 * in the chip should try to recover.
11464 */
11465 if ((!load_status &&
11466 (!global || !other_load_status)) &&
11467 bnx2x_trylock_leader_lock(bp) &&
11468 !bnx2x_leader_reset(bp)) {
11469 netdev_info(bp->dev,
11470 "Recovered in open\n");
11471 break;
11472 }
11473
11474 /* recovery has failed... */
11475 bnx2x_set_power_state(bp, PCI_D3hot);
11476 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11477
11478 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11479 "If you still see this message after a few retries then power cycle is required.\n");
11480
11481 return -EAGAIN;
11482 } while (0);
11483 }
11484 }
11485
11486 bp->recovery_state = BNX2X_RECOVERY_DONE;
11487 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11488 if (rc)
11489 return rc;
11490 return bnx2x_open_epilog(bp);
11491 }
11492
11493 /* called with rtnl_lock */
11494 static int bnx2x_close(struct net_device *dev)
11495 {
11496 struct bnx2x *bp = netdev_priv(dev);
11497
11498 /* Unload the driver, release IRQs */
11499 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11500
11501 /* Power off */
11502 bnx2x_set_power_state(bp, PCI_D3hot);
11503
11504 return 0;
11505 }
11506
11507 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11508 struct bnx2x_mcast_ramrod_params *p)
11509 {
11510 int mc_count = netdev_mc_count(bp->dev);
11511 struct bnx2x_mcast_list_elem *mc_mac =
11512 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11513 struct netdev_hw_addr *ha;
11514
11515 if (!mc_mac)
11516 return -ENOMEM;
11517
11518 INIT_LIST_HEAD(&p->mcast_list);
11519
11520 netdev_for_each_mc_addr(ha, bp->dev) {
11521 mc_mac->mac = bnx2x_mc_addr(ha);
11522 list_add_tail(&mc_mac->link, &p->mcast_list);
11523 mc_mac++;
11524 }
11525
11526 p->mcast_list_len = mc_count;
11527
11528 return 0;
11529 }
11530
11531 static void bnx2x_free_mcast_macs_list(
11532 struct bnx2x_mcast_ramrod_params *p)
11533 {
11534 struct bnx2x_mcast_list_elem *mc_mac =
11535 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11536 link);
11537
11538 WARN_ON(!mc_mac);
11539 kfree(mc_mac);
11540 }
11541
11542 /**
11543 * bnx2x_set_uc_list - configure a new unicast MACs list.
11544 *
11545 * @bp: driver handle
11546 *
11547 * We will use zero (0) as a MAC type for these MACs.
11548 */
11549 static int bnx2x_set_uc_list(struct bnx2x *bp)
11550 {
11551 int rc;
11552 struct net_device *dev = bp->dev;
11553 struct netdev_hw_addr *ha;
11554 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11555 unsigned long ramrod_flags = 0;
11556
11557 /* First schedule a cleanup up of old configuration */
11558 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11559 if (rc < 0) {
11560 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11561 return rc;
11562 }
11563
11564 netdev_for_each_uc_addr(ha, dev) {
11565 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11566 BNX2X_UC_LIST_MAC, &ramrod_flags);
11567 if (rc == -EEXIST) {
11568 DP(BNX2X_MSG_SP,
11569 "Failed to schedule ADD operations: %d\n", rc);
11570 /* do not treat adding same MAC as error */
11571 rc = 0;
11572
11573 } else if (rc < 0) {
11574
11575 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11576 rc);
11577 return rc;
11578 }
11579 }
11580
11581 /* Execute the pending commands */
11582 __set_bit(RAMROD_CONT, &ramrod_flags);
11583 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11584 BNX2X_UC_LIST_MAC, &ramrod_flags);
11585 }
11586
11587 static int bnx2x_set_mc_list(struct bnx2x *bp)
11588 {
11589 struct net_device *dev = bp->dev;
11590 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11591 int rc = 0;
11592
11593 rparam.mcast_obj = &bp->mcast_obj;
11594
11595 /* first, clear all configured multicast MACs */
11596 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11597 if (rc < 0) {
11598 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11599 return rc;
11600 }
11601
11602 /* then, configure a new MACs list */
11603 if (netdev_mc_count(dev)) {
11604 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11605 if (rc) {
11606 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11607 rc);
11608 return rc;
11609 }
11610
11611 /* Now add the new MACs */
11612 rc = bnx2x_config_mcast(bp, &rparam,
11613 BNX2X_MCAST_CMD_ADD);
11614 if (rc < 0)
11615 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11616 rc);
11617
11618 bnx2x_free_mcast_macs_list(&rparam);
11619 }
11620
11621 return rc;
11622 }
11623
11624 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11625 void bnx2x_set_rx_mode(struct net_device *dev)
11626 {
11627 struct bnx2x *bp = netdev_priv(dev);
11628 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11629
11630 if (bp->state != BNX2X_STATE_OPEN) {
11631 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11632 return;
11633 }
11634
11635 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11636
11637 if (dev->flags & IFF_PROMISC)
11638 rx_mode = BNX2X_RX_MODE_PROMISC;
11639 else if ((dev->flags & IFF_ALLMULTI) ||
11640 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11641 CHIP_IS_E1(bp)))
11642 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11643 else {
11644 if (IS_PF(bp)) {
11645 /* some multicasts */
11646 if (bnx2x_set_mc_list(bp) < 0)
11647 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11648
11649 if (bnx2x_set_uc_list(bp) < 0)
11650 rx_mode = BNX2X_RX_MODE_PROMISC;
11651 } else {
11652 /* configuring mcast to a vf involves sleeping (when we
11653 * wait for the pf's response). Since this function is
11654 * called from non sleepable context we must schedule
11655 * a work item for this purpose
11656 */
11657 smp_mb__before_clear_bit();
11658 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11659 &bp->sp_rtnl_state);
11660 smp_mb__after_clear_bit();
11661 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11662 }
11663 }
11664
11665 bp->rx_mode = rx_mode;
11666 /* handle ISCSI SD mode */
11667 if (IS_MF_ISCSI_SD(bp))
11668 bp->rx_mode = BNX2X_RX_MODE_NONE;
11669
11670 /* Schedule the rx_mode command */
11671 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11672 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11673 return;
11674 }
11675
11676 if (IS_PF(bp)) {
11677 bnx2x_set_storm_rx_mode(bp);
11678 } else {
11679 /* configuring rx mode to storms in a vf involves sleeping (when
11680 * we wait for the pf's response). Since this function is
11681 * called from non sleepable context we must schedule
11682 * a work item for this purpose
11683 */
11684 smp_mb__before_clear_bit();
11685 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11686 &bp->sp_rtnl_state);
11687 smp_mb__after_clear_bit();
11688 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11689 }
11690 }
11691
11692 /* called with rtnl_lock */
11693 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11694 int devad, u16 addr)
11695 {
11696 struct bnx2x *bp = netdev_priv(netdev);
11697 u16 value;
11698 int rc;
11699
11700 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11701 prtad, devad, addr);
11702
11703 /* The HW expects different devad if CL22 is used */
11704 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11705
11706 bnx2x_acquire_phy_lock(bp);
11707 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11708 bnx2x_release_phy_lock(bp);
11709 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11710
11711 if (!rc)
11712 rc = value;
11713 return rc;
11714 }
11715
11716 /* called with rtnl_lock */
11717 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11718 u16 addr, u16 value)
11719 {
11720 struct bnx2x *bp = netdev_priv(netdev);
11721 int rc;
11722
11723 DP(NETIF_MSG_LINK,
11724 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11725 prtad, devad, addr, value);
11726
11727 /* The HW expects different devad if CL22 is used */
11728 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11729
11730 bnx2x_acquire_phy_lock(bp);
11731 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11732 bnx2x_release_phy_lock(bp);
11733 return rc;
11734 }
11735
11736 /* called with rtnl_lock */
11737 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11738 {
11739 struct bnx2x *bp = netdev_priv(dev);
11740 struct mii_ioctl_data *mdio = if_mii(ifr);
11741
11742 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11743 mdio->phy_id, mdio->reg_num, mdio->val_in);
11744
11745 if (!netif_running(dev))
11746 return -EAGAIN;
11747
11748 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11749 }
11750
11751 #ifdef CONFIG_NET_POLL_CONTROLLER
11752 static void poll_bnx2x(struct net_device *dev)
11753 {
11754 struct bnx2x *bp = netdev_priv(dev);
11755 int i;
11756
11757 for_each_eth_queue(bp, i) {
11758 struct bnx2x_fastpath *fp = &bp->fp[i];
11759 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11760 }
11761 }
11762 #endif
11763
11764 static int bnx2x_validate_addr(struct net_device *dev)
11765 {
11766 struct bnx2x *bp = netdev_priv(dev);
11767
11768 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11769 BNX2X_ERR("Non-valid Ethernet address\n");
11770 return -EADDRNOTAVAIL;
11771 }
11772 return 0;
11773 }
11774
11775 static const struct net_device_ops bnx2x_netdev_ops = {
11776 .ndo_open = bnx2x_open,
11777 .ndo_stop = bnx2x_close,
11778 .ndo_start_xmit = bnx2x_start_xmit,
11779 .ndo_select_queue = bnx2x_select_queue,
11780 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11781 .ndo_set_mac_address = bnx2x_change_mac_addr,
11782 .ndo_validate_addr = bnx2x_validate_addr,
11783 .ndo_do_ioctl = bnx2x_ioctl,
11784 .ndo_change_mtu = bnx2x_change_mtu,
11785 .ndo_fix_features = bnx2x_fix_features,
11786 .ndo_set_features = bnx2x_set_features,
11787 .ndo_tx_timeout = bnx2x_tx_timeout,
11788 #ifdef CONFIG_NET_POLL_CONTROLLER
11789 .ndo_poll_controller = poll_bnx2x,
11790 #endif
11791 .ndo_setup_tc = bnx2x_setup_tc,
11792 #ifdef CONFIG_BNX2X_SRIOV
11793 .ndo_set_vf_mac = bnx2x_set_vf_mac,
11794 #endif
11795 #ifdef NETDEV_FCOE_WWNN
11796 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11797 #endif
11798 };
11799
11800 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11801 {
11802 struct device *dev = &bp->pdev->dev;
11803
11804 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11805 bp->flags |= USING_DAC_FLAG;
11806 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11807 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11808 return -EIO;
11809 }
11810 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11811 dev_err(dev, "System does not support DMA, aborting\n");
11812 return -EIO;
11813 }
11814
11815 return 0;
11816 }
11817
11818 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11819 struct net_device *dev, unsigned long board_type)
11820 {
11821 int rc;
11822 u32 pci_cfg_dword;
11823 bool chip_is_e1x = (board_type == BCM57710 ||
11824 board_type == BCM57711 ||
11825 board_type == BCM57711E);
11826
11827 SET_NETDEV_DEV(dev, &pdev->dev);
11828
11829 bp->dev = dev;
11830 bp->pdev = pdev;
11831
11832 rc = pci_enable_device(pdev);
11833 if (rc) {
11834 dev_err(&bp->pdev->dev,
11835 "Cannot enable PCI device, aborting\n");
11836 goto err_out;
11837 }
11838
11839 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11840 dev_err(&bp->pdev->dev,
11841 "Cannot find PCI device base address, aborting\n");
11842 rc = -ENODEV;
11843 goto err_out_disable;
11844 }
11845
11846 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11847 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11848 rc = -ENODEV;
11849 goto err_out_disable;
11850 }
11851
11852 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11853 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11854 PCICFG_REVESION_ID_ERROR_VAL) {
11855 pr_err("PCI device error, probably due to fan failure, aborting\n");
11856 rc = -ENODEV;
11857 goto err_out_disable;
11858 }
11859
11860 if (atomic_read(&pdev->enable_cnt) == 1) {
11861 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11862 if (rc) {
11863 dev_err(&bp->pdev->dev,
11864 "Cannot obtain PCI resources, aborting\n");
11865 goto err_out_disable;
11866 }
11867
11868 pci_set_master(pdev);
11869 pci_save_state(pdev);
11870 }
11871
11872 if (IS_PF(bp)) {
11873 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11874 if (bp->pm_cap == 0) {
11875 dev_err(&bp->pdev->dev,
11876 "Cannot find power management capability, aborting\n");
11877 rc = -EIO;
11878 goto err_out_release;
11879 }
11880 }
11881
11882 if (!pci_is_pcie(pdev)) {
11883 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11884 rc = -EIO;
11885 goto err_out_release;
11886 }
11887
11888 rc = bnx2x_set_coherency_mask(bp);
11889 if (rc)
11890 goto err_out_release;
11891
11892 dev->mem_start = pci_resource_start(pdev, 0);
11893 dev->base_addr = dev->mem_start;
11894 dev->mem_end = pci_resource_end(pdev, 0);
11895
11896 dev->irq = pdev->irq;
11897
11898 bp->regview = pci_ioremap_bar(pdev, 0);
11899 if (!bp->regview) {
11900 dev_err(&bp->pdev->dev,
11901 "Cannot map register space, aborting\n");
11902 rc = -ENOMEM;
11903 goto err_out_release;
11904 }
11905
11906 /* In E1/E1H use pci device function given by kernel.
11907 * In E2/E3 read physical function from ME register since these chips
11908 * support Physical Device Assignment where kernel BDF maybe arbitrary
11909 * (depending on hypervisor).
11910 */
11911 if (chip_is_e1x) {
11912 bp->pf_num = PCI_FUNC(pdev->devfn);
11913 } else {
11914 /* chip is E2/3*/
11915 pci_read_config_dword(bp->pdev,
11916 PCICFG_ME_REGISTER, &pci_cfg_dword);
11917 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11918 ME_REG_ABS_PF_NUM_SHIFT);
11919 }
11920 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11921
11922 bnx2x_set_power_state(bp, PCI_D0);
11923
11924 /* clean indirect addresses */
11925 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11926 PCICFG_VENDOR_ID_OFFSET);
11927 /*
11928 * Clean the following indirect addresses for all functions since it
11929 * is not used by the driver.
11930 */
11931 if (IS_PF(bp)) {
11932 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11933 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11934 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11935 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11936
11937 if (chip_is_e1x) {
11938 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11939 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11940 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11941 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11942 }
11943
11944 /* Enable internal target-read (in case we are probed after PF
11945 * FLR). Must be done prior to any BAR read access. Only for
11946 * 57712 and up
11947 */
11948 if (!chip_is_e1x)
11949 REG_WR(bp,
11950 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11951 }
11952
11953 dev->watchdog_timeo = TX_TIMEOUT;
11954
11955 dev->netdev_ops = &bnx2x_netdev_ops;
11956 bnx2x_set_ethtool_ops(dev);
11957
11958 dev->priv_flags |= IFF_UNICAST_FLT;
11959
11960 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11961 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11962 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11963 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11964
11965 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11966 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11967
11968 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11969 if (bp->flags & USING_DAC_FLAG)
11970 dev->features |= NETIF_F_HIGHDMA;
11971
11972 /* Add Loopback capability to the device */
11973 dev->hw_features |= NETIF_F_LOOPBACK;
11974
11975 #ifdef BCM_DCBNL
11976 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11977 #endif
11978
11979 /* get_port_hwinfo() will set prtad and mmds properly */
11980 bp->mdio.prtad = MDIO_PRTAD_NONE;
11981 bp->mdio.mmds = 0;
11982 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11983 bp->mdio.dev = dev;
11984 bp->mdio.mdio_read = bnx2x_mdio_read;
11985 bp->mdio.mdio_write = bnx2x_mdio_write;
11986
11987 return 0;
11988
11989 err_out_release:
11990 if (atomic_read(&pdev->enable_cnt) == 1)
11991 pci_release_regions(pdev);
11992
11993 err_out_disable:
11994 pci_disable_device(pdev);
11995 pci_set_drvdata(pdev, NULL);
11996
11997 err_out:
11998 return rc;
11999 }
12000
12001 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
12002 {
12003 u32 val = 0;
12004
12005 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12006 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12007
12008 /* return value of 1=2.5GHz 2=5GHz */
12009 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12010 }
12011
12012 static int bnx2x_check_firmware(struct bnx2x *bp)
12013 {
12014 const struct firmware *firmware = bp->firmware;
12015 struct bnx2x_fw_file_hdr *fw_hdr;
12016 struct bnx2x_fw_file_section *sections;
12017 u32 offset, len, num_ops;
12018 __be16 *ops_offsets;
12019 int i;
12020 const u8 *fw_ver;
12021
12022 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12023 BNX2X_ERR("Wrong FW size\n");
12024 return -EINVAL;
12025 }
12026
12027 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12028 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12029
12030 /* Make sure none of the offsets and sizes make us read beyond
12031 * the end of the firmware data */
12032 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12033 offset = be32_to_cpu(sections[i].offset);
12034 len = be32_to_cpu(sections[i].len);
12035 if (offset + len > firmware->size) {
12036 BNX2X_ERR("Section %d length is out of bounds\n", i);
12037 return -EINVAL;
12038 }
12039 }
12040
12041 /* Likewise for the init_ops offsets */
12042 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12043 ops_offsets = (__force __be16 *)(firmware->data + offset);
12044 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12045
12046 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12047 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12048 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12049 return -EINVAL;
12050 }
12051 }
12052
12053 /* Check FW version */
12054 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12055 fw_ver = firmware->data + offset;
12056 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12057 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12058 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12059 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12060 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12061 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12062 BCM_5710_FW_MAJOR_VERSION,
12063 BCM_5710_FW_MINOR_VERSION,
12064 BCM_5710_FW_REVISION_VERSION,
12065 BCM_5710_FW_ENGINEERING_VERSION);
12066 return -EINVAL;
12067 }
12068
12069 return 0;
12070 }
12071
12072 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12073 {
12074 const __be32 *source = (const __be32 *)_source;
12075 u32 *target = (u32 *)_target;
12076 u32 i;
12077
12078 for (i = 0; i < n/4; i++)
12079 target[i] = be32_to_cpu(source[i]);
12080 }
12081
12082 /*
12083 Ops array is stored in the following format:
12084 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12085 */
12086 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12087 {
12088 const __be32 *source = (const __be32 *)_source;
12089 struct raw_op *target = (struct raw_op *)_target;
12090 u32 i, j, tmp;
12091
12092 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12093 tmp = be32_to_cpu(source[j]);
12094 target[i].op = (tmp >> 24) & 0xff;
12095 target[i].offset = tmp & 0xffffff;
12096 target[i].raw_data = be32_to_cpu(source[j + 1]);
12097 }
12098 }
12099
12100 /* IRO array is stored in the following format:
12101 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12102 */
12103 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12104 {
12105 const __be32 *source = (const __be32 *)_source;
12106 struct iro *target = (struct iro *)_target;
12107 u32 i, j, tmp;
12108
12109 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12110 target[i].base = be32_to_cpu(source[j]);
12111 j++;
12112 tmp = be32_to_cpu(source[j]);
12113 target[i].m1 = (tmp >> 16) & 0xffff;
12114 target[i].m2 = tmp & 0xffff;
12115 j++;
12116 tmp = be32_to_cpu(source[j]);
12117 target[i].m3 = (tmp >> 16) & 0xffff;
12118 target[i].size = tmp & 0xffff;
12119 j++;
12120 }
12121 }
12122
12123 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12124 {
12125 const __be16 *source = (const __be16 *)_source;
12126 u16 *target = (u16 *)_target;
12127 u32 i;
12128
12129 for (i = 0; i < n/2; i++)
12130 target[i] = be16_to_cpu(source[i]);
12131 }
12132
12133 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12134 do { \
12135 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12136 bp->arr = kmalloc(len, GFP_KERNEL); \
12137 if (!bp->arr) \
12138 goto lbl; \
12139 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12140 (u8 *)bp->arr, len); \
12141 } while (0)
12142
12143 static int bnx2x_init_firmware(struct bnx2x *bp)
12144 {
12145 const char *fw_file_name;
12146 struct bnx2x_fw_file_hdr *fw_hdr;
12147 int rc;
12148
12149 if (bp->firmware)
12150 return 0;
12151
12152 if (CHIP_IS_E1(bp))
12153 fw_file_name = FW_FILE_NAME_E1;
12154 else if (CHIP_IS_E1H(bp))
12155 fw_file_name = FW_FILE_NAME_E1H;
12156 else if (!CHIP_IS_E1x(bp))
12157 fw_file_name = FW_FILE_NAME_E2;
12158 else {
12159 BNX2X_ERR("Unsupported chip revision\n");
12160 return -EINVAL;
12161 }
12162 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12163
12164 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12165 if (rc) {
12166 BNX2X_ERR("Can't load firmware file %s\n",
12167 fw_file_name);
12168 goto request_firmware_exit;
12169 }
12170
12171 rc = bnx2x_check_firmware(bp);
12172 if (rc) {
12173 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12174 goto request_firmware_exit;
12175 }
12176
12177 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12178
12179 /* Initialize the pointers to the init arrays */
12180 /* Blob */
12181 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12182
12183 /* Opcodes */
12184 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12185
12186 /* Offsets */
12187 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12188 be16_to_cpu_n);
12189
12190 /* STORMs firmware */
12191 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12192 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12193 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12194 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12195 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12196 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12197 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12198 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12199 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12200 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12201 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12202 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12203 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12204 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12205 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12206 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12207 /* IRO */
12208 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12209
12210 return 0;
12211
12212 iro_alloc_err:
12213 kfree(bp->init_ops_offsets);
12214 init_offsets_alloc_err:
12215 kfree(bp->init_ops);
12216 init_ops_alloc_err:
12217 kfree(bp->init_data);
12218 request_firmware_exit:
12219 release_firmware(bp->firmware);
12220 bp->firmware = NULL;
12221
12222 return rc;
12223 }
12224
12225 static void bnx2x_release_firmware(struct bnx2x *bp)
12226 {
12227 kfree(bp->init_ops_offsets);
12228 kfree(bp->init_ops);
12229 kfree(bp->init_data);
12230 release_firmware(bp->firmware);
12231 bp->firmware = NULL;
12232 }
12233
12234
12235 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12236 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12237 .init_hw_cmn = bnx2x_init_hw_common,
12238 .init_hw_port = bnx2x_init_hw_port,
12239 .init_hw_func = bnx2x_init_hw_func,
12240
12241 .reset_hw_cmn = bnx2x_reset_common,
12242 .reset_hw_port = bnx2x_reset_port,
12243 .reset_hw_func = bnx2x_reset_func,
12244
12245 .gunzip_init = bnx2x_gunzip_init,
12246 .gunzip_end = bnx2x_gunzip_end,
12247
12248 .init_fw = bnx2x_init_firmware,
12249 .release_fw = bnx2x_release_firmware,
12250 };
12251
12252 void bnx2x__init_func_obj(struct bnx2x *bp)
12253 {
12254 /* Prepare DMAE related driver resources */
12255 bnx2x_setup_dmae(bp);
12256
12257 bnx2x_init_func_obj(bp, &bp->func_obj,
12258 bnx2x_sp(bp, func_rdata),
12259 bnx2x_sp_mapping(bp, func_rdata),
12260 bnx2x_sp(bp, func_afex_rdata),
12261 bnx2x_sp_mapping(bp, func_afex_rdata),
12262 &bnx2x_func_sp_drv);
12263 }
12264
12265 /* must be called after sriov-enable */
12266 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12267 {
12268 int cid_count = BNX2X_L2_MAX_CID(bp);
12269
12270 if (IS_SRIOV(bp))
12271 cid_count += BNX2X_VF_CIDS;
12272
12273 if (CNIC_SUPPORT(bp))
12274 cid_count += CNIC_CID_MAX;
12275
12276 return roundup(cid_count, QM_CID_ROUND);
12277 }
12278
12279 /**
12280 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12281 *
12282 * @dev: pci device
12283 *
12284 */
12285 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12286 int cnic_cnt, bool is_vf)
12287 {
12288 int pos, index;
12289 u16 control = 0;
12290
12291 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12292
12293 /*
12294 * If MSI-X is not supported - return number of SBs needed to support
12295 * one fast path queue: one FP queue + SB for CNIC
12296 */
12297 if (!pos) {
12298 dev_info(&pdev->dev, "no msix capability found\n");
12299 return 1 + cnic_cnt;
12300 }
12301 dev_info(&pdev->dev, "msix capability found\n");
12302
12303 /*
12304 * The value in the PCI configuration space is the index of the last
12305 * entry, namely one less than the actual size of the table, which is
12306 * exactly what we want to return from this function: number of all SBs
12307 * without the default SB.
12308 * For VFs there is no default SB, then we return (index+1).
12309 */
12310 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
12311
12312 index = control & PCI_MSIX_FLAGS_QSIZE;
12313
12314 return is_vf ? index + 1 : index;
12315 }
12316
12317 static int set_max_cos_est(int chip_id)
12318 {
12319 switch (chip_id) {
12320 case BCM57710:
12321 case BCM57711:
12322 case BCM57711E:
12323 return BNX2X_MULTI_TX_COS_E1X;
12324 case BCM57712:
12325 case BCM57712_MF:
12326 case BCM57712_VF:
12327 return BNX2X_MULTI_TX_COS_E2_E3A0;
12328 case BCM57800:
12329 case BCM57800_MF:
12330 case BCM57800_VF:
12331 case BCM57810:
12332 case BCM57810_MF:
12333 case BCM57840_4_10:
12334 case BCM57840_2_20:
12335 case BCM57840_O:
12336 case BCM57840_MFO:
12337 case BCM57810_VF:
12338 case BCM57840_MF:
12339 case BCM57840_VF:
12340 case BCM57811:
12341 case BCM57811_MF:
12342 case BCM57811_VF:
12343 return BNX2X_MULTI_TX_COS_E3B0;
12344 return 1;
12345 default:
12346 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12347 return -ENODEV;
12348 }
12349 }
12350
12351 static int set_is_vf(int chip_id)
12352 {
12353 switch (chip_id) {
12354 case BCM57712_VF:
12355 case BCM57800_VF:
12356 case BCM57810_VF:
12357 case BCM57840_VF:
12358 case BCM57811_VF:
12359 return true;
12360 default:
12361 return false;
12362 }
12363 }
12364
12365 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12366
12367 static int bnx2x_init_one(struct pci_dev *pdev,
12368 const struct pci_device_id *ent)
12369 {
12370 struct net_device *dev = NULL;
12371 struct bnx2x *bp;
12372 int pcie_width, pcie_speed;
12373 int rc, max_non_def_sbs;
12374 int rx_count, tx_count, rss_count, doorbell_size;
12375 int max_cos_est;
12376 bool is_vf;
12377 int cnic_cnt;
12378
12379 /* An estimated maximum supported CoS number according to the chip
12380 * version.
12381 * We will try to roughly estimate the maximum number of CoSes this chip
12382 * may support in order to minimize the memory allocated for Tx
12383 * netdev_queue's. This number will be accurately calculated during the
12384 * initialization of bp->max_cos based on the chip versions AND chip
12385 * revision in the bnx2x_init_bp().
12386 */
12387 max_cos_est = set_max_cos_est(ent->driver_data);
12388 if (max_cos_est < 0)
12389 return max_cos_est;
12390 is_vf = set_is_vf(ent->driver_data);
12391 cnic_cnt = is_vf ? 0 : 1;
12392
12393 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12394
12395 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12396 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12397
12398 if (rss_count < 1)
12399 return -EINVAL;
12400
12401 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12402 rx_count = rss_count + cnic_cnt;
12403
12404 /* Maximum number of netdev Tx queues:
12405 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12406 */
12407 tx_count = rss_count * max_cos_est + cnic_cnt;
12408
12409 /* dev zeroed in init_etherdev */
12410 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12411 if (!dev)
12412 return -ENOMEM;
12413
12414 bp = netdev_priv(dev);
12415
12416 bp->flags = 0;
12417 if (is_vf)
12418 bp->flags |= IS_VF_FLAG;
12419
12420 bp->igu_sb_cnt = max_non_def_sbs;
12421 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12422 bp->msg_enable = debug;
12423 bp->cnic_support = cnic_cnt;
12424 bp->cnic_probe = bnx2x_cnic_probe;
12425
12426 pci_set_drvdata(pdev, dev);
12427
12428 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12429 if (rc < 0) {
12430 free_netdev(dev);
12431 return rc;
12432 }
12433
12434 BNX2X_DEV_INFO("This is a %s function\n",
12435 IS_PF(bp) ? "physical" : "virtual");
12436 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12437 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12438 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12439 tx_count, rx_count);
12440
12441 rc = bnx2x_init_bp(bp);
12442 if (rc)
12443 goto init_one_exit;
12444
12445 /* Map doorbells here as we need the real value of bp->max_cos which
12446 * is initialized in bnx2x_init_bp() to determine the number of
12447 * l2 connections.
12448 */
12449 if (IS_VF(bp)) {
12450 bnx2x_vf_map_doorbells(bp);
12451 rc = bnx2x_vf_pci_alloc(bp);
12452 if (rc)
12453 goto init_one_exit;
12454 } else {
12455 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12456 if (doorbell_size > pci_resource_len(pdev, 2)) {
12457 dev_err(&bp->pdev->dev,
12458 "Cannot map doorbells, bar size too small, aborting\n");
12459 rc = -ENOMEM;
12460 goto init_one_exit;
12461 }
12462 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12463 doorbell_size);
12464 }
12465 if (!bp->doorbells) {
12466 dev_err(&bp->pdev->dev,
12467 "Cannot map doorbell space, aborting\n");
12468 rc = -ENOMEM;
12469 goto init_one_exit;
12470 }
12471
12472 if (IS_VF(bp)) {
12473 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12474 if (rc)
12475 goto init_one_exit;
12476 }
12477
12478 /* Enable SRIOV if capability found in configuration space.
12479 * Once the generic SR-IOV framework makes it in from the
12480 * pci tree this will be revised, to allow dynamic control
12481 * over the number of VFs. Right now, change the num of vfs
12482 * param below to enable SR-IOV.
12483 */
12484 rc = bnx2x_iov_init_one(bp, int_mode, 0/*num vfs*/);
12485 if (rc)
12486 goto init_one_exit;
12487
12488 /* calc qm_cid_count */
12489 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12490 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12491
12492 /* disable FCOE L2 queue for E1x*/
12493 if (CHIP_IS_E1x(bp))
12494 bp->flags |= NO_FCOE_FLAG;
12495
12496 /* disable FCOE for 57840 device, until FW supports it */
12497 switch (ent->driver_data) {
12498 case BCM57840_O:
12499 case BCM57840_4_10:
12500 case BCM57840_2_20:
12501 case BCM57840_MFO:
12502 case BCM57840_MF:
12503 bp->flags |= NO_FCOE_FLAG;
12504 }
12505
12506 /* Set bp->num_queues for MSI-X mode*/
12507 bnx2x_set_num_queues(bp);
12508
12509 /* Configure interrupt mode: try to enable MSI-X/MSI if
12510 * needed.
12511 */
12512 rc = bnx2x_set_int_mode(bp);
12513 if (rc) {
12514 dev_err(&pdev->dev, "Cannot set interrupts\n");
12515 goto init_one_exit;
12516 }
12517 BNX2X_DEV_INFO("set interrupts successfully\n");
12518
12519 /* register the net device */
12520 rc = register_netdev(dev);
12521 if (rc) {
12522 dev_err(&pdev->dev, "Cannot register net device\n");
12523 goto init_one_exit;
12524 }
12525 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12526
12527
12528 if (!NO_FCOE(bp)) {
12529 /* Add storage MAC address */
12530 rtnl_lock();
12531 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12532 rtnl_unlock();
12533 }
12534
12535 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12536 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12537 pcie_width, pcie_speed);
12538
12539 BNX2X_DEV_INFO(
12540 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12541 board_info[ent->driver_data].name,
12542 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12543 pcie_width,
12544 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12545 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12546 "5GHz (Gen2)" : "2.5GHz",
12547 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12548
12549 return 0;
12550
12551 init_one_exit:
12552 if (bp->regview)
12553 iounmap(bp->regview);
12554
12555 if (IS_PF(bp) && bp->doorbells)
12556 iounmap(bp->doorbells);
12557
12558 free_netdev(dev);
12559
12560 if (atomic_read(&pdev->enable_cnt) == 1)
12561 pci_release_regions(pdev);
12562
12563 pci_disable_device(pdev);
12564 pci_set_drvdata(pdev, NULL);
12565
12566 return rc;
12567 }
12568
12569 static void bnx2x_remove_one(struct pci_dev *pdev)
12570 {
12571 struct net_device *dev = pci_get_drvdata(pdev);
12572 struct bnx2x *bp;
12573
12574 if (!dev) {
12575 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12576 return;
12577 }
12578 bp = netdev_priv(dev);
12579
12580 /* Delete storage MAC address */
12581 if (!NO_FCOE(bp)) {
12582 rtnl_lock();
12583 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12584 rtnl_unlock();
12585 }
12586
12587 #ifdef BCM_DCBNL
12588 /* Delete app tlvs from dcbnl */
12589 bnx2x_dcbnl_update_applist(bp, true);
12590 #endif
12591
12592 unregister_netdev(dev);
12593
12594 /* Power on: we can't let PCI layer write to us while we are in D3 */
12595 if (IS_PF(bp))
12596 bnx2x_set_power_state(bp, PCI_D0);
12597
12598 /* Disable MSI/MSI-X */
12599 bnx2x_disable_msi(bp);
12600
12601 /* Power off */
12602 if (IS_PF(bp))
12603 bnx2x_set_power_state(bp, PCI_D3hot);
12604
12605 /* Make sure RESET task is not scheduled before continuing */
12606 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12607
12608 bnx2x_iov_remove_one(bp);
12609
12610 /* send message via vfpf channel to release the resources of this vf */
12611 if (IS_VF(bp))
12612 bnx2x_vfpf_release(bp);
12613
12614 if (bp->regview)
12615 iounmap(bp->regview);
12616
12617 /* for vf doorbells are part of the regview and were unmapped along with
12618 * it. FW is only loaded by PF.
12619 */
12620 if (IS_PF(bp)) {
12621 if (bp->doorbells)
12622 iounmap(bp->doorbells);
12623
12624 bnx2x_release_firmware(bp);
12625 }
12626 bnx2x_free_mem_bp(bp);
12627
12628 free_netdev(dev);
12629
12630 if (atomic_read(&pdev->enable_cnt) == 1)
12631 pci_release_regions(pdev);
12632
12633 pci_disable_device(pdev);
12634 pci_set_drvdata(pdev, NULL);
12635 }
12636
12637 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12638 {
12639 int i;
12640
12641 bp->state = BNX2X_STATE_ERROR;
12642
12643 bp->rx_mode = BNX2X_RX_MODE_NONE;
12644
12645 if (CNIC_LOADED(bp))
12646 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12647
12648 /* Stop Tx */
12649 bnx2x_tx_disable(bp);
12650
12651 bnx2x_netif_stop(bp, 0);
12652 /* Delete all NAPI objects */
12653 bnx2x_del_all_napi(bp);
12654 if (CNIC_LOADED(bp))
12655 bnx2x_del_all_napi_cnic(bp);
12656
12657 del_timer_sync(&bp->timer);
12658
12659 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12660
12661 /* Release IRQs */
12662 bnx2x_free_irq(bp);
12663
12664 /* Free SKBs, SGEs, TPA pool and driver internals */
12665 bnx2x_free_skbs(bp);
12666
12667 for_each_rx_queue(bp, i)
12668 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12669
12670 bnx2x_free_mem(bp);
12671
12672 bp->state = BNX2X_STATE_CLOSED;
12673
12674 netif_carrier_off(bp->dev);
12675
12676 return 0;
12677 }
12678
12679 static void bnx2x_eeh_recover(struct bnx2x *bp)
12680 {
12681 u32 val;
12682
12683 mutex_init(&bp->port.phy_mutex);
12684
12685
12686 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12687 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12688 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12689 BNX2X_ERR("BAD MCP validity signature\n");
12690 }
12691
12692 /**
12693 * bnx2x_io_error_detected - called when PCI error is detected
12694 * @pdev: Pointer to PCI device
12695 * @state: The current pci connection state
12696 *
12697 * This function is called after a PCI bus error affecting
12698 * this device has been detected.
12699 */
12700 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12701 pci_channel_state_t state)
12702 {
12703 struct net_device *dev = pci_get_drvdata(pdev);
12704 struct bnx2x *bp = netdev_priv(dev);
12705
12706 rtnl_lock();
12707
12708 netif_device_detach(dev);
12709
12710 if (state == pci_channel_io_perm_failure) {
12711 rtnl_unlock();
12712 return PCI_ERS_RESULT_DISCONNECT;
12713 }
12714
12715 if (netif_running(dev))
12716 bnx2x_eeh_nic_unload(bp);
12717
12718 pci_disable_device(pdev);
12719
12720 rtnl_unlock();
12721
12722 /* Request a slot reset */
12723 return PCI_ERS_RESULT_NEED_RESET;
12724 }
12725
12726 /**
12727 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12728 * @pdev: Pointer to PCI device
12729 *
12730 * Restart the card from scratch, as if from a cold-boot.
12731 */
12732 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12733 {
12734 struct net_device *dev = pci_get_drvdata(pdev);
12735 struct bnx2x *bp = netdev_priv(dev);
12736
12737 rtnl_lock();
12738
12739 if (pci_enable_device(pdev)) {
12740 dev_err(&pdev->dev,
12741 "Cannot re-enable PCI device after reset\n");
12742 rtnl_unlock();
12743 return PCI_ERS_RESULT_DISCONNECT;
12744 }
12745
12746 pci_set_master(pdev);
12747 pci_restore_state(pdev);
12748
12749 if (netif_running(dev))
12750 bnx2x_set_power_state(bp, PCI_D0);
12751
12752 rtnl_unlock();
12753
12754 return PCI_ERS_RESULT_RECOVERED;
12755 }
12756
12757 /**
12758 * bnx2x_io_resume - called when traffic can start flowing again
12759 * @pdev: Pointer to PCI device
12760 *
12761 * This callback is called when the error recovery driver tells us that
12762 * its OK to resume normal operation.
12763 */
12764 static void bnx2x_io_resume(struct pci_dev *pdev)
12765 {
12766 struct net_device *dev = pci_get_drvdata(pdev);
12767 struct bnx2x *bp = netdev_priv(dev);
12768
12769 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12770 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12771 return;
12772 }
12773
12774 rtnl_lock();
12775
12776 bnx2x_eeh_recover(bp);
12777
12778 if (netif_running(dev))
12779 bnx2x_nic_load(bp, LOAD_NORMAL);
12780
12781 netif_device_attach(dev);
12782
12783 rtnl_unlock();
12784 }
12785
12786 static const struct pci_error_handlers bnx2x_err_handler = {
12787 .error_detected = bnx2x_io_error_detected,
12788 .slot_reset = bnx2x_io_slot_reset,
12789 .resume = bnx2x_io_resume,
12790 };
12791
12792 static struct pci_driver bnx2x_pci_driver = {
12793 .name = DRV_MODULE_NAME,
12794 .id_table = bnx2x_pci_tbl,
12795 .probe = bnx2x_init_one,
12796 .remove = bnx2x_remove_one,
12797 .suspend = bnx2x_suspend,
12798 .resume = bnx2x_resume,
12799 .err_handler = &bnx2x_err_handler,
12800 };
12801
12802 static int __init bnx2x_init(void)
12803 {
12804 int ret;
12805
12806 pr_info("%s", version);
12807
12808 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12809 if (bnx2x_wq == NULL) {
12810 pr_err("Cannot create workqueue\n");
12811 return -ENOMEM;
12812 }
12813
12814 ret = pci_register_driver(&bnx2x_pci_driver);
12815 if (ret) {
12816 pr_err("Cannot register driver\n");
12817 destroy_workqueue(bnx2x_wq);
12818 }
12819 return ret;
12820 }
12821
12822 static void __exit bnx2x_cleanup(void)
12823 {
12824 struct list_head *pos, *q;
12825 pci_unregister_driver(&bnx2x_pci_driver);
12826
12827 destroy_workqueue(bnx2x_wq);
12828
12829 /* Free globablly allocated resources */
12830 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12831 struct bnx2x_prev_path_list *tmp =
12832 list_entry(pos, struct bnx2x_prev_path_list, list);
12833 list_del(pos);
12834 kfree(tmp);
12835 }
12836 }
12837
12838 void bnx2x_notify_link_changed(struct bnx2x *bp)
12839 {
12840 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12841 }
12842
12843 module_init(bnx2x_init);
12844 module_exit(bnx2x_cleanup);
12845
12846 /**
12847 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12848 *
12849 * @bp: driver handle
12850 * @set: set or clear the CAM entry
12851 *
12852 * This function will wait until the ramdord completion returns.
12853 * Return 0 if success, -ENODEV if ramrod doesn't return.
12854 */
12855 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12856 {
12857 unsigned long ramrod_flags = 0;
12858
12859 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12860 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12861 &bp->iscsi_l2_mac_obj, true,
12862 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12863 }
12864
12865 /* count denotes the number of new completions we have seen */
12866 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12867 {
12868 struct eth_spe *spe;
12869 int cxt_index, cxt_offset;
12870
12871 #ifdef BNX2X_STOP_ON_ERROR
12872 if (unlikely(bp->panic))
12873 return;
12874 #endif
12875
12876 spin_lock_bh(&bp->spq_lock);
12877 BUG_ON(bp->cnic_spq_pending < count);
12878 bp->cnic_spq_pending -= count;
12879
12880
12881 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12882 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12883 & SPE_HDR_CONN_TYPE) >>
12884 SPE_HDR_CONN_TYPE_SHIFT;
12885 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12886 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12887
12888 /* Set validation for iSCSI L2 client before sending SETUP
12889 * ramrod
12890 */
12891 if (type == ETH_CONNECTION_TYPE) {
12892 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12893 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12894 ILT_PAGE_CIDS;
12895 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12896 (cxt_index * ILT_PAGE_CIDS);
12897 bnx2x_set_ctx_validation(bp,
12898 &bp->context[cxt_index].
12899 vcxt[cxt_offset].eth,
12900 BNX2X_ISCSI_ETH_CID(bp));
12901 }
12902 }
12903
12904 /*
12905 * There may be not more than 8 L2, not more than 8 L5 SPEs
12906 * and in the air. We also check that number of outstanding
12907 * COMMON ramrods is not more than the EQ and SPQ can
12908 * accommodate.
12909 */
12910 if (type == ETH_CONNECTION_TYPE) {
12911 if (!atomic_read(&bp->cq_spq_left))
12912 break;
12913 else
12914 atomic_dec(&bp->cq_spq_left);
12915 } else if (type == NONE_CONNECTION_TYPE) {
12916 if (!atomic_read(&bp->eq_spq_left))
12917 break;
12918 else
12919 atomic_dec(&bp->eq_spq_left);
12920 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12921 (type == FCOE_CONNECTION_TYPE)) {
12922 if (bp->cnic_spq_pending >=
12923 bp->cnic_eth_dev.max_kwqe_pending)
12924 break;
12925 else
12926 bp->cnic_spq_pending++;
12927 } else {
12928 BNX2X_ERR("Unknown SPE type: %d\n", type);
12929 bnx2x_panic();
12930 break;
12931 }
12932
12933 spe = bnx2x_sp_get_next(bp);
12934 *spe = *bp->cnic_kwq_cons;
12935
12936 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12937 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12938
12939 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12940 bp->cnic_kwq_cons = bp->cnic_kwq;
12941 else
12942 bp->cnic_kwq_cons++;
12943 }
12944 bnx2x_sp_prod_update(bp);
12945 spin_unlock_bh(&bp->spq_lock);
12946 }
12947
12948 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12949 struct kwqe_16 *kwqes[], u32 count)
12950 {
12951 struct bnx2x *bp = netdev_priv(dev);
12952 int i;
12953
12954 #ifdef BNX2X_STOP_ON_ERROR
12955 if (unlikely(bp->panic)) {
12956 BNX2X_ERR("Can't post to SP queue while panic\n");
12957 return -EIO;
12958 }
12959 #endif
12960
12961 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12962 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12963 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12964 return -EAGAIN;
12965 }
12966
12967 spin_lock_bh(&bp->spq_lock);
12968
12969 for (i = 0; i < count; i++) {
12970 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12971
12972 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12973 break;
12974
12975 *bp->cnic_kwq_prod = *spe;
12976
12977 bp->cnic_kwq_pending++;
12978
12979 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12980 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12981 spe->data.update_data_addr.hi,
12982 spe->data.update_data_addr.lo,
12983 bp->cnic_kwq_pending);
12984
12985 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12986 bp->cnic_kwq_prod = bp->cnic_kwq;
12987 else
12988 bp->cnic_kwq_prod++;
12989 }
12990
12991 spin_unlock_bh(&bp->spq_lock);
12992
12993 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12994 bnx2x_cnic_sp_post(bp, 0);
12995
12996 return i;
12997 }
12998
12999 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13000 {
13001 struct cnic_ops *c_ops;
13002 int rc = 0;
13003
13004 mutex_lock(&bp->cnic_mutex);
13005 c_ops = rcu_dereference_protected(bp->cnic_ops,
13006 lockdep_is_held(&bp->cnic_mutex));
13007 if (c_ops)
13008 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13009 mutex_unlock(&bp->cnic_mutex);
13010
13011 return rc;
13012 }
13013
13014 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13015 {
13016 struct cnic_ops *c_ops;
13017 int rc = 0;
13018
13019 rcu_read_lock();
13020 c_ops = rcu_dereference(bp->cnic_ops);
13021 if (c_ops)
13022 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13023 rcu_read_unlock();
13024
13025 return rc;
13026 }
13027
13028 /*
13029 * for commands that have no data
13030 */
13031 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13032 {
13033 struct cnic_ctl_info ctl = {0};
13034
13035 ctl.cmd = cmd;
13036
13037 return bnx2x_cnic_ctl_send(bp, &ctl);
13038 }
13039
13040 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13041 {
13042 struct cnic_ctl_info ctl = {0};
13043
13044 /* first we tell CNIC and only then we count this as a completion */
13045 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13046 ctl.data.comp.cid = cid;
13047 ctl.data.comp.error = err;
13048
13049 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13050 bnx2x_cnic_sp_post(bp, 0);
13051 }
13052
13053
13054 /* Called with netif_addr_lock_bh() taken.
13055 * Sets an rx_mode config for an iSCSI ETH client.
13056 * Doesn't block.
13057 * Completion should be checked outside.
13058 */
13059 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13060 {
13061 unsigned long accept_flags = 0, ramrod_flags = 0;
13062 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13063 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13064
13065 if (start) {
13066 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13067 * because it's the only way for UIO Queue to accept
13068 * multicasts (in non-promiscuous mode only one Queue per
13069 * function will receive multicast packets (leading in our
13070 * case).
13071 */
13072 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13073 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13074 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13075 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13076
13077 /* Clear STOP_PENDING bit if START is requested */
13078 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13079
13080 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13081 } else
13082 /* Clear START_PENDING bit if STOP is requested */
13083 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13084
13085 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13086 set_bit(sched_state, &bp->sp_state);
13087 else {
13088 __set_bit(RAMROD_RX, &ramrod_flags);
13089 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13090 ramrod_flags);
13091 }
13092 }
13093
13094
13095 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13096 {
13097 struct bnx2x *bp = netdev_priv(dev);
13098 int rc = 0;
13099
13100 switch (ctl->cmd) {
13101 case DRV_CTL_CTXTBL_WR_CMD: {
13102 u32 index = ctl->data.io.offset;
13103 dma_addr_t addr = ctl->data.io.dma_addr;
13104
13105 bnx2x_ilt_wr(bp, index, addr);
13106 break;
13107 }
13108
13109 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13110 int count = ctl->data.credit.credit_count;
13111
13112 bnx2x_cnic_sp_post(bp, count);
13113 break;
13114 }
13115
13116 /* rtnl_lock is held. */
13117 case DRV_CTL_START_L2_CMD: {
13118 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13119 unsigned long sp_bits = 0;
13120
13121 /* Configure the iSCSI classification object */
13122 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13123 cp->iscsi_l2_client_id,
13124 cp->iscsi_l2_cid, BP_FUNC(bp),
13125 bnx2x_sp(bp, mac_rdata),
13126 bnx2x_sp_mapping(bp, mac_rdata),
13127 BNX2X_FILTER_MAC_PENDING,
13128 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13129 &bp->macs_pool);
13130
13131 /* Set iSCSI MAC address */
13132 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13133 if (rc)
13134 break;
13135
13136 mmiowb();
13137 barrier();
13138
13139 /* Start accepting on iSCSI L2 ring */
13140
13141 netif_addr_lock_bh(dev);
13142 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13143 netif_addr_unlock_bh(dev);
13144
13145 /* bits to wait on */
13146 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13147 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13148
13149 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13150 BNX2X_ERR("rx_mode completion timed out!\n");
13151
13152 break;
13153 }
13154
13155 /* rtnl_lock is held. */
13156 case DRV_CTL_STOP_L2_CMD: {
13157 unsigned long sp_bits = 0;
13158
13159 /* Stop accepting on iSCSI L2 ring */
13160 netif_addr_lock_bh(dev);
13161 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13162 netif_addr_unlock_bh(dev);
13163
13164 /* bits to wait on */
13165 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13166 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13167
13168 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13169 BNX2X_ERR("rx_mode completion timed out!\n");
13170
13171 mmiowb();
13172 barrier();
13173
13174 /* Unset iSCSI L2 MAC */
13175 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13176 BNX2X_ISCSI_ETH_MAC, true);
13177 break;
13178 }
13179 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13180 int count = ctl->data.credit.credit_count;
13181
13182 smp_mb__before_atomic_inc();
13183 atomic_add(count, &bp->cq_spq_left);
13184 smp_mb__after_atomic_inc();
13185 break;
13186 }
13187 case DRV_CTL_ULP_REGISTER_CMD: {
13188 int ulp_type = ctl->data.register_data.ulp_type;
13189
13190 if (CHIP_IS_E3(bp)) {
13191 int idx = BP_FW_MB_IDX(bp);
13192 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13193 int path = BP_PATH(bp);
13194 int port = BP_PORT(bp);
13195 int i;
13196 u32 scratch_offset;
13197 u32 *host_addr;
13198
13199 /* first write capability to shmem2 */
13200 if (ulp_type == CNIC_ULP_ISCSI)
13201 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13202 else if (ulp_type == CNIC_ULP_FCOE)
13203 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13204 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13205
13206 if ((ulp_type != CNIC_ULP_FCOE) ||
13207 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13208 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13209 break;
13210
13211 /* if reached here - should write fcoe capabilities */
13212 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13213 if (!scratch_offset)
13214 break;
13215 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13216 fcoe_features[path][port]);
13217 host_addr = (u32 *) &(ctl->data.register_data.
13218 fcoe_features);
13219 for (i = 0; i < sizeof(struct fcoe_capabilities);
13220 i += 4)
13221 REG_WR(bp, scratch_offset + i,
13222 *(host_addr + i/4));
13223 }
13224 break;
13225 }
13226
13227 case DRV_CTL_ULP_UNREGISTER_CMD: {
13228 int ulp_type = ctl->data.ulp_type;
13229
13230 if (CHIP_IS_E3(bp)) {
13231 int idx = BP_FW_MB_IDX(bp);
13232 u32 cap;
13233
13234 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13235 if (ulp_type == CNIC_ULP_ISCSI)
13236 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13237 else if (ulp_type == CNIC_ULP_FCOE)
13238 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13239 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13240 }
13241 break;
13242 }
13243
13244 default:
13245 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13246 rc = -EINVAL;
13247 }
13248
13249 return rc;
13250 }
13251
13252 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13253 {
13254 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13255
13256 if (bp->flags & USING_MSIX_FLAG) {
13257 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13258 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13259 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13260 } else {
13261 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13262 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13263 }
13264 if (!CHIP_IS_E1x(bp))
13265 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13266 else
13267 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13268
13269 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13270 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13271 cp->irq_arr[1].status_blk = bp->def_status_blk;
13272 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13273 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13274
13275 cp->num_irq = 2;
13276 }
13277
13278 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13279 {
13280 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13281
13282
13283 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13284 bnx2x_cid_ilt_lines(bp);
13285 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13286 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13287 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13288
13289 if (NO_ISCSI_OOO(bp))
13290 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13291 }
13292
13293 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13294 void *data)
13295 {
13296 struct bnx2x *bp = netdev_priv(dev);
13297 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13298 int rc;
13299
13300 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13301
13302 if (ops == NULL) {
13303 BNX2X_ERR("NULL ops received\n");
13304 return -EINVAL;
13305 }
13306
13307 if (!CNIC_SUPPORT(bp)) {
13308 BNX2X_ERR("Can't register CNIC when not supported\n");
13309 return -EOPNOTSUPP;
13310 }
13311
13312 if (!CNIC_LOADED(bp)) {
13313 rc = bnx2x_load_cnic(bp);
13314 if (rc) {
13315 BNX2X_ERR("CNIC-related load failed\n");
13316 return rc;
13317 }
13318
13319 }
13320
13321 bp->cnic_enabled = true;
13322
13323 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13324 if (!bp->cnic_kwq)
13325 return -ENOMEM;
13326
13327 bp->cnic_kwq_cons = bp->cnic_kwq;
13328 bp->cnic_kwq_prod = bp->cnic_kwq;
13329 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13330
13331 bp->cnic_spq_pending = 0;
13332 bp->cnic_kwq_pending = 0;
13333
13334 bp->cnic_data = data;
13335
13336 cp->num_irq = 0;
13337 cp->drv_state |= CNIC_DRV_STATE_REGD;
13338 cp->iro_arr = bp->iro_arr;
13339
13340 bnx2x_setup_cnic_irq_info(bp);
13341
13342 rcu_assign_pointer(bp->cnic_ops, ops);
13343
13344 return 0;
13345 }
13346
13347 static int bnx2x_unregister_cnic(struct net_device *dev)
13348 {
13349 struct bnx2x *bp = netdev_priv(dev);
13350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13351
13352 mutex_lock(&bp->cnic_mutex);
13353 cp->drv_state = 0;
13354 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13355 mutex_unlock(&bp->cnic_mutex);
13356 synchronize_rcu();
13357 kfree(bp->cnic_kwq);
13358 bp->cnic_kwq = NULL;
13359
13360 return 0;
13361 }
13362
13363 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13364 {
13365 struct bnx2x *bp = netdev_priv(dev);
13366 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13367
13368 /* If both iSCSI and FCoE are disabled - return NULL in
13369 * order to indicate CNIC that it should not try to work
13370 * with this device.
13371 */
13372 if (NO_ISCSI(bp) && NO_FCOE(bp))
13373 return NULL;
13374
13375 cp->drv_owner = THIS_MODULE;
13376 cp->chip_id = CHIP_ID(bp);
13377 cp->pdev = bp->pdev;
13378 cp->io_base = bp->regview;
13379 cp->io_base2 = bp->doorbells;
13380 cp->max_kwqe_pending = 8;
13381 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13382 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13383 bnx2x_cid_ilt_lines(bp);
13384 cp->ctx_tbl_len = CNIC_ILT_LINES;
13385 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13386 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13387 cp->drv_ctl = bnx2x_drv_ctl;
13388 cp->drv_register_cnic = bnx2x_register_cnic;
13389 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13390 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13391 cp->iscsi_l2_client_id =
13392 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13393 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13394
13395 if (NO_ISCSI_OOO(bp))
13396 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13397
13398 if (NO_ISCSI(bp))
13399 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13400
13401 if (NO_FCOE(bp))
13402 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13403
13404 BNX2X_DEV_INFO(
13405 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13406 cp->ctx_blk_size,
13407 cp->ctx_tbl_offset,
13408 cp->ctx_tbl_len,
13409 cp->starting_cid);
13410 return cp;
13411 }
13412
13413 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13414 {
13415 struct bnx2x *bp = fp->bp;
13416 u32 offset = BAR_USTRORM_INTMEM;
13417
13418 if (IS_VF(bp))
13419 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13420 else if (!CHIP_IS_E1x(bp))
13421 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13422 else
13423 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13424
13425 return offset;
13426 }
13427
13428 /* called only on E1H or E2.
13429 * When pretending to be PF, the pretend value is the function number 0...7
13430 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13431 * combination
13432 */
13433 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13434 {
13435 u32 pretend_reg;
13436
13437 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13438 return -1;
13439
13440 /* get my own pretend register */
13441 pretend_reg = bnx2x_get_pretend_reg(bp);
13442 REG_WR(bp, pretend_reg, pretend_func_val);
13443 REG_RD(bp, pretend_reg);
13444 return 0;
13445 }
Linux 2.6 libata-dev (mirror)