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dw_dmac: use __func__ constant in the debug prints
[linux-2.6/libata-dev.git] / drivers / iommu / amd_iommu.c
blobd90a421e9caccbbfc38a3d2eb4dd20ef2a50c77b
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <asm/msidef.h>
35 #include <asm/proto.h>
36 #include <asm/iommu.h>
37 #include <asm/gart.h>
38 #include <asm/dma.h>
39
40 #include "amd_iommu_proto.h"
41 #include "amd_iommu_types.h"
42
43 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
44
45 #define LOOP_TIMEOUT 100000
46
47 /*
48 * This bitmap is used to advertise the page sizes our hardware support
49 * to the IOMMU core, which will then use this information to split
50 * physically contiguous memory regions it is mapping into page sizes
51 * that we support.
52 *
53 * Traditionally the IOMMU core just handed us the mappings directly,
54 * after making sure the size is an order of a 4KiB page and that the
55 * mapping has natural alignment.
56 *
57 * To retain this behavior, we currently advertise that we support
58 * all page sizes that are an order of 4KiB.
59 *
60 * If at some point we'd like to utilize the IOMMU core's new behavior,
61 * we could change this to advertise the real page sizes we support.
62 */
63 #define AMD_IOMMU_PGSIZES (~0xFFFUL)
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 /*
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
78 */
79 static struct protection_domain *pt_domain;
80
81 static struct iommu_ops amd_iommu_ops;
82
83 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
84 int amd_iommu_max_glx_val = -1;
85
86 /*
87 * general struct to manage commands send to an IOMMU
88 */
89 struct iommu_cmd {
90 u32 data[4];
91 };
92
93 static void update_domain(struct protection_domain *domain);
94 static int __init alloc_passthrough_domain(void);
95
96 /****************************************************************************
97 *
98 * Helper functions
99 *
100 ****************************************************************************/
101
102 static struct iommu_dev_data *alloc_dev_data(u16 devid)
103 {
104 struct iommu_dev_data *dev_data;
105 unsigned long flags;
106
107 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
108 if (!dev_data)
109 return NULL;
110
111 dev_data->devid = devid;
112 atomic_set(&dev_data->bind, 0);
113
114 spin_lock_irqsave(&dev_data_list_lock, flags);
115 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
116 spin_unlock_irqrestore(&dev_data_list_lock, flags);
117
118 return dev_data;
119 }
120
121 static void free_dev_data(struct iommu_dev_data *dev_data)
122 {
123 unsigned long flags;
124
125 spin_lock_irqsave(&dev_data_list_lock, flags);
126 list_del(&dev_data->dev_data_list);
127 spin_unlock_irqrestore(&dev_data_list_lock, flags);
128
129 kfree(dev_data);
130 }
131
132 static struct iommu_dev_data *search_dev_data(u16 devid)
133 {
134 struct iommu_dev_data *dev_data;
135 unsigned long flags;
136
137 spin_lock_irqsave(&dev_data_list_lock, flags);
138 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
139 if (dev_data->devid == devid)
140 goto out_unlock;
141 }
142
143 dev_data = NULL;
144
145 out_unlock:
146 spin_unlock_irqrestore(&dev_data_list_lock, flags);
147
148 return dev_data;
149 }
150
151 static struct iommu_dev_data *find_dev_data(u16 devid)
152 {
153 struct iommu_dev_data *dev_data;
154
155 dev_data = search_dev_data(devid);
156
157 if (dev_data == NULL)
158 dev_data = alloc_dev_data(devid);
159
160 return dev_data;
161 }
162
163 static inline u16 get_device_id(struct device *dev)
164 {
165 struct pci_dev *pdev = to_pci_dev(dev);
166
167 return calc_devid(pdev->bus->number, pdev->devfn);
168 }
169
170 static struct iommu_dev_data *get_dev_data(struct device *dev)
171 {
172 return dev->archdata.iommu;
173 }
174
175 static bool pci_iommuv2_capable(struct pci_dev *pdev)
176 {
177 static const int caps[] = {
178 PCI_EXT_CAP_ID_ATS,
179 PCI_EXT_CAP_ID_PRI,
180 PCI_EXT_CAP_ID_PASID,
181 };
182 int i, pos;
183
184 for (i = 0; i < 3; ++i) {
185 pos = pci_find_ext_capability(pdev, caps[i]);
186 if (pos == 0)
187 return false;
188 }
189
190 return true;
191 }
192
193 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
194 {
195 struct iommu_dev_data *dev_data;
196
197 dev_data = get_dev_data(&pdev->dev);
198
199 return dev_data->errata & (1 << erratum) ? true : false;
200 }
201
202 /*
203 * In this function the list of preallocated protection domains is traversed to
204 * find the domain for a specific device
205 */
206 static struct dma_ops_domain *find_protection_domain(u16 devid)
207 {
208 struct dma_ops_domain *entry, *ret = NULL;
209 unsigned long flags;
210 u16 alias = amd_iommu_alias_table[devid];
211
212 if (list_empty(&iommu_pd_list))
213 return NULL;
214
215 spin_lock_irqsave(&iommu_pd_list_lock, flags);
216
217 list_for_each_entry(entry, &iommu_pd_list, list) {
218 if (entry->target_dev == devid ||
219 entry->target_dev == alias) {
220 ret = entry;
221 break;
222 }
223 }
224
225 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
226
227 return ret;
228 }
229
230 /*
231 * This function checks if the driver got a valid device from the caller to
232 * avoid dereferencing invalid pointers.
233 */
234 static bool check_device(struct device *dev)
235 {
236 u16 devid;
237
238 if (!dev || !dev->dma_mask)
239 return false;
240
241 /* No device or no PCI device */
242 if (dev->bus != &pci_bus_type)
243 return false;
244
245 devid = get_device_id(dev);
246
247 /* Out of our scope? */
248 if (devid > amd_iommu_last_bdf)
249 return false;
250
251 if (amd_iommu_rlookup_table[devid] == NULL)
252 return false;
253
254 return true;
255 }
256
257 static int iommu_init_device(struct device *dev)
258 {
259 struct pci_dev *pdev = to_pci_dev(dev);
260 struct iommu_dev_data *dev_data;
261 u16 alias;
262
263 if (dev->archdata.iommu)
264 return 0;
265
266 dev_data = find_dev_data(get_device_id(dev));
267 if (!dev_data)
268 return -ENOMEM;
269
270 alias = amd_iommu_alias_table[dev_data->devid];
271 if (alias != dev_data->devid) {
272 struct iommu_dev_data *alias_data;
273
274 alias_data = find_dev_data(alias);
275 if (alias_data == NULL) {
276 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
277 dev_name(dev));
278 free_dev_data(dev_data);
279 return -ENOTSUPP;
280 }
281 dev_data->alias_data = alias_data;
282 }
283
284 if (pci_iommuv2_capable(pdev)) {
285 struct amd_iommu *iommu;
286
287 iommu = amd_iommu_rlookup_table[dev_data->devid];
288 dev_data->iommu_v2 = iommu->is_iommu_v2;
289 }
290
291 dev->archdata.iommu = dev_data;
292
293 return 0;
294 }
295
296 static void iommu_ignore_device(struct device *dev)
297 {
298 u16 devid, alias;
299
300 devid = get_device_id(dev);
301 alias = amd_iommu_alias_table[devid];
302
303 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
304 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
305
306 amd_iommu_rlookup_table[devid] = NULL;
307 amd_iommu_rlookup_table[alias] = NULL;
308 }
309
310 static void iommu_uninit_device(struct device *dev)
311 {
312 /*
313 * Nothing to do here - we keep dev_data around for unplugged devices
314 * and reuse it when the device is re-plugged - not doing so would
315 * introduce a ton of races.
316 */
317 }
318
319 void __init amd_iommu_uninit_devices(void)
320 {
321 struct iommu_dev_data *dev_data, *n;
322 struct pci_dev *pdev = NULL;
323
324 for_each_pci_dev(pdev) {
325
326 if (!check_device(&pdev->dev))
327 continue;
328
329 iommu_uninit_device(&pdev->dev);
330 }
331
332 /* Free all of our dev_data structures */
333 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
334 free_dev_data(dev_data);
335 }
336
337 int __init amd_iommu_init_devices(void)
338 {
339 struct pci_dev *pdev = NULL;
340 int ret = 0;
341
342 for_each_pci_dev(pdev) {
343
344 if (!check_device(&pdev->dev))
345 continue;
346
347 ret = iommu_init_device(&pdev->dev);
348 if (ret == -ENOTSUPP)
349 iommu_ignore_device(&pdev->dev);
350 else if (ret)
351 goto out_free;
352 }
353
354 return 0;
355
356 out_free:
357
358 amd_iommu_uninit_devices();
359
360 return ret;
361 }
362 #ifdef CONFIG_AMD_IOMMU_STATS
363
364 /*
365 * Initialization code for statistics collection
366 */
367
368 DECLARE_STATS_COUNTER(compl_wait);
369 DECLARE_STATS_COUNTER(cnt_map_single);
370 DECLARE_STATS_COUNTER(cnt_unmap_single);
371 DECLARE_STATS_COUNTER(cnt_map_sg);
372 DECLARE_STATS_COUNTER(cnt_unmap_sg);
373 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
374 DECLARE_STATS_COUNTER(cnt_free_coherent);
375 DECLARE_STATS_COUNTER(cross_page);
376 DECLARE_STATS_COUNTER(domain_flush_single);
377 DECLARE_STATS_COUNTER(domain_flush_all);
378 DECLARE_STATS_COUNTER(alloced_io_mem);
379 DECLARE_STATS_COUNTER(total_map_requests);
380 DECLARE_STATS_COUNTER(complete_ppr);
381 DECLARE_STATS_COUNTER(invalidate_iotlb);
382 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
383 DECLARE_STATS_COUNTER(pri_requests);
384
385
386 static struct dentry *stats_dir;
387 static struct dentry *de_fflush;
388
389 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
390 {
391 if (stats_dir == NULL)
392 return;
393
394 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
395 &cnt->value);
396 }
397
398 static void amd_iommu_stats_init(void)
399 {
400 stats_dir = debugfs_create_dir("amd-iommu", NULL);
401 if (stats_dir == NULL)
402 return;
403
404 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
405 (u32 *)&amd_iommu_unmap_flush);
406
407 amd_iommu_stats_add(&compl_wait);
408 amd_iommu_stats_add(&cnt_map_single);
409 amd_iommu_stats_add(&cnt_unmap_single);
410 amd_iommu_stats_add(&cnt_map_sg);
411 amd_iommu_stats_add(&cnt_unmap_sg);
412 amd_iommu_stats_add(&cnt_alloc_coherent);
413 amd_iommu_stats_add(&cnt_free_coherent);
414 amd_iommu_stats_add(&cross_page);
415 amd_iommu_stats_add(&domain_flush_single);
416 amd_iommu_stats_add(&domain_flush_all);
417 amd_iommu_stats_add(&alloced_io_mem);
418 amd_iommu_stats_add(&total_map_requests);
419 amd_iommu_stats_add(&complete_ppr);
420 amd_iommu_stats_add(&invalidate_iotlb);
421 amd_iommu_stats_add(&invalidate_iotlb_all);
422 amd_iommu_stats_add(&pri_requests);
423 }
424
425 #endif
426
427 /****************************************************************************
428 *
429 * Interrupt handling functions
430 *
431 ****************************************************************************/
432
433 static void dump_dte_entry(u16 devid)
434 {
435 int i;
436
437 for (i = 0; i < 4; ++i)
438 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
439 amd_iommu_dev_table[devid].data[i]);
440 }
441
442 static void dump_command(unsigned long phys_addr)
443 {
444 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
445 int i;
446
447 for (i = 0; i < 4; ++i)
448 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
449 }
450
451 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
452 {
453 int type, devid, domid, flags;
454 volatile u32 *event = __evt;
455 int count = 0;
456 u64 address;
457
458 retry:
459 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
460 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
461 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
462 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
463 address = (u64)(((u64)event[3]) << 32) | event[2];
464
465 if (type == 0) {
466 /* Did we hit the erratum? */
467 if (++count == LOOP_TIMEOUT) {
468 pr_err("AMD-Vi: No event written to event log\n");
469 return;
470 }
471 udelay(1);
472 goto retry;
473 }
474
475 printk(KERN_ERR "AMD-Vi: Event logged [");
476
477 switch (type) {
478 case EVENT_TYPE_ILL_DEV:
479 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
480 "address=0x%016llx flags=0x%04x]\n",
481 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
482 address, flags);
483 dump_dte_entry(devid);
484 break;
485 case EVENT_TYPE_IO_FAULT:
486 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
487 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
488 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
489 domid, address, flags);
490 break;
491 case EVENT_TYPE_DEV_TAB_ERR:
492 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
493 "address=0x%016llx flags=0x%04x]\n",
494 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
495 address, flags);
496 break;
497 case EVENT_TYPE_PAGE_TAB_ERR:
498 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
499 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
500 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
501 domid, address, flags);
502 break;
503 case EVENT_TYPE_ILL_CMD:
504 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
505 dump_command(address);
506 break;
507 case EVENT_TYPE_CMD_HARD_ERR:
508 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
509 "flags=0x%04x]\n", address, flags);
510 break;
511 case EVENT_TYPE_IOTLB_INV_TO:
512 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
513 "address=0x%016llx]\n",
514 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
515 address);
516 break;
517 case EVENT_TYPE_INV_DEV_REQ:
518 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
519 "address=0x%016llx flags=0x%04x]\n",
520 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
521 address, flags);
522 break;
523 default:
524 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
525 }
526
527 memset(__evt, 0, 4 * sizeof(u32));
528 }
529
530 static void iommu_poll_events(struct amd_iommu *iommu)
531 {
532 u32 head, tail;
533 unsigned long flags;
534
535 spin_lock_irqsave(&iommu->lock, flags);
536
537 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
538 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
539
540 while (head != tail) {
541 iommu_print_event(iommu, iommu->evt_buf + head);
542 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
543 }
544
545 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
546
547 spin_unlock_irqrestore(&iommu->lock, flags);
548 }
549
550 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u32 head)
551 {
552 struct amd_iommu_fault fault;
553 volatile u64 *raw;
554 int i;
555
556 INC_STATS_COUNTER(pri_requests);
557
558 raw = (u64 *)(iommu->ppr_log + head);
559
560 /*
561 * Hardware bug: Interrupt may arrive before the entry is written to
562 * memory. If this happens we need to wait for the entry to arrive.
563 */
564 for (i = 0; i < LOOP_TIMEOUT; ++i) {
565 if (PPR_REQ_TYPE(raw[0]) != 0)
566 break;
567 udelay(1);
568 }
569
570 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
571 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
572 return;
573 }
574
575 fault.address = raw[1];
576 fault.pasid = PPR_PASID(raw[0]);
577 fault.device_id = PPR_DEVID(raw[0]);
578 fault.tag = PPR_TAG(raw[0]);
579 fault.flags = PPR_FLAGS(raw[0]);
580
581 /*
582 * To detect the hardware bug we need to clear the entry
583 * to back to zero.
584 */
585 raw[0] = raw[1] = 0;
586
587 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
588 }
589
590 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
591 {
592 unsigned long flags;
593 u32 head, tail;
594
595 if (iommu->ppr_log == NULL)
596 return;
597
598 spin_lock_irqsave(&iommu->lock, flags);
599
600 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
601 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
602
603 while (head != tail) {
604
605 /* Handle PPR entry */
606 iommu_handle_ppr_entry(iommu, head);
607
608 /* Update and refresh ring-buffer state*/
609 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
610 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
611 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
612 }
613
614 /* enable ppr interrupts again */
615 writel(MMIO_STATUS_PPR_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET);
616
617 spin_unlock_irqrestore(&iommu->lock, flags);
618 }
619
620 irqreturn_t amd_iommu_int_thread(int irq, void *data)
621 {
622 struct amd_iommu *iommu;
623
624 for_each_iommu(iommu) {
625 iommu_poll_events(iommu);
626 iommu_poll_ppr_log(iommu);
627 }
628
629 return IRQ_HANDLED;
630 }
631
632 irqreturn_t amd_iommu_int_handler(int irq, void *data)
633 {
634 return IRQ_WAKE_THREAD;
635 }
636
637 /****************************************************************************
638 *
639 * IOMMU command queuing functions
640 *
641 ****************************************************************************/
642
643 static int wait_on_sem(volatile u64 *sem)
644 {
645 int i = 0;
646
647 while (*sem == 0 && i < LOOP_TIMEOUT) {
648 udelay(1);
649 i += 1;
650 }
651
652 if (i == LOOP_TIMEOUT) {
653 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
654 return -EIO;
655 }
656
657 return 0;
658 }
659
660 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
661 struct iommu_cmd *cmd,
662 u32 tail)
663 {
664 u8 *target;
665
666 target = iommu->cmd_buf + tail;
667 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
668
669 /* Copy command to buffer */
670 memcpy(target, cmd, sizeof(*cmd));
671
672 /* Tell the IOMMU about it */
673 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
674 }
675
676 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
677 {
678 WARN_ON(address & 0x7ULL);
679
680 memset(cmd, 0, sizeof(*cmd));
681 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
682 cmd->data[1] = upper_32_bits(__pa(address));
683 cmd->data[2] = 1;
684 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
685 }
686
687 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
688 {
689 memset(cmd, 0, sizeof(*cmd));
690 cmd->data[0] = devid;
691 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
692 }
693
694 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
695 size_t size, u16 domid, int pde)
696 {
697 u64 pages;
698 int s;
699
700 pages = iommu_num_pages(address, size, PAGE_SIZE);
701 s = 0;
702
703 if (pages > 1) {
704 /*
705 * If we have to flush more than one page, flush all
706 * TLB entries for this domain
707 */
708 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
709 s = 1;
710 }
711
712 address &= PAGE_MASK;
713
714 memset(cmd, 0, sizeof(*cmd));
715 cmd->data[1] |= domid;
716 cmd->data[2] = lower_32_bits(address);
717 cmd->data[3] = upper_32_bits(address);
718 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
719 if (s) /* size bit - we flush more than one 4kb page */
720 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
721 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
722 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
723 }
724
725 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
726 u64 address, size_t size)
727 {
728 u64 pages;
729 int s;
730
731 pages = iommu_num_pages(address, size, PAGE_SIZE);
732 s = 0;
733
734 if (pages > 1) {
735 /*
736 * If we have to flush more than one page, flush all
737 * TLB entries for this domain
738 */
739 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
740 s = 1;
741 }
742
743 address &= PAGE_MASK;
744
745 memset(cmd, 0, sizeof(*cmd));
746 cmd->data[0] = devid;
747 cmd->data[0] |= (qdep & 0xff) << 24;
748 cmd->data[1] = devid;
749 cmd->data[2] = lower_32_bits(address);
750 cmd->data[3] = upper_32_bits(address);
751 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
752 if (s)
753 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
754 }
755
756 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
757 u64 address, bool size)
758 {
759 memset(cmd, 0, sizeof(*cmd));
760
761 address &= ~(0xfffULL);
762
763 cmd->data[0] = pasid & PASID_MASK;
764 cmd->data[1] = domid;
765 cmd->data[2] = lower_32_bits(address);
766 cmd->data[3] = upper_32_bits(address);
767 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
768 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
769 if (size)
770 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
771 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
772 }
773
774 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
775 int qdep, u64 address, bool size)
776 {
777 memset(cmd, 0, sizeof(*cmd));
778
779 address &= ~(0xfffULL);
780
781 cmd->data[0] = devid;
782 cmd->data[0] |= (pasid & 0xff) << 16;
783 cmd->data[0] |= (qdep & 0xff) << 24;
784 cmd->data[1] = devid;
785 cmd->data[1] |= ((pasid >> 8) & 0xfff) << 16;
786 cmd->data[2] = lower_32_bits(address);
787 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
788 cmd->data[3] = upper_32_bits(address);
789 if (size)
790 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
791 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
792 }
793
794 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
795 int status, int tag, bool gn)
796 {
797 memset(cmd, 0, sizeof(*cmd));
798
799 cmd->data[0] = devid;
800 if (gn) {
801 cmd->data[1] = pasid & PASID_MASK;
802 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
803 }
804 cmd->data[3] = tag & 0x1ff;
805 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
806
807 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
808 }
809
810 static void build_inv_all(struct iommu_cmd *cmd)
811 {
812 memset(cmd, 0, sizeof(*cmd));
813 CMD_SET_TYPE(cmd, CMD_INV_ALL);
814 }
815
816 /*
817 * Writes the command to the IOMMUs command buffer and informs the
818 * hardware about the new command.
819 */
820 static int iommu_queue_command_sync(struct amd_iommu *iommu,
821 struct iommu_cmd *cmd,
822 bool sync)
823 {
824 u32 left, tail, head, next_tail;
825 unsigned long flags;
826
827 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
828
829 again:
830 spin_lock_irqsave(&iommu->lock, flags);
831
832 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
833 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
834 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
835 left = (head - next_tail) % iommu->cmd_buf_size;
836
837 if (left <= 2) {
838 struct iommu_cmd sync_cmd;
839 volatile u64 sem = 0;
840 int ret;
841
842 build_completion_wait(&sync_cmd, (u64)&sem);
843 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
844
845 spin_unlock_irqrestore(&iommu->lock, flags);
846
847 if ((ret = wait_on_sem(&sem)) != 0)
848 return ret;
849
850 goto again;
851 }
852
853 copy_cmd_to_buffer(iommu, cmd, tail);
854
855 /* We need to sync now to make sure all commands are processed */
856 iommu->need_sync = sync;
857
858 spin_unlock_irqrestore(&iommu->lock, flags);
859
860 return 0;
861 }
862
863 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
864 {
865 return iommu_queue_command_sync(iommu, cmd, true);
866 }
867
868 /*
869 * This function queues a completion wait command into the command
870 * buffer of an IOMMU
871 */
872 static int iommu_completion_wait(struct amd_iommu *iommu)
873 {
874 struct iommu_cmd cmd;
875 volatile u64 sem = 0;
876 int ret;
877
878 if (!iommu->need_sync)
879 return 0;
880
881 build_completion_wait(&cmd, (u64)&sem);
882
883 ret = iommu_queue_command_sync(iommu, &cmd, false);
884 if (ret)
885 return ret;
886
887 return wait_on_sem(&sem);
888 }
889
890 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
891 {
892 struct iommu_cmd cmd;
893
894 build_inv_dte(&cmd, devid);
895
896 return iommu_queue_command(iommu, &cmd);
897 }
898
899 static void iommu_flush_dte_all(struct amd_iommu *iommu)
900 {
901 u32 devid;
902
903 for (devid = 0; devid <= 0xffff; ++devid)
904 iommu_flush_dte(iommu, devid);
905
906 iommu_completion_wait(iommu);
907 }
908
909 /*
910 * This function uses heavy locking and may disable irqs for some time. But
911 * this is no issue because it is only called during resume.
912 */
913 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
914 {
915 u32 dom_id;
916
917 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
918 struct iommu_cmd cmd;
919 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
920 dom_id, 1);
921 iommu_queue_command(iommu, &cmd);
922 }
923
924 iommu_completion_wait(iommu);
925 }
926
927 static void iommu_flush_all(struct amd_iommu *iommu)
928 {
929 struct iommu_cmd cmd;
930
931 build_inv_all(&cmd);
932
933 iommu_queue_command(iommu, &cmd);
934 iommu_completion_wait(iommu);
935 }
936
937 void iommu_flush_all_caches(struct amd_iommu *iommu)
938 {
939 if (iommu_feature(iommu, FEATURE_IA)) {
940 iommu_flush_all(iommu);
941 } else {
942 iommu_flush_dte_all(iommu);
943 iommu_flush_tlb_all(iommu);
944 }
945 }
946
947 /*
948 * Command send function for flushing on-device TLB
949 */
950 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
951 u64 address, size_t size)
952 {
953 struct amd_iommu *iommu;
954 struct iommu_cmd cmd;
955 int qdep;
956
957 qdep = dev_data->ats.qdep;
958 iommu = amd_iommu_rlookup_table[dev_data->devid];
959
960 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
961
962 return iommu_queue_command(iommu, &cmd);
963 }
964
965 /*
966 * Command send function for invalidating a device table entry
967 */
968 static int device_flush_dte(struct iommu_dev_data *dev_data)
969 {
970 struct amd_iommu *iommu;
971 int ret;
972
973 iommu = amd_iommu_rlookup_table[dev_data->devid];
974
975 ret = iommu_flush_dte(iommu, dev_data->devid);
976 if (ret)
977 return ret;
978
979 if (dev_data->ats.enabled)
980 ret = device_flush_iotlb(dev_data, 0, ~0UL);
981
982 return ret;
983 }
984
985 /*
986 * TLB invalidation function which is called from the mapping functions.
987 * It invalidates a single PTE if the range to flush is within a single
988 * page. Otherwise it flushes the whole TLB of the IOMMU.
989 */
990 static void __domain_flush_pages(struct protection_domain *domain,
991 u64 address, size_t size, int pde)
992 {
993 struct iommu_dev_data *dev_data;
994 struct iommu_cmd cmd;
995 int ret = 0, i;
996
997 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
998
999 for (i = 0; i < amd_iommus_present; ++i) {
1000 if (!domain->dev_iommu[i])
1001 continue;
1002
1003 /*
1004 * Devices of this domain are behind this IOMMU
1005 * We need a TLB flush
1006 */
1007 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1008 }
1009
1010 list_for_each_entry(dev_data, &domain->dev_list, list) {
1011
1012 if (!dev_data->ats.enabled)
1013 continue;
1014
1015 ret |= device_flush_iotlb(dev_data, address, size);
1016 }
1017
1018 WARN_ON(ret);
1019 }
1020
1021 static void domain_flush_pages(struct protection_domain *domain,
1022 u64 address, size_t size)
1023 {
1024 __domain_flush_pages(domain, address, size, 0);
1025 }
1026
1027 /* Flush the whole IO/TLB for a given protection domain */
1028 static void domain_flush_tlb(struct protection_domain *domain)
1029 {
1030 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1031 }
1032
1033 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1034 static void domain_flush_tlb_pde(struct protection_domain *domain)
1035 {
1036 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1037 }
1038
1039 static void domain_flush_complete(struct protection_domain *domain)
1040 {
1041 int i;
1042
1043 for (i = 0; i < amd_iommus_present; ++i) {
1044 if (!domain->dev_iommu[i])
1045 continue;
1046
1047 /*
1048 * Devices of this domain are behind this IOMMU
1049 * We need to wait for completion of all commands.
1050 */
1051 iommu_completion_wait(amd_iommus[i]);
1052 }
1053 }
1054
1055
1056 /*
1057 * This function flushes the DTEs for all devices in domain
1058 */
1059 static void domain_flush_devices(struct protection_domain *domain)
1060 {
1061 struct iommu_dev_data *dev_data;
1062
1063 list_for_each_entry(dev_data, &domain->dev_list, list)
1064 device_flush_dte(dev_data);
1065 }
1066
1067 /****************************************************************************
1068 *
1069 * The functions below are used the create the page table mappings for
1070 * unity mapped regions.
1071 *
1072 ****************************************************************************/
1073
1074 /*
1075 * This function is used to add another level to an IO page table. Adding
1076 * another level increases the size of the address space by 9 bits to a size up
1077 * to 64 bits.
1078 */
1079 static bool increase_address_space(struct protection_domain *domain,
1080 gfp_t gfp)
1081 {
1082 u64 *pte;
1083
1084 if (domain->mode == PAGE_MODE_6_LEVEL)
1085 /* address space already 64 bit large */
1086 return false;
1087
1088 pte = (void *)get_zeroed_page(gfp);
1089 if (!pte)
1090 return false;
1091
1092 *pte = PM_LEVEL_PDE(domain->mode,
1093 virt_to_phys(domain->pt_root));
1094 domain->pt_root = pte;
1095 domain->mode += 1;
1096 domain->updated = true;
1097
1098 return true;
1099 }
1100
1101 static u64 *alloc_pte(struct protection_domain *domain,
1102 unsigned long address,
1103 unsigned long page_size,
1104 u64 **pte_page,
1105 gfp_t gfp)
1106 {
1107 int level, end_lvl;
1108 u64 *pte, *page;
1109
1110 BUG_ON(!is_power_of_2(page_size));
1111
1112 while (address > PM_LEVEL_SIZE(domain->mode))
1113 increase_address_space(domain, gfp);
1114
1115 level = domain->mode - 1;
1116 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1117 address = PAGE_SIZE_ALIGN(address, page_size);
1118 end_lvl = PAGE_SIZE_LEVEL(page_size);
1119
1120 while (level > end_lvl) {
1121 if (!IOMMU_PTE_PRESENT(*pte)) {
1122 page = (u64 *)get_zeroed_page(gfp);
1123 if (!page)
1124 return NULL;
1125 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1126 }
1127
1128 /* No level skipping support yet */
1129 if (PM_PTE_LEVEL(*pte) != level)
1130 return NULL;
1131
1132 level -= 1;
1133
1134 pte = IOMMU_PTE_PAGE(*pte);
1135
1136 if (pte_page && level == end_lvl)
1137 *pte_page = pte;
1138
1139 pte = &pte[PM_LEVEL_INDEX(level, address)];
1140 }
1141
1142 return pte;
1143 }
1144
1145 /*
1146 * This function checks if there is a PTE for a given dma address. If
1147 * there is one, it returns the pointer to it.
1148 */
1149 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
1150 {
1151 int level;
1152 u64 *pte;
1153
1154 if (address > PM_LEVEL_SIZE(domain->mode))
1155 return NULL;
1156
1157 level = domain->mode - 1;
1158 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1159
1160 while (level > 0) {
1161
1162 /* Not Present */
1163 if (!IOMMU_PTE_PRESENT(*pte))
1164 return NULL;
1165
1166 /* Large PTE */
1167 if (PM_PTE_LEVEL(*pte) == 0x07) {
1168 unsigned long pte_mask, __pte;
1169
1170 /*
1171 * If we have a series of large PTEs, make
1172 * sure to return a pointer to the first one.
1173 */
1174 pte_mask = PTE_PAGE_SIZE(*pte);
1175 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1176 __pte = ((unsigned long)pte) & pte_mask;
1177
1178 return (u64 *)__pte;
1179 }
1180
1181 /* No level skipping support yet */
1182 if (PM_PTE_LEVEL(*pte) != level)
1183 return NULL;
1184
1185 level -= 1;
1186
1187 /* Walk to the next level */
1188 pte = IOMMU_PTE_PAGE(*pte);
1189 pte = &pte[PM_LEVEL_INDEX(level, address)];
1190 }
1191
1192 return pte;
1193 }
1194
1195 /*
1196 * Generic mapping functions. It maps a physical address into a DMA
1197 * address space. It allocates the page table pages if necessary.
1198 * In the future it can be extended to a generic mapping function
1199 * supporting all features of AMD IOMMU page tables like level skipping
1200 * and full 64 bit address spaces.
1201 */
1202 static int iommu_map_page(struct protection_domain *dom,
1203 unsigned long bus_addr,
1204 unsigned long phys_addr,
1205 int prot,
1206 unsigned long page_size)
1207 {
1208 u64 __pte, *pte;
1209 int i, count;
1210
1211 if (!(prot & IOMMU_PROT_MASK))
1212 return -EINVAL;
1213
1214 bus_addr = PAGE_ALIGN(bus_addr);
1215 phys_addr = PAGE_ALIGN(phys_addr);
1216 count = PAGE_SIZE_PTE_COUNT(page_size);
1217 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1218
1219 for (i = 0; i < count; ++i)
1220 if (IOMMU_PTE_PRESENT(pte[i]))
1221 return -EBUSY;
1222
1223 if (page_size > PAGE_SIZE) {
1224 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1225 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1226 } else
1227 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1228
1229 if (prot & IOMMU_PROT_IR)
1230 __pte |= IOMMU_PTE_IR;
1231 if (prot & IOMMU_PROT_IW)
1232 __pte |= IOMMU_PTE_IW;
1233
1234 for (i = 0; i < count; ++i)
1235 pte[i] = __pte;
1236
1237 update_domain(dom);
1238
1239 return 0;
1240 }
1241
1242 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1243 unsigned long bus_addr,
1244 unsigned long page_size)
1245 {
1246 unsigned long long unmap_size, unmapped;
1247 u64 *pte;
1248
1249 BUG_ON(!is_power_of_2(page_size));
1250
1251 unmapped = 0;
1252
1253 while (unmapped < page_size) {
1254
1255 pte = fetch_pte(dom, bus_addr);
1256
1257 if (!pte) {
1258 /*
1259 * No PTE for this address
1260 * move forward in 4kb steps
1261 */
1262 unmap_size = PAGE_SIZE;
1263 } else if (PM_PTE_LEVEL(*pte) == 0) {
1264 /* 4kb PTE found for this address */
1265 unmap_size = PAGE_SIZE;
1266 *pte = 0ULL;
1267 } else {
1268 int count, i;
1269
1270 /* Large PTE found which maps this address */
1271 unmap_size = PTE_PAGE_SIZE(*pte);
1272 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1273 for (i = 0; i < count; i++)
1274 pte[i] = 0ULL;
1275 }
1276
1277 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1278 unmapped += unmap_size;
1279 }
1280
1281 BUG_ON(!is_power_of_2(unmapped));
1282
1283 return unmapped;
1284 }
1285
1286 /*
1287 * This function checks if a specific unity mapping entry is needed for
1288 * this specific IOMMU.
1289 */
1290 static int iommu_for_unity_map(struct amd_iommu *iommu,
1291 struct unity_map_entry *entry)
1292 {
1293 u16 bdf, i;
1294
1295 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1296 bdf = amd_iommu_alias_table[i];
1297 if (amd_iommu_rlookup_table[bdf] == iommu)
1298 return 1;
1299 }
1300
1301 return 0;
1302 }
1303
1304 /*
1305 * This function actually applies the mapping to the page table of the
1306 * dma_ops domain.
1307 */
1308 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1309 struct unity_map_entry *e)
1310 {
1311 u64 addr;
1312 int ret;
1313
1314 for (addr = e->address_start; addr < e->address_end;
1315 addr += PAGE_SIZE) {
1316 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1317 PAGE_SIZE);
1318 if (ret)
1319 return ret;
1320 /*
1321 * if unity mapping is in aperture range mark the page
1322 * as allocated in the aperture
1323 */
1324 if (addr < dma_dom->aperture_size)
1325 __set_bit(addr >> PAGE_SHIFT,
1326 dma_dom->aperture[0]->bitmap);
1327 }
1328
1329 return 0;
1330 }
1331
1332 /*
1333 * Init the unity mappings for a specific IOMMU in the system
1334 *
1335 * Basically iterates over all unity mapping entries and applies them to
1336 * the default domain DMA of that IOMMU if necessary.
1337 */
1338 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1339 {
1340 struct unity_map_entry *entry;
1341 int ret;
1342
1343 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1344 if (!iommu_for_unity_map(iommu, entry))
1345 continue;
1346 ret = dma_ops_unity_map(iommu->default_dom, entry);
1347 if (ret)
1348 return ret;
1349 }
1350
1351 return 0;
1352 }
1353
1354 /*
1355 * Inits the unity mappings required for a specific device
1356 */
1357 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1358 u16 devid)
1359 {
1360 struct unity_map_entry *e;
1361 int ret;
1362
1363 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1364 if (!(devid >= e->devid_start && devid <= e->devid_end))
1365 continue;
1366 ret = dma_ops_unity_map(dma_dom, e);
1367 if (ret)
1368 return ret;
1369 }
1370
1371 return 0;
1372 }
1373
1374 /****************************************************************************
1375 *
1376 * The next functions belong to the address allocator for the dma_ops
1377 * interface functions. They work like the allocators in the other IOMMU
1378 * drivers. Its basically a bitmap which marks the allocated pages in
1379 * the aperture. Maybe it could be enhanced in the future to a more
1380 * efficient allocator.
1381 *
1382 ****************************************************************************/
1383
1384 /*
1385 * The address allocator core functions.
1386 *
1387 * called with domain->lock held
1388 */
1389
1390 /*
1391 * Used to reserve address ranges in the aperture (e.g. for exclusion
1392 * ranges.
1393 */
1394 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1395 unsigned long start_page,
1396 unsigned int pages)
1397 {
1398 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1399
1400 if (start_page + pages > last_page)
1401 pages = last_page - start_page;
1402
1403 for (i = start_page; i < start_page + pages; ++i) {
1404 int index = i / APERTURE_RANGE_PAGES;
1405 int page = i % APERTURE_RANGE_PAGES;
1406 __set_bit(page, dom->aperture[index]->bitmap);
1407 }
1408 }
1409
1410 /*
1411 * This function is used to add a new aperture range to an existing
1412 * aperture in case of dma_ops domain allocation or address allocation
1413 * failure.
1414 */
1415 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1416 bool populate, gfp_t gfp)
1417 {
1418 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1419 struct amd_iommu *iommu;
1420 unsigned long i, old_size;
1421
1422 #ifdef CONFIG_IOMMU_STRESS
1423 populate = false;
1424 #endif
1425
1426 if (index >= APERTURE_MAX_RANGES)
1427 return -ENOMEM;
1428
1429 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1430 if (!dma_dom->aperture[index])
1431 return -ENOMEM;
1432
1433 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1434 if (!dma_dom->aperture[index]->bitmap)
1435 goto out_free;
1436
1437 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1438
1439 if (populate) {
1440 unsigned long address = dma_dom->aperture_size;
1441 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1442 u64 *pte, *pte_page;
1443
1444 for (i = 0; i < num_ptes; ++i) {
1445 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1446 &pte_page, gfp);
1447 if (!pte)
1448 goto out_free;
1449
1450 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1451
1452 address += APERTURE_RANGE_SIZE / 64;
1453 }
1454 }
1455
1456 old_size = dma_dom->aperture_size;
1457 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1458
1459 /* Reserve address range used for MSI messages */
1460 if (old_size < MSI_ADDR_BASE_LO &&
1461 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1462 unsigned long spage;
1463 int pages;
1464
1465 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1466 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1467
1468 dma_ops_reserve_addresses(dma_dom, spage, pages);
1469 }
1470
1471 /* Initialize the exclusion range if necessary */
1472 for_each_iommu(iommu) {
1473 if (iommu->exclusion_start &&
1474 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1475 && iommu->exclusion_start < dma_dom->aperture_size) {
1476 unsigned long startpage;
1477 int pages = iommu_num_pages(iommu->exclusion_start,
1478 iommu->exclusion_length,
1479 PAGE_SIZE);
1480 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1481 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1482 }
1483 }
1484
1485 /*
1486 * Check for areas already mapped as present in the new aperture
1487 * range and mark those pages as reserved in the allocator. Such
1488 * mappings may already exist as a result of requested unity
1489 * mappings for devices.
1490 */
1491 for (i = dma_dom->aperture[index]->offset;
1492 i < dma_dom->aperture_size;
1493 i += PAGE_SIZE) {
1494 u64 *pte = fetch_pte(&dma_dom->domain, i);
1495 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1496 continue;
1497
1498 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1499 }
1500
1501 update_domain(&dma_dom->domain);
1502
1503 return 0;
1504
1505 out_free:
1506 update_domain(&dma_dom->domain);
1507
1508 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1509
1510 kfree(dma_dom->aperture[index]);
1511 dma_dom->aperture[index] = NULL;
1512
1513 return -ENOMEM;
1514 }
1515
1516 static unsigned long dma_ops_area_alloc(struct device *dev,
1517 struct dma_ops_domain *dom,
1518 unsigned int pages,
1519 unsigned long align_mask,
1520 u64 dma_mask,
1521 unsigned long start)
1522 {
1523 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1524 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1525 int i = start >> APERTURE_RANGE_SHIFT;
1526 unsigned long boundary_size;
1527 unsigned long address = -1;
1528 unsigned long limit;
1529
1530 next_bit >>= PAGE_SHIFT;
1531
1532 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1533 PAGE_SIZE) >> PAGE_SHIFT;
1534
1535 for (;i < max_index; ++i) {
1536 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1537
1538 if (dom->aperture[i]->offset >= dma_mask)
1539 break;
1540
1541 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1542 dma_mask >> PAGE_SHIFT);
1543
1544 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1545 limit, next_bit, pages, 0,
1546 boundary_size, align_mask);
1547 if (address != -1) {
1548 address = dom->aperture[i]->offset +
1549 (address << PAGE_SHIFT);
1550 dom->next_address = address + (pages << PAGE_SHIFT);
1551 break;
1552 }
1553
1554 next_bit = 0;
1555 }
1556
1557 return address;
1558 }
1559
1560 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1561 struct dma_ops_domain *dom,
1562 unsigned int pages,
1563 unsigned long align_mask,
1564 u64 dma_mask)
1565 {
1566 unsigned long address;
1567
1568 #ifdef CONFIG_IOMMU_STRESS
1569 dom->next_address = 0;
1570 dom->need_flush = true;
1571 #endif
1572
1573 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1574 dma_mask, dom->next_address);
1575
1576 if (address == -1) {
1577 dom->next_address = 0;
1578 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1579 dma_mask, 0);
1580 dom->need_flush = true;
1581 }
1582
1583 if (unlikely(address == -1))
1584 address = DMA_ERROR_CODE;
1585
1586 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1587
1588 return address;
1589 }
1590
1591 /*
1592 * The address free function.
1593 *
1594 * called with domain->lock held
1595 */
1596 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1597 unsigned long address,
1598 unsigned int pages)
1599 {
1600 unsigned i = address >> APERTURE_RANGE_SHIFT;
1601 struct aperture_range *range = dom->aperture[i];
1602
1603 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1604
1605 #ifdef CONFIG_IOMMU_STRESS
1606 if (i < 4)
1607 return;
1608 #endif
1609
1610 if (address >= dom->next_address)
1611 dom->need_flush = true;
1612
1613 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1614
1615 bitmap_clear(range->bitmap, address, pages);
1616
1617 }
1618
1619 /****************************************************************************
1620 *
1621 * The next functions belong to the domain allocation. A domain is
1622 * allocated for every IOMMU as the default domain. If device isolation
1623 * is enabled, every device get its own domain. The most important thing
1624 * about domains is the page table mapping the DMA address space they
1625 * contain.
1626 *
1627 ****************************************************************************/
1628
1629 /*
1630 * This function adds a protection domain to the global protection domain list
1631 */
1632 static void add_domain_to_list(struct protection_domain *domain)
1633 {
1634 unsigned long flags;
1635
1636 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1637 list_add(&domain->list, &amd_iommu_pd_list);
1638 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1639 }
1640
1641 /*
1642 * This function removes a protection domain to the global
1643 * protection domain list
1644 */
1645 static void del_domain_from_list(struct protection_domain *domain)
1646 {
1647 unsigned long flags;
1648
1649 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1650 list_del(&domain->list);
1651 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1652 }
1653
1654 static u16 domain_id_alloc(void)
1655 {
1656 unsigned long flags;
1657 int id;
1658
1659 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1660 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1661 BUG_ON(id == 0);
1662 if (id > 0 && id < MAX_DOMAIN_ID)
1663 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1664 else
1665 id = 0;
1666 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1667
1668 return id;
1669 }
1670
1671 static void domain_id_free(int id)
1672 {
1673 unsigned long flags;
1674
1675 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1676 if (id > 0 && id < MAX_DOMAIN_ID)
1677 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1678 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1679 }
1680
1681 static void free_pagetable(struct protection_domain *domain)
1682 {
1683 int i, j;
1684 u64 *p1, *p2, *p3;
1685
1686 p1 = domain->pt_root;
1687
1688 if (!p1)
1689 return;
1690
1691 for (i = 0; i < 512; ++i) {
1692 if (!IOMMU_PTE_PRESENT(p1[i]))
1693 continue;
1694
1695 p2 = IOMMU_PTE_PAGE(p1[i]);
1696 for (j = 0; j < 512; ++j) {
1697 if (!IOMMU_PTE_PRESENT(p2[j]))
1698 continue;
1699 p3 = IOMMU_PTE_PAGE(p2[j]);
1700 free_page((unsigned long)p3);
1701 }
1702
1703 free_page((unsigned long)p2);
1704 }
1705
1706 free_page((unsigned long)p1);
1707
1708 domain->pt_root = NULL;
1709 }
1710
1711 static void free_gcr3_tbl_level1(u64 *tbl)
1712 {
1713 u64 *ptr;
1714 int i;
1715
1716 for (i = 0; i < 512; ++i) {
1717 if (!(tbl[i] & GCR3_VALID))
1718 continue;
1719
1720 ptr = __va(tbl[i] & PAGE_MASK);
1721
1722 free_page((unsigned long)ptr);
1723 }
1724 }
1725
1726 static void free_gcr3_tbl_level2(u64 *tbl)
1727 {
1728 u64 *ptr;
1729 int i;
1730
1731 for (i = 0; i < 512; ++i) {
1732 if (!(tbl[i] & GCR3_VALID))
1733 continue;
1734
1735 ptr = __va(tbl[i] & PAGE_MASK);
1736
1737 free_gcr3_tbl_level1(ptr);
1738 }
1739 }
1740
1741 static void free_gcr3_table(struct protection_domain *domain)
1742 {
1743 if (domain->glx == 2)
1744 free_gcr3_tbl_level2(domain->gcr3_tbl);
1745 else if (domain->glx == 1)
1746 free_gcr3_tbl_level1(domain->gcr3_tbl);
1747 else if (domain->glx != 0)
1748 BUG();
1749
1750 free_page((unsigned long)domain->gcr3_tbl);
1751 }
1752
1753 /*
1754 * Free a domain, only used if something went wrong in the
1755 * allocation path and we need to free an already allocated page table
1756 */
1757 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1758 {
1759 int i;
1760
1761 if (!dom)
1762 return;
1763
1764 del_domain_from_list(&dom->domain);
1765
1766 free_pagetable(&dom->domain);
1767
1768 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1769 if (!dom->aperture[i])
1770 continue;
1771 free_page((unsigned long)dom->aperture[i]->bitmap);
1772 kfree(dom->aperture[i]);
1773 }
1774
1775 kfree(dom);
1776 }
1777
1778 /*
1779 * Allocates a new protection domain usable for the dma_ops functions.
1780 * It also initializes the page table and the address allocator data
1781 * structures required for the dma_ops interface
1782 */
1783 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1784 {
1785 struct dma_ops_domain *dma_dom;
1786
1787 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1788 if (!dma_dom)
1789 return NULL;
1790
1791 spin_lock_init(&dma_dom->domain.lock);
1792
1793 dma_dom->domain.id = domain_id_alloc();
1794 if (dma_dom->domain.id == 0)
1795 goto free_dma_dom;
1796 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1797 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1798 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1799 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1800 dma_dom->domain.priv = dma_dom;
1801 if (!dma_dom->domain.pt_root)
1802 goto free_dma_dom;
1803
1804 dma_dom->need_flush = false;
1805 dma_dom->target_dev = 0xffff;
1806
1807 add_domain_to_list(&dma_dom->domain);
1808
1809 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1810 goto free_dma_dom;
1811
1812 /*
1813 * mark the first page as allocated so we never return 0 as
1814 * a valid dma-address. So we can use 0 as error value
1815 */
1816 dma_dom->aperture[0]->bitmap[0] = 1;
1817 dma_dom->next_address = 0;
1818
1819
1820 return dma_dom;
1821
1822 free_dma_dom:
1823 dma_ops_domain_free(dma_dom);
1824
1825 return NULL;
1826 }
1827
1828 /*
1829 * little helper function to check whether a given protection domain is a
1830 * dma_ops domain
1831 */
1832 static bool dma_ops_domain(struct protection_domain *domain)
1833 {
1834 return domain->flags & PD_DMA_OPS_MASK;
1835 }
1836
1837 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1838 {
1839 u64 pte_root = 0;
1840 u64 flags = 0;
1841
1842 if (domain->mode != PAGE_MODE_NONE)
1843 pte_root = virt_to_phys(domain->pt_root);
1844
1845 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1846 << DEV_ENTRY_MODE_SHIFT;
1847 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1848
1849 flags = amd_iommu_dev_table[devid].data[1];
1850
1851 if (ats)
1852 flags |= DTE_FLAG_IOTLB;
1853
1854 if (domain->flags & PD_IOMMUV2_MASK) {
1855 u64 gcr3 = __pa(domain->gcr3_tbl);
1856 u64 glx = domain->glx;
1857 u64 tmp;
1858
1859 pte_root |= DTE_FLAG_GV;
1860 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1861
1862 /* First mask out possible old values for GCR3 table */
1863 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1864 flags &= ~tmp;
1865
1866 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1867 flags &= ~tmp;
1868
1869 /* Encode GCR3 table into DTE */
1870 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1871 pte_root |= tmp;
1872
1873 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1874 flags |= tmp;
1875
1876 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1877 flags |= tmp;
1878 }
1879
1880 flags &= ~(0xffffUL);
1881 flags |= domain->id;
1882
1883 amd_iommu_dev_table[devid].data[1] = flags;
1884 amd_iommu_dev_table[devid].data[0] = pte_root;
1885 }
1886
1887 static void clear_dte_entry(u16 devid)
1888 {
1889 /* remove entry from the device table seen by the hardware */
1890 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1891 amd_iommu_dev_table[devid].data[1] = 0;
1892
1893 amd_iommu_apply_erratum_63(devid);
1894 }
1895
1896 static void do_attach(struct iommu_dev_data *dev_data,
1897 struct protection_domain *domain)
1898 {
1899 struct amd_iommu *iommu;
1900 bool ats;
1901
1902 iommu = amd_iommu_rlookup_table[dev_data->devid];
1903 ats = dev_data->ats.enabled;
1904
1905 /* Update data structures */
1906 dev_data->domain = domain;
1907 list_add(&dev_data->list, &domain->dev_list);
1908 set_dte_entry(dev_data->devid, domain, ats);
1909
1910 /* Do reference counting */
1911 domain->dev_iommu[iommu->index] += 1;
1912 domain->dev_cnt += 1;
1913
1914 /* Flush the DTE entry */
1915 device_flush_dte(dev_data);
1916 }
1917
1918 static void do_detach(struct iommu_dev_data *dev_data)
1919 {
1920 struct amd_iommu *iommu;
1921
1922 iommu = amd_iommu_rlookup_table[dev_data->devid];
1923
1924 /* decrease reference counters */
1925 dev_data->domain->dev_iommu[iommu->index] -= 1;
1926 dev_data->domain->dev_cnt -= 1;
1927
1928 /* Update data structures */
1929 dev_data->domain = NULL;
1930 list_del(&dev_data->list);
1931 clear_dte_entry(dev_data->devid);
1932
1933 /* Flush the DTE entry */
1934 device_flush_dte(dev_data);
1935 }
1936
1937 /*
1938 * If a device is not yet associated with a domain, this function does
1939 * assigns it visible for the hardware
1940 */
1941 static int __attach_device(struct iommu_dev_data *dev_data,
1942 struct protection_domain *domain)
1943 {
1944 int ret;
1945
1946 /* lock domain */
1947 spin_lock(&domain->lock);
1948
1949 if (dev_data->alias_data != NULL) {
1950 struct iommu_dev_data *alias_data = dev_data->alias_data;
1951
1952 /* Some sanity checks */
1953 ret = -EBUSY;
1954 if (alias_data->domain != NULL &&
1955 alias_data->domain != domain)
1956 goto out_unlock;
1957
1958 if (dev_data->domain != NULL &&
1959 dev_data->domain != domain)
1960 goto out_unlock;
1961
1962 /* Do real assignment */
1963 if (alias_data->domain == NULL)
1964 do_attach(alias_data, domain);
1965
1966 atomic_inc(&alias_data->bind);
1967 }
1968
1969 if (dev_data->domain == NULL)
1970 do_attach(dev_data, domain);
1971
1972 atomic_inc(&dev_data->bind);
1973
1974 ret = 0;
1975
1976 out_unlock:
1977
1978 /* ready */
1979 spin_unlock(&domain->lock);
1980
1981 return ret;
1982 }
1983
1984
1985 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1986 {
1987 pci_disable_ats(pdev);
1988 pci_disable_pri(pdev);
1989 pci_disable_pasid(pdev);
1990 }
1991
1992 /* FIXME: Change generic reset-function to do the same */
1993 static int pri_reset_while_enabled(struct pci_dev *pdev)
1994 {
1995 u16 control;
1996 int pos;
1997
1998 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1999 if (!pos)
2000 return -EINVAL;
2001
2002 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2003 control |= PCI_PRI_CTRL_RESET;
2004 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2005
2006 return 0;
2007 }
2008
2009 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2010 {
2011 bool reset_enable;
2012 int reqs, ret;
2013
2014 /* FIXME: Hardcode number of outstanding requests for now */
2015 reqs = 32;
2016 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2017 reqs = 1;
2018 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2019
2020 /* Only allow access to user-accessible pages */
2021 ret = pci_enable_pasid(pdev, 0);
2022 if (ret)
2023 goto out_err;
2024
2025 /* First reset the PRI state of the device */
2026 ret = pci_reset_pri(pdev);
2027 if (ret)
2028 goto out_err;
2029
2030 /* Enable PRI */
2031 ret = pci_enable_pri(pdev, reqs);
2032 if (ret)
2033 goto out_err;
2034
2035 if (reset_enable) {
2036 ret = pri_reset_while_enabled(pdev);
2037 if (ret)
2038 goto out_err;
2039 }
2040
2041 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2042 if (ret)
2043 goto out_err;
2044
2045 return 0;
2046
2047 out_err:
2048 pci_disable_pri(pdev);
2049 pci_disable_pasid(pdev);
2050
2051 return ret;
2052 }
2053
2054 /* FIXME: Move this to PCI code */
2055 #define PCI_PRI_TLP_OFF (1 << 15)
2056
2057 bool pci_pri_tlp_required(struct pci_dev *pdev)
2058 {
2059 u16 status;
2060 int pos;
2061
2062 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2063 if (!pos)
2064 return false;
2065
2066 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2067
2068 return (status & PCI_PRI_TLP_OFF) ? true : false;
2069 }
2070
2071 /*
2072 * If a device is not yet associated with a domain, this function does
2073 * assigns it visible for the hardware
2074 */
2075 static int attach_device(struct device *dev,
2076 struct protection_domain *domain)
2077 {
2078 struct pci_dev *pdev = to_pci_dev(dev);
2079 struct iommu_dev_data *dev_data;
2080 unsigned long flags;
2081 int ret;
2082
2083 dev_data = get_dev_data(dev);
2084
2085 if (domain->flags & PD_IOMMUV2_MASK) {
2086 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2087 return -EINVAL;
2088
2089 if (pdev_iommuv2_enable(pdev) != 0)
2090 return -EINVAL;
2091
2092 dev_data->ats.enabled = true;
2093 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2094 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2095 } else if (amd_iommu_iotlb_sup &&
2096 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2097 dev_data->ats.enabled = true;
2098 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2099 }
2100
2101 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2102 ret = __attach_device(dev_data, domain);
2103 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2104
2105 /*
2106 * We might boot into a crash-kernel here. The crashed kernel
2107 * left the caches in the IOMMU dirty. So we have to flush
2108 * here to evict all dirty stuff.
2109 */
2110 domain_flush_tlb_pde(domain);
2111
2112 return ret;
2113 }
2114
2115 /*
2116 * Removes a device from a protection domain (unlocked)
2117 */
2118 static void __detach_device(struct iommu_dev_data *dev_data)
2119 {
2120 struct protection_domain *domain;
2121 unsigned long flags;
2122
2123 BUG_ON(!dev_data->domain);
2124
2125 domain = dev_data->domain;
2126
2127 spin_lock_irqsave(&domain->lock, flags);
2128
2129 if (dev_data->alias_data != NULL) {
2130 struct iommu_dev_data *alias_data = dev_data->alias_data;
2131
2132 if (atomic_dec_and_test(&alias_data->bind))
2133 do_detach(alias_data);
2134 }
2135
2136 if (atomic_dec_and_test(&dev_data->bind))
2137 do_detach(dev_data);
2138
2139 spin_unlock_irqrestore(&domain->lock, flags);
2140
2141 /*
2142 * If we run in passthrough mode the device must be assigned to the
2143 * passthrough domain if it is detached from any other domain.
2144 * Make sure we can deassign from the pt_domain itself.
2145 */
2146 if (dev_data->passthrough &&
2147 (dev_data->domain == NULL && domain != pt_domain))
2148 __attach_device(dev_data, pt_domain);
2149 }
2150
2151 /*
2152 * Removes a device from a protection domain (with devtable_lock held)
2153 */
2154 static void detach_device(struct device *dev)
2155 {
2156 struct protection_domain *domain;
2157 struct iommu_dev_data *dev_data;
2158 unsigned long flags;
2159
2160 dev_data = get_dev_data(dev);
2161 domain = dev_data->domain;
2162
2163 /* lock device table */
2164 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2165 __detach_device(dev_data);
2166 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2167
2168 if (domain->flags & PD_IOMMUV2_MASK)
2169 pdev_iommuv2_disable(to_pci_dev(dev));
2170 else if (dev_data->ats.enabled)
2171 pci_disable_ats(to_pci_dev(dev));
2172
2173 dev_data->ats.enabled = false;
2174 }
2175
2176 /*
2177 * Find out the protection domain structure for a given PCI device. This
2178 * will give us the pointer to the page table root for example.
2179 */
2180 static struct protection_domain *domain_for_device(struct device *dev)
2181 {
2182 struct iommu_dev_data *dev_data;
2183 struct protection_domain *dom = NULL;
2184 unsigned long flags;
2185
2186 dev_data = get_dev_data(dev);
2187
2188 if (dev_data->domain)
2189 return dev_data->domain;
2190
2191 if (dev_data->alias_data != NULL) {
2192 struct iommu_dev_data *alias_data = dev_data->alias_data;
2193
2194 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2195 if (alias_data->domain != NULL) {
2196 __attach_device(dev_data, alias_data->domain);
2197 dom = alias_data->domain;
2198 }
2199 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2200 }
2201
2202 return dom;
2203 }
2204
2205 static int device_change_notifier(struct notifier_block *nb,
2206 unsigned long action, void *data)
2207 {
2208 struct dma_ops_domain *dma_domain;
2209 struct protection_domain *domain;
2210 struct iommu_dev_data *dev_data;
2211 struct device *dev = data;
2212 struct amd_iommu *iommu;
2213 unsigned long flags;
2214 u16 devid;
2215
2216 if (!check_device(dev))
2217 return 0;
2218
2219 devid = get_device_id(dev);
2220 iommu = amd_iommu_rlookup_table[devid];
2221 dev_data = get_dev_data(dev);
2222
2223 switch (action) {
2224 case BUS_NOTIFY_UNBOUND_DRIVER:
2225
2226 domain = domain_for_device(dev);
2227
2228 if (!domain)
2229 goto out;
2230 if (dev_data->passthrough)
2231 break;
2232 detach_device(dev);
2233 break;
2234 case BUS_NOTIFY_ADD_DEVICE:
2235
2236 iommu_init_device(dev);
2237
2238 domain = domain_for_device(dev);
2239
2240 /* allocate a protection domain if a device is added */
2241 dma_domain = find_protection_domain(devid);
2242 if (dma_domain)
2243 goto out;
2244 dma_domain = dma_ops_domain_alloc();
2245 if (!dma_domain)
2246 goto out;
2247 dma_domain->target_dev = devid;
2248
2249 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2250 list_add_tail(&dma_domain->list, &iommu_pd_list);
2251 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2252
2253 break;
2254 case BUS_NOTIFY_DEL_DEVICE:
2255
2256 iommu_uninit_device(dev);
2257
2258 default:
2259 goto out;
2260 }
2261
2262 iommu_completion_wait(iommu);
2263
2264 out:
2265 return 0;
2266 }
2267
2268 static struct notifier_block device_nb = {
2269 .notifier_call = device_change_notifier,
2270 };
2271
2272 void amd_iommu_init_notifier(void)
2273 {
2274 bus_register_notifier(&pci_bus_type, &device_nb);
2275 }
2276
2277 /*****************************************************************************
2278 *
2279 * The next functions belong to the dma_ops mapping/unmapping code.
2280 *
2281 *****************************************************************************/
2282
2283 /*
2284 * In the dma_ops path we only have the struct device. This function
2285 * finds the corresponding IOMMU, the protection domain and the
2286 * requestor id for a given device.
2287 * If the device is not yet associated with a domain this is also done
2288 * in this function.
2289 */
2290 static struct protection_domain *get_domain(struct device *dev)
2291 {
2292 struct protection_domain *domain;
2293 struct dma_ops_domain *dma_dom;
2294 u16 devid = get_device_id(dev);
2295
2296 if (!check_device(dev))
2297 return ERR_PTR(-EINVAL);
2298
2299 domain = domain_for_device(dev);
2300 if (domain != NULL && !dma_ops_domain(domain))
2301 return ERR_PTR(-EBUSY);
2302
2303 if (domain != NULL)
2304 return domain;
2305
2306 /* Device not bount yet - bind it */
2307 dma_dom = find_protection_domain(devid);
2308 if (!dma_dom)
2309 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2310 attach_device(dev, &dma_dom->domain);
2311 DUMP_printk("Using protection domain %d for device %s\n",
2312 dma_dom->domain.id, dev_name(dev));
2313
2314 return &dma_dom->domain;
2315 }
2316
2317 static void update_device_table(struct protection_domain *domain)
2318 {
2319 struct iommu_dev_data *dev_data;
2320
2321 list_for_each_entry(dev_data, &domain->dev_list, list)
2322 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2323 }
2324
2325 static void update_domain(struct protection_domain *domain)
2326 {
2327 if (!domain->updated)
2328 return;
2329
2330 update_device_table(domain);
2331
2332 domain_flush_devices(domain);
2333 domain_flush_tlb_pde(domain);
2334
2335 domain->updated = false;
2336 }
2337
2338 /*
2339 * This function fetches the PTE for a given address in the aperture
2340 */
2341 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2342 unsigned long address)
2343 {
2344 struct aperture_range *aperture;
2345 u64 *pte, *pte_page;
2346
2347 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2348 if (!aperture)
2349 return NULL;
2350
2351 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2352 if (!pte) {
2353 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2354 GFP_ATOMIC);
2355 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2356 } else
2357 pte += PM_LEVEL_INDEX(0, address);
2358
2359 update_domain(&dom->domain);
2360
2361 return pte;
2362 }
2363
2364 /*
2365 * This is the generic map function. It maps one 4kb page at paddr to
2366 * the given address in the DMA address space for the domain.
2367 */
2368 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2369 unsigned long address,
2370 phys_addr_t paddr,
2371 int direction)
2372 {
2373 u64 *pte, __pte;
2374
2375 WARN_ON(address > dom->aperture_size);
2376
2377 paddr &= PAGE_MASK;
2378
2379 pte = dma_ops_get_pte(dom, address);
2380 if (!pte)
2381 return DMA_ERROR_CODE;
2382
2383 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2384
2385 if (direction == DMA_TO_DEVICE)
2386 __pte |= IOMMU_PTE_IR;
2387 else if (direction == DMA_FROM_DEVICE)
2388 __pte |= IOMMU_PTE_IW;
2389 else if (direction == DMA_BIDIRECTIONAL)
2390 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2391
2392 WARN_ON(*pte);
2393
2394 *pte = __pte;
2395
2396 return (dma_addr_t)address;
2397 }
2398
2399 /*
2400 * The generic unmapping function for on page in the DMA address space.
2401 */
2402 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2403 unsigned long address)
2404 {
2405 struct aperture_range *aperture;
2406 u64 *pte;
2407
2408 if (address >= dom->aperture_size)
2409 return;
2410
2411 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2412 if (!aperture)
2413 return;
2414
2415 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2416 if (!pte)
2417 return;
2418
2419 pte += PM_LEVEL_INDEX(0, address);
2420
2421 WARN_ON(!*pte);
2422
2423 *pte = 0ULL;
2424 }
2425
2426 /*
2427 * This function contains common code for mapping of a physically
2428 * contiguous memory region into DMA address space. It is used by all
2429 * mapping functions provided with this IOMMU driver.
2430 * Must be called with the domain lock held.
2431 */
2432 static dma_addr_t __map_single(struct device *dev,
2433 struct dma_ops_domain *dma_dom,
2434 phys_addr_t paddr,
2435 size_t size,
2436 int dir,
2437 bool align,
2438 u64 dma_mask)
2439 {
2440 dma_addr_t offset = paddr & ~PAGE_MASK;
2441 dma_addr_t address, start, ret;
2442 unsigned int pages;
2443 unsigned long align_mask = 0;
2444 int i;
2445
2446 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2447 paddr &= PAGE_MASK;
2448
2449 INC_STATS_COUNTER(total_map_requests);
2450
2451 if (pages > 1)
2452 INC_STATS_COUNTER(cross_page);
2453
2454 if (align)
2455 align_mask = (1UL << get_order(size)) - 1;
2456
2457 retry:
2458 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2459 dma_mask);
2460 if (unlikely(address == DMA_ERROR_CODE)) {
2461 /*
2462 * setting next_address here will let the address
2463 * allocator only scan the new allocated range in the
2464 * first run. This is a small optimization.
2465 */
2466 dma_dom->next_address = dma_dom->aperture_size;
2467
2468 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2469 goto out;
2470
2471 /*
2472 * aperture was successfully enlarged by 128 MB, try
2473 * allocation again
2474 */
2475 goto retry;
2476 }
2477
2478 start = address;
2479 for (i = 0; i < pages; ++i) {
2480 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2481 if (ret == DMA_ERROR_CODE)
2482 goto out_unmap;
2483
2484 paddr += PAGE_SIZE;
2485 start += PAGE_SIZE;
2486 }
2487 address += offset;
2488
2489 ADD_STATS_COUNTER(alloced_io_mem, size);
2490
2491 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2492 domain_flush_tlb(&dma_dom->domain);
2493 dma_dom->need_flush = false;
2494 } else if (unlikely(amd_iommu_np_cache))
2495 domain_flush_pages(&dma_dom->domain, address, size);
2496
2497 out:
2498 return address;
2499
2500 out_unmap:
2501
2502 for (--i; i >= 0; --i) {
2503 start -= PAGE_SIZE;
2504 dma_ops_domain_unmap(dma_dom, start);
2505 }
2506
2507 dma_ops_free_addresses(dma_dom, address, pages);
2508
2509 return DMA_ERROR_CODE;
2510 }
2511
2512 /*
2513 * Does the reverse of the __map_single function. Must be called with
2514 * the domain lock held too
2515 */
2516 static void __unmap_single(struct dma_ops_domain *dma_dom,
2517 dma_addr_t dma_addr,
2518 size_t size,
2519 int dir)
2520 {
2521 dma_addr_t flush_addr;
2522 dma_addr_t i, start;
2523 unsigned int pages;
2524
2525 if ((dma_addr == DMA_ERROR_CODE) ||
2526 (dma_addr + size > dma_dom->aperture_size))
2527 return;
2528
2529 flush_addr = dma_addr;
2530 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2531 dma_addr &= PAGE_MASK;
2532 start = dma_addr;
2533
2534 for (i = 0; i < pages; ++i) {
2535 dma_ops_domain_unmap(dma_dom, start);
2536 start += PAGE_SIZE;
2537 }
2538
2539 SUB_STATS_COUNTER(alloced_io_mem, size);
2540
2541 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2542
2543 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2544 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2545 dma_dom->need_flush = false;
2546 }
2547 }
2548
2549 /*
2550 * The exported map_single function for dma_ops.
2551 */
2552 static dma_addr_t map_page(struct device *dev, struct page *page,
2553 unsigned long offset, size_t size,
2554 enum dma_data_direction dir,
2555 struct dma_attrs *attrs)
2556 {
2557 unsigned long flags;
2558 struct protection_domain *domain;
2559 dma_addr_t addr;
2560 u64 dma_mask;
2561 phys_addr_t paddr = page_to_phys(page) + offset;
2562
2563 INC_STATS_COUNTER(cnt_map_single);
2564
2565 domain = get_domain(dev);
2566 if (PTR_ERR(domain) == -EINVAL)
2567 return (dma_addr_t)paddr;
2568 else if (IS_ERR(domain))
2569 return DMA_ERROR_CODE;
2570
2571 dma_mask = *dev->dma_mask;
2572
2573 spin_lock_irqsave(&domain->lock, flags);
2574
2575 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2576 dma_mask);
2577 if (addr == DMA_ERROR_CODE)
2578 goto out;
2579
2580 domain_flush_complete(domain);
2581
2582 out:
2583 spin_unlock_irqrestore(&domain->lock, flags);
2584
2585 return addr;
2586 }
2587
2588 /*
2589 * The exported unmap_single function for dma_ops.
2590 */
2591 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2592 enum dma_data_direction dir, struct dma_attrs *attrs)
2593 {
2594 unsigned long flags;
2595 struct protection_domain *domain;
2596
2597 INC_STATS_COUNTER(cnt_unmap_single);
2598
2599 domain = get_domain(dev);
2600 if (IS_ERR(domain))
2601 return;
2602
2603 spin_lock_irqsave(&domain->lock, flags);
2604
2605 __unmap_single(domain->priv, dma_addr, size, dir);
2606
2607 domain_flush_complete(domain);
2608
2609 spin_unlock_irqrestore(&domain->lock, flags);
2610 }
2611
2612 /*
2613 * This is a special map_sg function which is used if we should map a
2614 * device which is not handled by an AMD IOMMU in the system.
2615 */
2616 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2617 int nelems, int dir)
2618 {
2619 struct scatterlist *s;
2620 int i;
2621
2622 for_each_sg(sglist, s, nelems, i) {
2623 s->dma_address = (dma_addr_t)sg_phys(s);
2624 s->dma_length = s->length;
2625 }
2626
2627 return nelems;
2628 }
2629
2630 /*
2631 * The exported map_sg function for dma_ops (handles scatter-gather
2632 * lists).
2633 */
2634 static int map_sg(struct device *dev, struct scatterlist *sglist,
2635 int nelems, enum dma_data_direction dir,
2636 struct dma_attrs *attrs)
2637 {
2638 unsigned long flags;
2639 struct protection_domain *domain;
2640 int i;
2641 struct scatterlist *s;
2642 phys_addr_t paddr;
2643 int mapped_elems = 0;
2644 u64 dma_mask;
2645
2646 INC_STATS_COUNTER(cnt_map_sg);
2647
2648 domain = get_domain(dev);
2649 if (PTR_ERR(domain) == -EINVAL)
2650 return map_sg_no_iommu(dev, sglist, nelems, dir);
2651 else if (IS_ERR(domain))
2652 return 0;
2653
2654 dma_mask = *dev->dma_mask;
2655
2656 spin_lock_irqsave(&domain->lock, flags);
2657
2658 for_each_sg(sglist, s, nelems, i) {
2659 paddr = sg_phys(s);
2660
2661 s->dma_address = __map_single(dev, domain->priv,
2662 paddr, s->length, dir, false,
2663 dma_mask);
2664
2665 if (s->dma_address) {
2666 s->dma_length = s->length;
2667 mapped_elems++;
2668 } else
2669 goto unmap;
2670 }
2671
2672 domain_flush_complete(domain);
2673
2674 out:
2675 spin_unlock_irqrestore(&domain->lock, flags);
2676
2677 return mapped_elems;
2678 unmap:
2679 for_each_sg(sglist, s, mapped_elems, i) {
2680 if (s->dma_address)
2681 __unmap_single(domain->priv, s->dma_address,
2682 s->dma_length, dir);
2683 s->dma_address = s->dma_length = 0;
2684 }
2685
2686 mapped_elems = 0;
2687
2688 goto out;
2689 }
2690
2691 /*
2692 * The exported map_sg function for dma_ops (handles scatter-gather
2693 * lists).
2694 */
2695 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2696 int nelems, enum dma_data_direction dir,
2697 struct dma_attrs *attrs)
2698 {
2699 unsigned long flags;
2700 struct protection_domain *domain;
2701 struct scatterlist *s;
2702 int i;
2703
2704 INC_STATS_COUNTER(cnt_unmap_sg);
2705
2706 domain = get_domain(dev);
2707 if (IS_ERR(domain))
2708 return;
2709
2710 spin_lock_irqsave(&domain->lock, flags);
2711
2712 for_each_sg(sglist, s, nelems, i) {
2713 __unmap_single(domain->priv, s->dma_address,
2714 s->dma_length, dir);
2715 s->dma_address = s->dma_length = 0;
2716 }
2717
2718 domain_flush_complete(domain);
2719
2720 spin_unlock_irqrestore(&domain->lock, flags);
2721 }
2722
2723 /*
2724 * The exported alloc_coherent function for dma_ops.
2725 */
2726 static void *alloc_coherent(struct device *dev, size_t size,
2727 dma_addr_t *dma_addr, gfp_t flag,
2728 struct dma_attrs *attrs)
2729 {
2730 unsigned long flags;
2731 void *virt_addr;
2732 struct protection_domain *domain;
2733 phys_addr_t paddr;
2734 u64 dma_mask = dev->coherent_dma_mask;
2735
2736 INC_STATS_COUNTER(cnt_alloc_coherent);
2737
2738 domain = get_domain(dev);
2739 if (PTR_ERR(domain) == -EINVAL) {
2740 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2741 *dma_addr = __pa(virt_addr);
2742 return virt_addr;
2743 } else if (IS_ERR(domain))
2744 return NULL;
2745
2746 dma_mask = dev->coherent_dma_mask;
2747 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2748 flag |= __GFP_ZERO;
2749
2750 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2751 if (!virt_addr)
2752 return NULL;
2753
2754 paddr = virt_to_phys(virt_addr);
2755
2756 if (!dma_mask)
2757 dma_mask = *dev->dma_mask;
2758
2759 spin_lock_irqsave(&domain->lock, flags);
2760
2761 *dma_addr = __map_single(dev, domain->priv, paddr,
2762 size, DMA_BIDIRECTIONAL, true, dma_mask);
2763
2764 if (*dma_addr == DMA_ERROR_CODE) {
2765 spin_unlock_irqrestore(&domain->lock, flags);
2766 goto out_free;
2767 }
2768
2769 domain_flush_complete(domain);
2770
2771 spin_unlock_irqrestore(&domain->lock, flags);
2772
2773 return virt_addr;
2774
2775 out_free:
2776
2777 free_pages((unsigned long)virt_addr, get_order(size));
2778
2779 return NULL;
2780 }
2781
2782 /*
2783 * The exported free_coherent function for dma_ops.
2784 */
2785 static void free_coherent(struct device *dev, size_t size,
2786 void *virt_addr, dma_addr_t dma_addr,
2787 struct dma_attrs *attrs)
2788 {
2789 unsigned long flags;
2790 struct protection_domain *domain;
2791
2792 INC_STATS_COUNTER(cnt_free_coherent);
2793
2794 domain = get_domain(dev);
2795 if (IS_ERR(domain))
2796 goto free_mem;
2797
2798 spin_lock_irqsave(&domain->lock, flags);
2799
2800 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2801
2802 domain_flush_complete(domain);
2803
2804 spin_unlock_irqrestore(&domain->lock, flags);
2805
2806 free_mem:
2807 free_pages((unsigned long)virt_addr, get_order(size));
2808 }
2809
2810 /*
2811 * This function is called by the DMA layer to find out if we can handle a
2812 * particular device. It is part of the dma_ops.
2813 */
2814 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2815 {
2816 return check_device(dev);
2817 }
2818
2819 /*
2820 * The function for pre-allocating protection domains.
2821 *
2822 * If the driver core informs the DMA layer if a driver grabs a device
2823 * we don't need to preallocate the protection domains anymore.
2824 * For now we have to.
2825 */
2826 static void __init prealloc_protection_domains(void)
2827 {
2828 struct iommu_dev_data *dev_data;
2829 struct dma_ops_domain *dma_dom;
2830 struct pci_dev *dev = NULL;
2831 u16 devid;
2832
2833 for_each_pci_dev(dev) {
2834
2835 /* Do we handle this device? */
2836 if (!check_device(&dev->dev))
2837 continue;
2838
2839 dev_data = get_dev_data(&dev->dev);
2840 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
2841 /* Make sure passthrough domain is allocated */
2842 alloc_passthrough_domain();
2843 dev_data->passthrough = true;
2844 attach_device(&dev->dev, pt_domain);
2845 pr_info("AMD-Vi: Using passthough domain for device %s\n",
2846 dev_name(&dev->dev));
2847 }
2848
2849 /* Is there already any domain for it? */
2850 if (domain_for_device(&dev->dev))
2851 continue;
2852
2853 devid = get_device_id(&dev->dev);
2854
2855 dma_dom = dma_ops_domain_alloc();
2856 if (!dma_dom)
2857 continue;
2858 init_unity_mappings_for_device(dma_dom, devid);
2859 dma_dom->target_dev = devid;
2860
2861 attach_device(&dev->dev, &dma_dom->domain);
2862
2863 list_add_tail(&dma_dom->list, &iommu_pd_list);
2864 }
2865 }
2866
2867 static struct dma_map_ops amd_iommu_dma_ops = {
2868 .alloc = alloc_coherent,
2869 .free = free_coherent,
2870 .map_page = map_page,
2871 .unmap_page = unmap_page,
2872 .map_sg = map_sg,
2873 .unmap_sg = unmap_sg,
2874 .dma_supported = amd_iommu_dma_supported,
2875 };
2876
2877 static unsigned device_dma_ops_init(void)
2878 {
2879 struct iommu_dev_data *dev_data;
2880 struct pci_dev *pdev = NULL;
2881 unsigned unhandled = 0;
2882
2883 for_each_pci_dev(pdev) {
2884 if (!check_device(&pdev->dev)) {
2885
2886 iommu_ignore_device(&pdev->dev);
2887
2888 unhandled += 1;
2889 continue;
2890 }
2891
2892 dev_data = get_dev_data(&pdev->dev);
2893
2894 if (!dev_data->passthrough)
2895 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2896 else
2897 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
2898 }
2899
2900 return unhandled;
2901 }
2902
2903 /*
2904 * The function which clues the AMD IOMMU driver into dma_ops.
2905 */
2906
2907 void __init amd_iommu_init_api(void)
2908 {
2909 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2910 }
2911
2912 int __init amd_iommu_init_dma_ops(void)
2913 {
2914 struct amd_iommu *iommu;
2915 int ret, unhandled;
2916
2917 /*
2918 * first allocate a default protection domain for every IOMMU we
2919 * found in the system. Devices not assigned to any other
2920 * protection domain will be assigned to the default one.
2921 */
2922 for_each_iommu(iommu) {
2923 iommu->default_dom = dma_ops_domain_alloc();
2924 if (iommu->default_dom == NULL)
2925 return -ENOMEM;
2926 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2927 ret = iommu_init_unity_mappings(iommu);
2928 if (ret)
2929 goto free_domains;
2930 }
2931
2932 /*
2933 * Pre-allocate the protection domains for each device.
2934 */
2935 prealloc_protection_domains();
2936
2937 iommu_detected = 1;
2938 swiotlb = 0;
2939
2940 /* Make the driver finally visible to the drivers */
2941 unhandled = device_dma_ops_init();
2942 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2943 /* There are unhandled devices - initialize swiotlb for them */
2944 swiotlb = 1;
2945 }
2946
2947 amd_iommu_stats_init();
2948
2949 return 0;
2950
2951 free_domains:
2952
2953 for_each_iommu(iommu) {
2954 if (iommu->default_dom)
2955 dma_ops_domain_free(iommu->default_dom);
2956 }
2957
2958 return ret;
2959 }
2960
2961 /*****************************************************************************
2962 *
2963 * The following functions belong to the exported interface of AMD IOMMU
2964 *
2965 * This interface allows access to lower level functions of the IOMMU
2966 * like protection domain handling and assignement of devices to domains
2967 * which is not possible with the dma_ops interface.
2968 *
2969 *****************************************************************************/
2970
2971 static void cleanup_domain(struct protection_domain *domain)
2972 {
2973 struct iommu_dev_data *dev_data, *next;
2974 unsigned long flags;
2975
2976 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2977
2978 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2979 __detach_device(dev_data);
2980 atomic_set(&dev_data->bind, 0);
2981 }
2982
2983 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2984 }
2985
2986 static void protection_domain_free(struct protection_domain *domain)
2987 {
2988 if (!domain)
2989 return;
2990
2991 del_domain_from_list(domain);
2992
2993 if (domain->id)
2994 domain_id_free(domain->id);
2995
2996 kfree(domain);
2997 }
2998
2999 static struct protection_domain *protection_domain_alloc(void)
3000 {
3001 struct protection_domain *domain;
3002
3003 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3004 if (!domain)
3005 return NULL;
3006
3007 spin_lock_init(&domain->lock);
3008 mutex_init(&domain->api_lock);
3009 domain->id = domain_id_alloc();
3010 if (!domain->id)
3011 goto out_err;
3012 INIT_LIST_HEAD(&domain->dev_list);
3013
3014 add_domain_to_list(domain);
3015
3016 return domain;
3017
3018 out_err:
3019 kfree(domain);
3020
3021 return NULL;
3022 }
3023
3024 static int __init alloc_passthrough_domain(void)
3025 {
3026 if (pt_domain != NULL)
3027 return 0;
3028
3029 /* allocate passthrough domain */
3030 pt_domain = protection_domain_alloc();
3031 if (!pt_domain)
3032 return -ENOMEM;
3033
3034 pt_domain->mode = PAGE_MODE_NONE;
3035
3036 return 0;
3037 }
3038 static int amd_iommu_domain_init(struct iommu_domain *dom)
3039 {
3040 struct protection_domain *domain;
3041
3042 domain = protection_domain_alloc();
3043 if (!domain)
3044 goto out_free;
3045
3046 domain->mode = PAGE_MODE_3_LEVEL;
3047 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3048 if (!domain->pt_root)
3049 goto out_free;
3050
3051 domain->iommu_domain = dom;
3052
3053 dom->priv = domain;
3054
3055 return 0;
3056
3057 out_free:
3058 protection_domain_free(domain);
3059
3060 return -ENOMEM;
3061 }
3062
3063 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3064 {
3065 struct protection_domain *domain = dom->priv;
3066
3067 if (!domain)
3068 return;
3069
3070 if (domain->dev_cnt > 0)
3071 cleanup_domain(domain);
3072
3073 BUG_ON(domain->dev_cnt != 0);
3074
3075 if (domain->mode != PAGE_MODE_NONE)
3076 free_pagetable(domain);
3077
3078 if (domain->flags & PD_IOMMUV2_MASK)
3079 free_gcr3_table(domain);
3080
3081 protection_domain_free(domain);
3082
3083 dom->priv = NULL;
3084 }
3085
3086 static void amd_iommu_detach_device(struct iommu_domain *dom,
3087 struct device *dev)
3088 {
3089 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3090 struct amd_iommu *iommu;
3091 u16 devid;
3092
3093 if (!check_device(dev))
3094 return;
3095
3096 devid = get_device_id(dev);
3097
3098 if (dev_data->domain != NULL)
3099 detach_device(dev);
3100
3101 iommu = amd_iommu_rlookup_table[devid];
3102 if (!iommu)
3103 return;
3104
3105 iommu_completion_wait(iommu);
3106 }
3107
3108 static int amd_iommu_attach_device(struct iommu_domain *dom,
3109 struct device *dev)
3110 {
3111 struct protection_domain *domain = dom->priv;
3112 struct iommu_dev_data *dev_data;
3113 struct amd_iommu *iommu;
3114 int ret;
3115
3116 if (!check_device(dev))
3117 return -EINVAL;
3118
3119 dev_data = dev->archdata.iommu;
3120
3121 iommu = amd_iommu_rlookup_table[dev_data->devid];
3122 if (!iommu)
3123 return -EINVAL;
3124
3125 if (dev_data->domain)
3126 detach_device(dev);
3127
3128 ret = attach_device(dev, domain);
3129
3130 iommu_completion_wait(iommu);
3131
3132 return ret;
3133 }
3134
3135 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3136 phys_addr_t paddr, size_t page_size, int iommu_prot)
3137 {
3138 struct protection_domain *domain = dom->priv;
3139 int prot = 0;
3140 int ret;
3141
3142 if (domain->mode == PAGE_MODE_NONE)
3143 return -EINVAL;
3144
3145 if (iommu_prot & IOMMU_READ)
3146 prot |= IOMMU_PROT_IR;
3147 if (iommu_prot & IOMMU_WRITE)
3148 prot |= IOMMU_PROT_IW;
3149
3150 mutex_lock(&domain->api_lock);
3151 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3152 mutex_unlock(&domain->api_lock);
3153
3154 return ret;
3155 }
3156
3157 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3158 size_t page_size)
3159 {
3160 struct protection_domain *domain = dom->priv;
3161 size_t unmap_size;
3162
3163 if (domain->mode == PAGE_MODE_NONE)
3164 return -EINVAL;
3165
3166 mutex_lock(&domain->api_lock);
3167 unmap_size = iommu_unmap_page(domain, iova, page_size);
3168 mutex_unlock(&domain->api_lock);
3169
3170 domain_flush_tlb_pde(domain);
3171
3172 return unmap_size;
3173 }
3174
3175 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3176 unsigned long iova)
3177 {
3178 struct protection_domain *domain = dom->priv;
3179 unsigned long offset_mask;
3180 phys_addr_t paddr;
3181 u64 *pte, __pte;
3182
3183 if (domain->mode == PAGE_MODE_NONE)
3184 return iova;
3185
3186 pte = fetch_pte(domain, iova);
3187
3188 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3189 return 0;
3190
3191 if (PM_PTE_LEVEL(*pte) == 0)
3192 offset_mask = PAGE_SIZE - 1;
3193 else
3194 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
3195
3196 __pte = *pte & PM_ADDR_MASK;
3197 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
3198
3199 return paddr;
3200 }
3201
3202 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
3203 unsigned long cap)
3204 {
3205 switch (cap) {
3206 case IOMMU_CAP_CACHE_COHERENCY:
3207 return 1;
3208 }
3209
3210 return 0;
3211 }
3212
3213 static int amd_iommu_device_group(struct device *dev, unsigned int *groupid)
3214 {
3215 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3216 struct pci_dev *pdev = to_pci_dev(dev);
3217 u16 devid;
3218
3219 if (!dev_data)
3220 return -ENODEV;
3221
3222 if (pdev->is_virtfn || !iommu_group_mf)
3223 devid = dev_data->devid;
3224 else
3225 devid = calc_devid(pdev->bus->number,
3226 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
3227
3228 *groupid = amd_iommu_alias_table[devid];
3229
3230 return 0;
3231 }
3232
3233 static struct iommu_ops amd_iommu_ops = {
3234 .domain_init = amd_iommu_domain_init,
3235 .domain_destroy = amd_iommu_domain_destroy,
3236 .attach_dev = amd_iommu_attach_device,
3237 .detach_dev = amd_iommu_detach_device,
3238 .map = amd_iommu_map,
3239 .unmap = amd_iommu_unmap,
3240 .iova_to_phys = amd_iommu_iova_to_phys,
3241 .domain_has_cap = amd_iommu_domain_has_cap,
3242 .device_group = amd_iommu_device_group,
3243 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3244 };
3245
3246 /*****************************************************************************
3247 *
3248 * The next functions do a basic initialization of IOMMU for pass through
3249 * mode
3250 *
3251 * In passthrough mode the IOMMU is initialized and enabled but not used for
3252 * DMA-API translation.
3253 *
3254 *****************************************************************************/
3255
3256 int __init amd_iommu_init_passthrough(void)
3257 {
3258 struct iommu_dev_data *dev_data;
3259 struct pci_dev *dev = NULL;
3260 struct amd_iommu *iommu;
3261 u16 devid;
3262 int ret;
3263
3264 ret = alloc_passthrough_domain();
3265 if (ret)
3266 return ret;
3267
3268 for_each_pci_dev(dev) {
3269 if (!check_device(&dev->dev))
3270 continue;
3271
3272 dev_data = get_dev_data(&dev->dev);
3273 dev_data->passthrough = true;
3274
3275 devid = get_device_id(&dev->dev);
3276
3277 iommu = amd_iommu_rlookup_table[devid];
3278 if (!iommu)
3279 continue;
3280
3281 attach_device(&dev->dev, pt_domain);
3282 }
3283
3284 amd_iommu_stats_init();
3285
3286 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3287
3288 return 0;
3289 }
3290
3291 /* IOMMUv2 specific functions */
3292 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3293 {
3294 return atomic_notifier_chain_register(&ppr_notifier, nb);
3295 }
3296 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3297
3298 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3299 {
3300 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3301 }
3302 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3303
3304 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3305 {
3306 struct protection_domain *domain = dom->priv;
3307 unsigned long flags;
3308
3309 spin_lock_irqsave(&domain->lock, flags);
3310
3311 /* Update data structure */
3312 domain->mode = PAGE_MODE_NONE;
3313 domain->updated = true;
3314
3315 /* Make changes visible to IOMMUs */
3316 update_domain(domain);
3317
3318 /* Page-table is not visible to IOMMU anymore, so free it */
3319 free_pagetable(domain);
3320
3321 spin_unlock_irqrestore(&domain->lock, flags);
3322 }
3323 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3324
3325 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3326 {
3327 struct protection_domain *domain = dom->priv;
3328 unsigned long flags;
3329 int levels, ret;
3330
3331 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3332 return -EINVAL;
3333
3334 /* Number of GCR3 table levels required */
3335 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3336 levels += 1;
3337
3338 if (levels > amd_iommu_max_glx_val)
3339 return -EINVAL;
3340
3341 spin_lock_irqsave(&domain->lock, flags);
3342
3343 /*
3344 * Save us all sanity checks whether devices already in the
3345 * domain support IOMMUv2. Just force that the domain has no
3346 * devices attached when it is switched into IOMMUv2 mode.
3347 */
3348 ret = -EBUSY;
3349 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3350 goto out;
3351
3352 ret = -ENOMEM;
3353 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3354 if (domain->gcr3_tbl == NULL)
3355 goto out;
3356
3357 domain->glx = levels;
3358 domain->flags |= PD_IOMMUV2_MASK;
3359 domain->updated = true;
3360
3361 update_domain(domain);
3362
3363 ret = 0;
3364
3365 out:
3366 spin_unlock_irqrestore(&domain->lock, flags);
3367
3368 return ret;
3369 }
3370 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3371
3372 static int __flush_pasid(struct protection_domain *domain, int pasid,
3373 u64 address, bool size)
3374 {
3375 struct iommu_dev_data *dev_data;
3376 struct iommu_cmd cmd;
3377 int i, ret;
3378
3379 if (!(domain->flags & PD_IOMMUV2_MASK))
3380 return -EINVAL;
3381
3382 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3383
3384 /*
3385 * IOMMU TLB needs to be flushed before Device TLB to
3386 * prevent device TLB refill from IOMMU TLB
3387 */
3388 for (i = 0; i < amd_iommus_present; ++i) {
3389 if (domain->dev_iommu[i] == 0)
3390 continue;
3391
3392 ret = iommu_queue_command(amd_iommus[i], &cmd);
3393 if (ret != 0)
3394 goto out;
3395 }
3396
3397 /* Wait until IOMMU TLB flushes are complete */
3398 domain_flush_complete(domain);
3399
3400 /* Now flush device TLBs */
3401 list_for_each_entry(dev_data, &domain->dev_list, list) {
3402 struct amd_iommu *iommu;
3403 int qdep;
3404
3405 BUG_ON(!dev_data->ats.enabled);
3406
3407 qdep = dev_data->ats.qdep;
3408 iommu = amd_iommu_rlookup_table[dev_data->devid];
3409
3410 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3411 qdep, address, size);
3412
3413 ret = iommu_queue_command(iommu, &cmd);
3414 if (ret != 0)
3415 goto out;
3416 }
3417
3418 /* Wait until all device TLBs are flushed */
3419 domain_flush_complete(domain);
3420
3421 ret = 0;
3422
3423 out:
3424
3425 return ret;
3426 }
3427
3428 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3429 u64 address)
3430 {
3431 INC_STATS_COUNTER(invalidate_iotlb);
3432
3433 return __flush_pasid(domain, pasid, address, false);
3434 }
3435
3436 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3437 u64 address)
3438 {
3439 struct protection_domain *domain = dom->priv;
3440 unsigned long flags;
3441 int ret;
3442
3443 spin_lock_irqsave(&domain->lock, flags);
3444 ret = __amd_iommu_flush_page(domain, pasid, address);
3445 spin_unlock_irqrestore(&domain->lock, flags);
3446
3447 return ret;
3448 }
3449 EXPORT_SYMBOL(amd_iommu_flush_page);
3450
3451 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3452 {
3453 INC_STATS_COUNTER(invalidate_iotlb_all);
3454
3455 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3456 true);
3457 }
3458
3459 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3460 {
3461 struct protection_domain *domain = dom->priv;
3462 unsigned long flags;
3463 int ret;
3464
3465 spin_lock_irqsave(&domain->lock, flags);
3466 ret = __amd_iommu_flush_tlb(domain, pasid);
3467 spin_unlock_irqrestore(&domain->lock, flags);
3468
3469 return ret;
3470 }
3471 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3472
3473 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3474 {
3475 int index;
3476 u64 *pte;
3477
3478 while (true) {
3479
3480 index = (pasid >> (9 * level)) & 0x1ff;
3481 pte = &root[index];
3482
3483 if (level == 0)
3484 break;
3485
3486 if (!(*pte & GCR3_VALID)) {
3487 if (!alloc)
3488 return NULL;
3489
3490 root = (void *)get_zeroed_page(GFP_ATOMIC);
3491 if (root == NULL)
3492 return NULL;
3493
3494 *pte = __pa(root) | GCR3_VALID;
3495 }
3496
3497 root = __va(*pte & PAGE_MASK);
3498
3499 level -= 1;
3500 }
3501
3502 return pte;
3503 }
3504
3505 static int __set_gcr3(struct protection_domain *domain, int pasid,
3506 unsigned long cr3)
3507 {
3508 u64 *pte;
3509
3510 if (domain->mode != PAGE_MODE_NONE)
3511 return -EINVAL;
3512
3513 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3514 if (pte == NULL)
3515 return -ENOMEM;
3516
3517 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3518
3519 return __amd_iommu_flush_tlb(domain, pasid);
3520 }
3521
3522 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3523 {
3524 u64 *pte;
3525
3526 if (domain->mode != PAGE_MODE_NONE)
3527 return -EINVAL;
3528
3529 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3530 if (pte == NULL)
3531 return 0;
3532
3533 *pte = 0;
3534
3535 return __amd_iommu_flush_tlb(domain, pasid);
3536 }
3537
3538 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3539 unsigned long cr3)
3540 {
3541 struct protection_domain *domain = dom->priv;
3542 unsigned long flags;
3543 int ret;
3544
3545 spin_lock_irqsave(&domain->lock, flags);
3546 ret = __set_gcr3(domain, pasid, cr3);
3547 spin_unlock_irqrestore(&domain->lock, flags);
3548
3549 return ret;
3550 }
3551 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3552
3553 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3554 {
3555 struct protection_domain *domain = dom->priv;
3556 unsigned long flags;
3557 int ret;
3558
3559 spin_lock_irqsave(&domain->lock, flags);
3560 ret = __clear_gcr3(domain, pasid);
3561 spin_unlock_irqrestore(&domain->lock, flags);
3562
3563 return ret;
3564 }
3565 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3566
3567 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3568 int status, int tag)
3569 {
3570 struct iommu_dev_data *dev_data;
3571 struct amd_iommu *iommu;
3572 struct iommu_cmd cmd;
3573
3574 INC_STATS_COUNTER(complete_ppr);
3575
3576 dev_data = get_dev_data(&pdev->dev);
3577 iommu = amd_iommu_rlookup_table[dev_data->devid];
3578
3579 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3580 tag, dev_data->pri_tlp);
3581
3582 return iommu_queue_command(iommu, &cmd);
3583 }
3584 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3585
3586 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3587 {
3588 struct protection_domain *domain;
3589
3590 domain = get_domain(&pdev->dev);
3591 if (IS_ERR(domain))
3592 return NULL;
3593
3594 /* Only return IOMMUv2 domains */
3595 if (!(domain->flags & PD_IOMMUV2_MASK))
3596 return NULL;
3597
3598 return domain->iommu_domain;
3599 }
3600 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3601
3602 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3603 {
3604 struct iommu_dev_data *dev_data;
3605
3606 if (!amd_iommu_v2_supported())
3607 return;
3608
3609 dev_data = get_dev_data(&pdev->dev);
3610 dev_data->errata |= (1 << erratum);
3611 }
3612 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3613
3614 int amd_iommu_device_info(struct pci_dev *pdev,
3615 struct amd_iommu_device_info *info)
3616 {
3617 int max_pasids;
3618 int pos;
3619
3620 if (pdev == NULL || info == NULL)
3621 return -EINVAL;
3622
3623 if (!amd_iommu_v2_supported())
3624 return -EINVAL;
3625
3626 memset(info, 0, sizeof(*info));
3627
3628 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3629 if (pos)
3630 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3631
3632 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3633 if (pos)
3634 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3635
3636 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3637 if (pos) {
3638 int features;
3639
3640 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3641 max_pasids = min(max_pasids, (1 << 20));
3642
3643 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3644 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3645
3646 features = pci_pasid_features(pdev);
3647 if (features & PCI_PASID_CAP_EXEC)
3648 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3649 if (features & PCI_PASID_CAP_PRIV)
3650 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3651 }
3652
3653 return 0;
3654 }
3655 EXPORT_SYMBOL(amd_iommu_device_info);
Linux 2.6 libata-dev (mirror)