2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
77 static DEFINE_RAW_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing
[MAX_IO_APICS
];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
94 /* # of MP IRQ source entries */
98 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
104 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
106 int skip_ioapic_setup
;
108 void arch_disable_smp_support(void)
112 noioapicreroute
= -1;
114 skip_ioapic_setup
= 1;
117 static int __init
parse_noapic(char *str
)
119 /* disable IO-APIC */
120 arch_disable_smp_support();
123 early_param("noapic", parse_noapic
);
125 struct irq_pin_list
{
127 struct irq_pin_list
*next
;
130 static struct irq_pin_list
*get_one_free_irq_2_pin(int node
)
132 struct irq_pin_list
*pin
;
134 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
143 static struct irq_cfg irq_cfgx
[NR_IRQS
];
146 int __init
arch_early_irq_init(void)
149 struct irq_desc
*desc
;
154 if (!legacy_pic
->nr_legacy_irqs
) {
160 count
= ARRAY_SIZE(irq_cfgx
);
161 node
= cpu_to_node(boot_cpu_id
);
163 for (i
= 0; i
< count
; i
++) {
164 if (i
< legacy_pic
->nr_legacy_irqs
)
165 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
166 desc
= irq_to_desc(i
);
167 desc
->chip_data
= &cfg
[i
];
168 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_NOWAIT
, node
);
169 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_NOWAIT
, node
);
171 * For legacy IRQ's, start with assigning irq0 to irq15 to
172 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
174 if (i
< legacy_pic
->nr_legacy_irqs
) {
175 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
176 cpumask_set_cpu(0, cfg
[i
].domain
);
183 #ifdef CONFIG_SPARSE_IRQ
184 struct irq_cfg
*irq_cfg(unsigned int irq
)
186 struct irq_cfg
*cfg
= NULL
;
187 struct irq_desc
*desc
;
189 desc
= irq_to_desc(irq
);
191 cfg
= desc
->chip_data
;
196 static struct irq_cfg
*get_one_free_irq_cfg(int node
)
200 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
202 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
205 } else if (!zalloc_cpumask_var_node(&cfg
->old_domain
,
207 free_cpumask_var(cfg
->domain
);
216 int arch_init_chip_data(struct irq_desc
*desc
, int node
)
220 cfg
= desc
->chip_data
;
222 desc
->chip_data
= get_one_free_irq_cfg(node
);
223 if (!desc
->chip_data
) {
224 printk(KERN_ERR
"can not alloc irq_cfg\n");
232 /* for move_irq_desc */
234 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int node
)
236 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
238 cfg
->irq_2_pin
= NULL
;
239 old_entry
= old_cfg
->irq_2_pin
;
243 entry
= get_one_free_irq_2_pin(node
);
247 entry
->apic
= old_entry
->apic
;
248 entry
->pin
= old_entry
->pin
;
251 old_entry
= old_entry
->next
;
253 entry
= get_one_free_irq_2_pin(node
);
261 /* still use the old one */
264 entry
->apic
= old_entry
->apic
;
265 entry
->pin
= old_entry
->pin
;
268 old_entry
= old_entry
->next
;
272 cfg
->irq_2_pin
= head
;
275 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
277 struct irq_pin_list
*entry
, *next
;
279 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
282 entry
= old_cfg
->irq_2_pin
;
289 old_cfg
->irq_2_pin
= NULL
;
292 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
293 struct irq_desc
*desc
, int node
)
296 struct irq_cfg
*old_cfg
;
298 cfg
= get_one_free_irq_cfg(node
);
303 desc
->chip_data
= cfg
;
305 old_cfg
= old_desc
->chip_data
;
307 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
309 init_copy_irq_2_pin(old_cfg
, cfg
, node
);
312 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
317 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
319 struct irq_cfg
*old_cfg
, *cfg
;
321 old_cfg
= old_desc
->chip_data
;
322 cfg
= desc
->chip_data
;
328 free_irq_2_pin(old_cfg
, cfg
);
329 free_irq_cfg(old_cfg
);
330 old_desc
->chip_data
= NULL
;
333 /* end for move_irq_desc */
336 struct irq_cfg
*irq_cfg(unsigned int irq
)
338 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
345 unsigned int unused
[3];
347 unsigned int unused2
[11];
351 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
353 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
354 + (mp_ioapics
[idx
].apicaddr
& ~PAGE_MASK
);
357 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
359 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
360 writel(vector
, &io_apic
->eoi
);
363 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
365 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
366 writel(reg
, &io_apic
->index
);
367 return readl(&io_apic
->data
);
370 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
372 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
373 writel(reg
, &io_apic
->index
);
374 writel(value
, &io_apic
->data
);
378 * Re-write a value: to be used for read-modify-write
379 * cycles where the read already set up the index register.
381 * Older SiS APIC requires we rewrite the index register
383 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
385 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
388 writel(reg
, &io_apic
->index
);
389 writel(value
, &io_apic
->data
);
392 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
394 struct irq_pin_list
*entry
;
397 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
398 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
403 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
404 /* Is the remote IRR bit set? */
405 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
406 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
410 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
416 struct { u32 w1
, w2
; };
417 struct IO_APIC_route_entry entry
;
420 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
422 union entry_union eu
;
424 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
425 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
426 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
427 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
432 * When we write a new IO APIC routing entry, we need to write the high
433 * word first! If the mask bit in the low word is clear, we will enable
434 * the interrupt, and we need to make sure the entry is fully populated
435 * before that happens.
438 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
440 union entry_union eu
= {{0, 0}};
443 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
444 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
447 void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
450 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
451 __ioapic_write_entry(apic
, pin
, e
);
452 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
456 * When we mask an IO APIC routing entry, we need to write the low
457 * word first, in order to set the mask bit before we change the
460 static void ioapic_mask_entry(int apic
, int pin
)
463 union entry_union eu
= { .entry
.mask
= 1 };
465 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
466 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
467 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
468 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
472 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
473 * shared ISA-space IRQs, so we have to support them. We are super
474 * fast in the common case, and fast for shared ISA-space IRQs.
477 add_pin_to_irq_node_nopanic(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
479 struct irq_pin_list
**last
, *entry
;
481 /* don't allow duplicates */
482 last
= &cfg
->irq_2_pin
;
483 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
484 if (entry
->apic
== apic
&& entry
->pin
== pin
)
489 entry
= get_one_free_irq_2_pin(node
);
491 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
502 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
504 if (add_pin_to_irq_node_nopanic(cfg
, node
, apic
, pin
))
505 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
509 * Reroute an IRQ to a different pin.
511 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
512 int oldapic
, int oldpin
,
513 int newapic
, int newpin
)
515 struct irq_pin_list
*entry
;
517 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
518 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
519 entry
->apic
= newapic
;
521 /* every one is different, right? */
526 /* old apic/pin didn't exist, so just add new ones */
527 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
530 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
531 int mask_and
, int mask_or
,
532 void (*final
)(struct irq_pin_list
*entry
))
534 unsigned int reg
, pin
;
537 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
540 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
545 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
546 int mask_and
, int mask_or
,
547 void (*final
)(struct irq_pin_list
*entry
))
549 struct irq_pin_list
*entry
;
551 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
552 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
555 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list
*entry
)
557 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
558 IO_APIC_REDIR_MASKED
, NULL
);
561 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list
*entry
)
563 __io_apic_modify_irq(entry
, ~IO_APIC_REDIR_MASKED
,
564 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
567 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
569 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
572 static void io_apic_sync(struct irq_pin_list
*entry
)
575 * Synchronize the IO-APIC and the CPU by doing
576 * a dummy read from the IO-APIC
578 struct io_apic __iomem
*io_apic
;
579 io_apic
= io_apic_base(entry
->apic
);
580 readl(&io_apic
->data
);
583 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
585 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
588 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
590 struct irq_cfg
*cfg
= desc
->chip_data
;
595 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
596 __mask_IO_APIC_irq(cfg
);
597 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
600 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
602 struct irq_cfg
*cfg
= desc
->chip_data
;
605 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
606 __unmask_IO_APIC_irq(cfg
);
607 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
610 static void mask_IO_APIC_irq(unsigned int irq
)
612 struct irq_desc
*desc
= irq_to_desc(irq
);
614 mask_IO_APIC_irq_desc(desc
);
616 static void unmask_IO_APIC_irq(unsigned int irq
)
618 struct irq_desc
*desc
= irq_to_desc(irq
);
620 unmask_IO_APIC_irq_desc(desc
);
623 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
625 struct IO_APIC_route_entry entry
;
627 /* Check delivery_mode to be sure we're not clearing an SMI pin */
628 entry
= ioapic_read_entry(apic
, pin
);
629 if (entry
.delivery_mode
== dest_SMI
)
632 * Disable it in the IO-APIC irq-routing table:
634 ioapic_mask_entry(apic
, pin
);
637 static void clear_IO_APIC (void)
641 for (apic
= 0; apic
< nr_ioapics
; apic
++)
642 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
643 clear_IO_APIC_pin(apic
, pin
);
648 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
649 * specific CPU-side IRQs.
653 static int pirq_entries
[MAX_PIRQS
] = {
654 [0 ... MAX_PIRQS
- 1] = -1
657 static int __init
ioapic_pirq_setup(char *str
)
660 int ints
[MAX_PIRQS
+1];
662 get_options(str
, ARRAY_SIZE(ints
), ints
);
664 apic_printk(APIC_VERBOSE
, KERN_INFO
665 "PIRQ redirection, working around broken MP-BIOS.\n");
667 if (ints
[0] < MAX_PIRQS
)
670 for (i
= 0; i
< max
; i
++) {
671 apic_printk(APIC_VERBOSE
, KERN_DEBUG
672 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
674 * PIRQs are mapped upside down, usually.
676 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
681 __setup("pirq=", ioapic_pirq_setup
);
682 #endif /* CONFIG_X86_32 */
684 struct IO_APIC_route_entry
**alloc_ioapic_entries(void)
687 struct IO_APIC_route_entry
**ioapic_entries
;
689 ioapic_entries
= kzalloc(sizeof(*ioapic_entries
) * nr_ioapics
,
694 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
695 ioapic_entries
[apic
] =
696 kzalloc(sizeof(struct IO_APIC_route_entry
) *
697 nr_ioapic_registers
[apic
], GFP_ATOMIC
);
698 if (!ioapic_entries
[apic
])
702 return ioapic_entries
;
706 kfree(ioapic_entries
[apic
]);
707 kfree(ioapic_entries
);
713 * Saves all the IO-APIC RTE's
715 int save_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
722 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
723 if (!ioapic_entries
[apic
])
726 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
727 ioapic_entries
[apic
][pin
] =
728 ioapic_read_entry(apic
, pin
);
735 * Mask all IO APIC entries.
737 void mask_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
744 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
745 if (!ioapic_entries
[apic
])
748 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
749 struct IO_APIC_route_entry entry
;
751 entry
= ioapic_entries
[apic
][pin
];
754 ioapic_write_entry(apic
, pin
, entry
);
761 * Restore IO APIC entries which was saved in ioapic_entries.
763 int restore_IO_APIC_setup(struct IO_APIC_route_entry
**ioapic_entries
)
770 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
771 if (!ioapic_entries
[apic
])
774 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
775 ioapic_write_entry(apic
, pin
,
776 ioapic_entries
[apic
][pin
]);
781 void free_ioapic_entries(struct IO_APIC_route_entry
**ioapic_entries
)
785 for (apic
= 0; apic
< nr_ioapics
; apic
++)
786 kfree(ioapic_entries
[apic
]);
788 kfree(ioapic_entries
);
792 * Find the IRQ entry number of a certain pin.
794 static int find_irq_entry(int apic
, int pin
, int type
)
798 for (i
= 0; i
< mp_irq_entries
; i
++)
799 if (mp_irqs
[i
].irqtype
== type
&&
800 (mp_irqs
[i
].dstapic
== mp_ioapics
[apic
].apicid
||
801 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
802 mp_irqs
[i
].dstirq
== pin
)
809 * Find the pin to which IRQ[irq] (ISA) is connected
811 static int __init
find_isa_irq_pin(int irq
, int type
)
815 for (i
= 0; i
< mp_irq_entries
; i
++) {
816 int lbus
= mp_irqs
[i
].srcbus
;
818 if (test_bit(lbus
, mp_bus_not_pci
) &&
819 (mp_irqs
[i
].irqtype
== type
) &&
820 (mp_irqs
[i
].srcbusirq
== irq
))
822 return mp_irqs
[i
].dstirq
;
827 static int __init
find_isa_irq_apic(int irq
, int type
)
831 for (i
= 0; i
< mp_irq_entries
; i
++) {
832 int lbus
= mp_irqs
[i
].srcbus
;
834 if (test_bit(lbus
, mp_bus_not_pci
) &&
835 (mp_irqs
[i
].irqtype
== type
) &&
836 (mp_irqs
[i
].srcbusirq
== irq
))
839 if (i
< mp_irq_entries
) {
841 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
842 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
)
850 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
852 * EISA Edge/Level control register, ELCR
854 static int EISA_ELCR(unsigned int irq
)
856 if (irq
< legacy_pic
->nr_legacy_irqs
) {
857 unsigned int port
= 0x4d0 + (irq
>> 3);
858 return (inb(port
) >> (irq
& 7)) & 1;
860 apic_printk(APIC_VERBOSE
, KERN_INFO
861 "Broken MPtable reports ISA irq %d\n", irq
);
867 /* ISA interrupts are always polarity zero edge triggered,
868 * when listed as conforming in the MP table. */
870 #define default_ISA_trigger(idx) (0)
871 #define default_ISA_polarity(idx) (0)
873 /* EISA interrupts are always polarity zero and can be edge or level
874 * trigger depending on the ELCR value. If an interrupt is listed as
875 * EISA conforming in the MP table, that means its trigger type must
876 * be read in from the ELCR */
878 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
879 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
881 /* PCI interrupts are always polarity one level triggered,
882 * when listed as conforming in the MP table. */
884 #define default_PCI_trigger(idx) (1)
885 #define default_PCI_polarity(idx) (1)
887 /* MCA interrupts are always polarity zero level triggered,
888 * when listed as conforming in the MP table. */
890 #define default_MCA_trigger(idx) (1)
891 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
893 static int MPBIOS_polarity(int idx
)
895 int bus
= mp_irqs
[idx
].srcbus
;
899 * Determine IRQ line polarity (high active or low active):
901 switch (mp_irqs
[idx
].irqflag
& 3)
903 case 0: /* conforms, ie. bus-type dependent polarity */
904 if (test_bit(bus
, mp_bus_not_pci
))
905 polarity
= default_ISA_polarity(idx
);
907 polarity
= default_PCI_polarity(idx
);
909 case 1: /* high active */
914 case 2: /* reserved */
916 printk(KERN_WARNING
"broken BIOS!!\n");
920 case 3: /* low active */
925 default: /* invalid */
927 printk(KERN_WARNING
"broken BIOS!!\n");
935 static int MPBIOS_trigger(int idx
)
937 int bus
= mp_irqs
[idx
].srcbus
;
941 * Determine IRQ trigger mode (edge or level sensitive):
943 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
945 case 0: /* conforms, ie. bus-type dependent */
946 if (test_bit(bus
, mp_bus_not_pci
))
947 trigger
= default_ISA_trigger(idx
);
949 trigger
= default_PCI_trigger(idx
);
950 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
951 switch (mp_bus_id_to_type
[bus
]) {
952 case MP_BUS_ISA
: /* ISA pin */
954 /* set before the switch */
957 case MP_BUS_EISA
: /* EISA pin */
959 trigger
= default_EISA_trigger(idx
);
962 case MP_BUS_PCI
: /* PCI pin */
964 /* set before the switch */
967 case MP_BUS_MCA
: /* MCA pin */
969 trigger
= default_MCA_trigger(idx
);
974 printk(KERN_WARNING
"broken BIOS!!\n");
986 case 2: /* reserved */
988 printk(KERN_WARNING
"broken BIOS!!\n");
997 default: /* invalid */
999 printk(KERN_WARNING
"broken BIOS!!\n");
1007 static inline int irq_polarity(int idx
)
1009 return MPBIOS_polarity(idx
);
1012 static inline int irq_trigger(int idx
)
1014 return MPBIOS_trigger(idx
);
1017 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1018 static int pin_2_irq(int idx
, int apic
, int pin
)
1021 int bus
= mp_irqs
[idx
].srcbus
;
1024 * Debugging check, we are in big trouble if this message pops up!
1026 if (mp_irqs
[idx
].dstirq
!= pin
)
1027 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1029 if (test_bit(bus
, mp_bus_not_pci
)) {
1030 irq
= mp_irqs
[idx
].srcbusirq
;
1033 * PCI IRQs are mapped in order
1037 irq
+= nr_ioapic_registers
[i
++];
1040 * For MPS mode, so far only needed by ES7000 platform
1042 if (ioapic_renumber_irq
)
1043 irq
= ioapic_renumber_irq(apic
, irq
);
1046 #ifdef CONFIG_X86_32
1048 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1050 if ((pin
>= 16) && (pin
<= 23)) {
1051 if (pirq_entries
[pin
-16] != -1) {
1052 if (!pirq_entries
[pin
-16]) {
1053 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1054 "disabling PIRQ%d\n", pin
-16);
1056 irq
= pirq_entries
[pin
-16];
1057 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1058 "using PIRQ%d -> IRQ %d\n",
1069 * Find a specific PCI IRQ entry.
1070 * Not an __init, possibly needed by modules
1072 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1073 struct io_apic_irq_attr
*irq_attr
)
1075 int apic
, i
, best_guess
= -1;
1077 apic_printk(APIC_DEBUG
,
1078 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1080 if (test_bit(bus
, mp_bus_not_pci
)) {
1081 apic_printk(APIC_VERBOSE
,
1082 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1085 for (i
= 0; i
< mp_irq_entries
; i
++) {
1086 int lbus
= mp_irqs
[i
].srcbus
;
1088 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1089 if (mp_ioapics
[apic
].apicid
== mp_irqs
[i
].dstapic
||
1090 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1093 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1094 !mp_irqs
[i
].irqtype
&&
1096 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1097 int irq
= pin_2_irq(i
, apic
, mp_irqs
[i
].dstirq
);
1099 if (!(apic
|| IO_APIC_IRQ(irq
)))
1102 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1103 set_io_apic_irq_attr(irq_attr
, apic
,
1110 * Use the first all-but-pin matching entry as a
1111 * best-guess fuzzy result for broken mptables.
1113 if (best_guess
< 0) {
1114 set_io_apic_irq_attr(irq_attr
, apic
,
1124 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1126 void lock_vector_lock(void)
1128 /* Used to the online set of cpus does not change
1129 * during assign_irq_vector.
1131 raw_spin_lock(&vector_lock
);
1134 void unlock_vector_lock(void)
1136 raw_spin_unlock(&vector_lock
);
1140 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1143 * NOTE! The local APIC isn't very good at handling
1144 * multiple interrupts at the same interrupt level.
1145 * As the interrupt level is determined by taking the
1146 * vector number and shifting that right by 4, we
1147 * want to spread these out a bit so that they don't
1148 * all fall in the same interrupt level.
1150 * Also, we've got to be careful not to trash gate
1151 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1153 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1154 static int current_offset
= VECTOR_OFFSET_START
% 8;
1155 unsigned int old_vector
;
1157 cpumask_var_t tmp_mask
;
1159 if (cfg
->move_in_progress
)
1162 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1165 old_vector
= cfg
->vector
;
1167 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1168 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1169 if (!cpumask_empty(tmp_mask
)) {
1170 free_cpumask_var(tmp_mask
);
1175 /* Only try and allocate irqs on cpus that are present */
1177 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1181 apic
->vector_allocation_domain(cpu
, tmp_mask
);
1183 vector
= current_vector
;
1184 offset
= current_offset
;
1187 if (vector
>= first_system_vector
) {
1188 /* If out of vectors on large boxen, must share them. */
1189 offset
= (offset
+ 1) % 8;
1190 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1192 if (unlikely(current_vector
== vector
))
1195 if (test_bit(vector
, used_vectors
))
1198 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1199 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1202 current_vector
= vector
;
1203 current_offset
= offset
;
1205 cfg
->move_in_progress
= 1;
1206 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1208 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1209 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1210 cfg
->vector
= vector
;
1211 cpumask_copy(cfg
->domain
, tmp_mask
);
1215 free_cpumask_var(tmp_mask
);
1219 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1222 unsigned long flags
;
1224 raw_spin_lock_irqsave(&vector_lock
, flags
);
1225 err
= __assign_irq_vector(irq
, cfg
, mask
);
1226 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1230 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1234 BUG_ON(!cfg
->vector
);
1236 vector
= cfg
->vector
;
1237 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1238 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1241 cpumask_clear(cfg
->domain
);
1243 if (likely(!cfg
->move_in_progress
))
1245 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1246 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1248 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1250 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1254 cfg
->move_in_progress
= 0;
1257 void __setup_vector_irq(int cpu
)
1259 /* Initialize vector_irq on a new cpu */
1261 struct irq_cfg
*cfg
;
1262 struct irq_desc
*desc
;
1265 * vector_lock will make sure that we don't run into irq vector
1266 * assignments that might be happening on another cpu in parallel,
1267 * while we setup our initial vector to irq mappings.
1269 raw_spin_lock(&vector_lock
);
1270 /* Mark the inuse vectors */
1271 for_each_irq_desc(irq
, desc
) {
1272 cfg
= desc
->chip_data
;
1273 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1275 vector
= cfg
->vector
;
1276 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1278 /* Mark the free vectors */
1279 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1280 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1285 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1286 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1288 raw_spin_unlock(&vector_lock
);
1291 static struct irq_chip ioapic_chip
;
1292 static struct irq_chip ir_ioapic_chip
;
1294 #define IOAPIC_AUTO -1
1295 #define IOAPIC_EDGE 0
1296 #define IOAPIC_LEVEL 1
1298 #ifdef CONFIG_X86_32
1299 static inline int IO_APIC_irq_trigger(int irq
)
1303 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1304 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1305 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1306 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1307 return irq_trigger(idx
);
1311 * nonexistent IRQs are edge default
1316 static inline int IO_APIC_irq_trigger(int irq
)
1322 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1325 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1326 trigger
== IOAPIC_LEVEL
)
1327 desc
->status
|= IRQ_LEVEL
;
1329 desc
->status
&= ~IRQ_LEVEL
;
1331 if (irq_remapped(irq
)) {
1332 desc
->status
|= IRQ_MOVE_PCNTXT
;
1334 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1338 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1339 handle_edge_irq
, "edge");
1343 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1344 trigger
== IOAPIC_LEVEL
)
1345 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1349 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1350 handle_edge_irq
, "edge");
1353 int setup_ioapic_entry(int apic_id
, int irq
,
1354 struct IO_APIC_route_entry
*entry
,
1355 unsigned int destination
, int trigger
,
1356 int polarity
, int vector
, int pin
)
1359 * add it to the IO-APIC irq-routing table:
1361 memset(entry
,0,sizeof(*entry
));
1363 if (intr_remapping_enabled
) {
1364 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic_id
);
1366 struct IR_IO_APIC_route_entry
*ir_entry
=
1367 (struct IR_IO_APIC_route_entry
*) entry
;
1371 panic("No mapping iommu for ioapic %d\n", apic_id
);
1373 index
= alloc_irte(iommu
, irq
, 1);
1375 panic("Failed to allocate IRTE for ioapic %d\n", apic_id
);
1377 memset(&irte
, 0, sizeof(irte
));
1380 irte
.dst_mode
= apic
->irq_dest_mode
;
1382 * Trigger mode in the IRTE will always be edge, and the
1383 * actual level or edge trigger will be setup in the IO-APIC
1384 * RTE. This will help simplify level triggered irq migration.
1385 * For more details, see the comments above explainig IO-APIC
1386 * irq migration in the presence of interrupt-remapping.
1388 irte
.trigger_mode
= 0;
1389 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
1390 irte
.vector
= vector
;
1391 irte
.dest_id
= IRTE_DEST(destination
);
1393 /* Set source-id of interrupt request */
1394 set_ioapic_sid(&irte
, apic_id
);
1396 modify_irte(irq
, &irte
);
1398 ir_entry
->index2
= (index
>> 15) & 0x1;
1400 ir_entry
->format
= 1;
1401 ir_entry
->index
= (index
& 0x7fff);
1403 * IO-APIC RTE will be configured with virtual vector.
1404 * irq handler will do the explicit EOI to the io-apic.
1406 ir_entry
->vector
= pin
;
1408 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1409 entry
->dest_mode
= apic
->irq_dest_mode
;
1410 entry
->dest
= destination
;
1411 entry
->vector
= vector
;
1414 entry
->mask
= 0; /* enable IRQ */
1415 entry
->trigger
= trigger
;
1416 entry
->polarity
= polarity
;
1418 /* Mask level triggered irqs.
1419 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1426 static void setup_IO_APIC_irq(int apic_id
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1427 int trigger
, int polarity
)
1429 struct irq_cfg
*cfg
;
1430 struct IO_APIC_route_entry entry
;
1433 if (!IO_APIC_IRQ(irq
))
1436 cfg
= desc
->chip_data
;
1439 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1440 * controllers like 8259. Now that IO-APIC can handle this irq, update
1443 if (irq
< nr_legacy_irqs
&& cpumask_test_cpu(0, cfg
->domain
))
1444 apic
->vector_allocation_domain(0, cfg
->domain
);
1446 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1449 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
1451 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1452 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1453 "IRQ %d Mode:%i Active:%i)\n",
1454 apic_id
, mp_ioapics
[apic_id
].apicid
, pin
, cfg
->vector
,
1455 irq
, trigger
, polarity
);
1458 if (setup_ioapic_entry(mp_ioapics
[apic_id
].apicid
, irq
, &entry
,
1459 dest
, trigger
, polarity
, cfg
->vector
, pin
)) {
1460 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1461 mp_ioapics
[apic_id
].apicid
, pin
);
1462 __clear_irq_vector(irq
, cfg
);
1466 ioapic_register_intr(irq
, desc
, trigger
);
1467 if (irq
< legacy_pic
->nr_legacy_irqs
)
1468 legacy_pic
->chip
->mask(irq
);
1470 ioapic_write_entry(apic_id
, pin
, entry
);
1474 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
1475 } mp_ioapic_routing
[MAX_IO_APICS
];
1477 static void __init
setup_IO_APIC_irqs(void)
1479 int apic_id
= 0, pin
, idx
, irq
;
1481 struct irq_desc
*desc
;
1482 struct irq_cfg
*cfg
;
1483 int node
= cpu_to_node(boot_cpu_id
);
1485 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1488 if (!acpi_disabled
&& acpi_ioapic
) {
1489 apic_id
= mp_find_ioapic(0);
1495 for (pin
= 0; pin
< nr_ioapic_registers
[apic_id
]; pin
++) {
1496 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1500 apic_printk(APIC_VERBOSE
,
1501 KERN_DEBUG
" %d-%d",
1502 mp_ioapics
[apic_id
].apicid
, pin
);
1504 apic_printk(APIC_VERBOSE
, " %d-%d",
1505 mp_ioapics
[apic_id
].apicid
, pin
);
1509 apic_printk(APIC_VERBOSE
,
1510 " (apicid-pin) not connected\n");
1514 irq
= pin_2_irq(idx
, apic_id
, pin
);
1517 * Skip the timer IRQ if there's a quirk handler
1518 * installed and if it returns 1:
1520 if (apic
->multi_timer_check
&&
1521 apic
->multi_timer_check(apic_id
, irq
))
1524 desc
= irq_to_desc_alloc_node(irq
, node
);
1526 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1529 cfg
= desc
->chip_data
;
1530 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1532 * don't mark it in pin_programmed, so later acpi could
1533 * set it correctly when irq < 16
1535 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1536 irq_trigger(idx
), irq_polarity(idx
));
1540 apic_printk(APIC_VERBOSE
,
1541 " (apicid-pin) not connected\n");
1545 * for the gsit that is not in first ioapic
1546 * but could not use acpi_register_gsi()
1547 * like some special sci in IBM x3330
1549 void setup_IO_APIC_irq_extra(u32 gsi
)
1551 int apic_id
= 0, pin
, idx
, irq
;
1552 int node
= cpu_to_node(boot_cpu_id
);
1553 struct irq_desc
*desc
;
1554 struct irq_cfg
*cfg
;
1557 * Convert 'gsi' to 'ioapic.pin'.
1559 apic_id
= mp_find_ioapic(gsi
);
1563 pin
= mp_find_ioapic_pin(apic_id
, gsi
);
1564 idx
= find_irq_entry(apic_id
, pin
, mp_INT
);
1568 irq
= pin_2_irq(idx
, apic_id
, pin
);
1569 #ifdef CONFIG_SPARSE_IRQ
1570 desc
= irq_to_desc(irq
);
1574 desc
= irq_to_desc_alloc_node(irq
, node
);
1576 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1580 cfg
= desc
->chip_data
;
1581 add_pin_to_irq_node(cfg
, node
, apic_id
, pin
);
1583 if (test_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
)) {
1584 pr_debug("Pin %d-%d already programmed\n",
1585 mp_ioapics
[apic_id
].apicid
, pin
);
1588 set_bit(pin
, mp_ioapic_routing
[apic_id
].pin_programmed
);
1590 setup_IO_APIC_irq(apic_id
, pin
, irq
, desc
,
1591 irq_trigger(idx
), irq_polarity(idx
));
1595 * Set up the timer pin, possibly with the 8259A-master behind.
1597 static void __init
setup_timer_IRQ0_pin(unsigned int apic_id
, unsigned int pin
,
1600 struct IO_APIC_route_entry entry
;
1602 if (intr_remapping_enabled
)
1605 memset(&entry
, 0, sizeof(entry
));
1608 * We use logical delivery to get the timer IRQ
1611 entry
.dest_mode
= apic
->irq_dest_mode
;
1612 entry
.mask
= 0; /* don't mask IRQ for edge */
1613 entry
.dest
= apic
->cpu_mask_to_apicid(apic
->target_cpus());
1614 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1617 entry
.vector
= vector
;
1620 * The timer IRQ doesn't have to know that behind the
1621 * scene we may have a 8259A-master in AEOI mode ...
1623 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1626 * Add it to the IO-APIC irq-routing table:
1628 ioapic_write_entry(apic_id
, pin
, entry
);
1632 __apicdebuginit(void) print_IO_APIC(void)
1635 union IO_APIC_reg_00 reg_00
;
1636 union IO_APIC_reg_01 reg_01
;
1637 union IO_APIC_reg_02 reg_02
;
1638 union IO_APIC_reg_03 reg_03
;
1639 unsigned long flags
;
1640 struct irq_cfg
*cfg
;
1641 struct irq_desc
*desc
;
1644 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1645 for (i
= 0; i
< nr_ioapics
; i
++)
1646 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1647 mp_ioapics
[i
].apicid
, nr_ioapic_registers
[i
]);
1650 * We are a bit conservative about what we expect. We have to
1651 * know about every hardware change ASAP.
1653 printk(KERN_INFO
"testing the IO APIC.......................\n");
1655 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1657 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1658 reg_00
.raw
= io_apic_read(apic
, 0);
1659 reg_01
.raw
= io_apic_read(apic
, 1);
1660 if (reg_01
.bits
.version
>= 0x10)
1661 reg_02
.raw
= io_apic_read(apic
, 2);
1662 if (reg_01
.bits
.version
>= 0x20)
1663 reg_03
.raw
= io_apic_read(apic
, 3);
1664 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1667 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].apicid
);
1668 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1669 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1670 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1671 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1673 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1674 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1676 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1677 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1680 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1681 * but the value of reg_02 is read as the previous read register
1682 * value, so ignore it if reg_02 == reg_01.
1684 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1685 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1686 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1690 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1691 * or reg_03, but the value of reg_0[23] is read as the previous read
1692 * register value, so ignore it if reg_03 == reg_0[12].
1694 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1695 reg_03
.raw
!= reg_01
.raw
) {
1696 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1697 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1700 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1702 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1703 " Stat Dmod Deli Vect: \n");
1705 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1706 struct IO_APIC_route_entry entry
;
1708 entry
= ioapic_read_entry(apic
, i
);
1710 printk(KERN_DEBUG
" %02x %03X ",
1715 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1720 entry
.delivery_status
,
1722 entry
.delivery_mode
,
1727 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1728 for_each_irq_desc(irq
, desc
) {
1729 struct irq_pin_list
*entry
;
1731 cfg
= desc
->chip_data
;
1732 entry
= cfg
->irq_2_pin
;
1735 printk(KERN_DEBUG
"IRQ%d ", irq
);
1736 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1737 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1741 printk(KERN_INFO
".................................... done.\n");
1746 __apicdebuginit(void) print_APIC_field(int base
)
1752 for (i
= 0; i
< 8; i
++)
1753 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1755 printk(KERN_CONT
"\n");
1758 __apicdebuginit(void) print_local_APIC(void *dummy
)
1760 unsigned int i
, v
, ver
, maxlvt
;
1763 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1764 smp_processor_id(), hard_smp_processor_id());
1765 v
= apic_read(APIC_ID
);
1766 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1767 v
= apic_read(APIC_LVR
);
1768 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1769 ver
= GET_APIC_VERSION(v
);
1770 maxlvt
= lapic_get_maxlvt();
1772 v
= apic_read(APIC_TASKPRI
);
1773 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1775 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1776 if (!APIC_XAPIC(ver
)) {
1777 v
= apic_read(APIC_ARBPRI
);
1778 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1779 v
& APIC_ARBPRI_MASK
);
1781 v
= apic_read(APIC_PROCPRI
);
1782 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1786 * Remote read supported only in the 82489DX and local APIC for
1787 * Pentium processors.
1789 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1790 v
= apic_read(APIC_RRR
);
1791 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1794 v
= apic_read(APIC_LDR
);
1795 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1796 if (!x2apic_enabled()) {
1797 v
= apic_read(APIC_DFR
);
1798 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1800 v
= apic_read(APIC_SPIV
);
1801 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1803 printk(KERN_DEBUG
"... APIC ISR field:\n");
1804 print_APIC_field(APIC_ISR
);
1805 printk(KERN_DEBUG
"... APIC TMR field:\n");
1806 print_APIC_field(APIC_TMR
);
1807 printk(KERN_DEBUG
"... APIC IRR field:\n");
1808 print_APIC_field(APIC_IRR
);
1810 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1811 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1812 apic_write(APIC_ESR
, 0);
1814 v
= apic_read(APIC_ESR
);
1815 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1818 icr
= apic_icr_read();
1819 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1820 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1822 v
= apic_read(APIC_LVTT
);
1823 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1825 if (maxlvt
> 3) { /* PC is LVT#4. */
1826 v
= apic_read(APIC_LVTPC
);
1827 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1829 v
= apic_read(APIC_LVT0
);
1830 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1831 v
= apic_read(APIC_LVT1
);
1832 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1834 if (maxlvt
> 2) { /* ERR is LVT#3. */
1835 v
= apic_read(APIC_LVTERR
);
1836 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1839 v
= apic_read(APIC_TMICT
);
1840 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1841 v
= apic_read(APIC_TMCCT
);
1842 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1843 v
= apic_read(APIC_TDCR
);
1844 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1846 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1847 v
= apic_read(APIC_EFEAT
);
1848 maxlvt
= (v
>> 16) & 0xff;
1849 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1850 v
= apic_read(APIC_ECTRL
);
1851 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1852 for (i
= 0; i
< maxlvt
; i
++) {
1853 v
= apic_read(APIC_EILVTn(i
));
1854 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1860 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1868 for_each_online_cpu(cpu
) {
1871 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1876 __apicdebuginit(void) print_PIC(void)
1879 unsigned long flags
;
1881 if (!legacy_pic
->nr_legacy_irqs
)
1884 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1886 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1888 v
= inb(0xa1) << 8 | inb(0x21);
1889 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1891 v
= inb(0xa0) << 8 | inb(0x20);
1892 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1896 v
= inb(0xa0) << 8 | inb(0x20);
1900 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1902 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1904 v
= inb(0x4d1) << 8 | inb(0x4d0);
1905 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1908 static int __initdata show_lapic
= 1;
1909 static __init
int setup_show_lapic(char *arg
)
1913 if (strcmp(arg
, "all") == 0) {
1914 show_lapic
= CONFIG_NR_CPUS
;
1916 get_option(&arg
, &num
);
1923 __setup("show_lapic=", setup_show_lapic
);
1925 __apicdebuginit(int) print_ICs(void)
1927 if (apic_verbosity
== APIC_QUIET
)
1932 /* don't print out if apic is not there */
1933 if (!cpu_has_apic
&& !apic_from_smp_config())
1936 print_local_APICs(show_lapic
);
1942 fs_initcall(print_ICs
);
1945 /* Where if anywhere is the i8259 connect in external int mode */
1946 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1948 void __init
enable_IO_APIC(void)
1950 union IO_APIC_reg_01 reg_01
;
1951 int i8259_apic
, i8259_pin
;
1953 unsigned long flags
;
1956 * The number of IO-APIC IRQ registers (== #pins):
1958 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1959 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1960 reg_01
.raw
= io_apic_read(apic
, 1);
1961 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1962 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1965 if (!legacy_pic
->nr_legacy_irqs
)
1968 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1970 /* See if any of the pins is in ExtINT mode */
1971 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1972 struct IO_APIC_route_entry entry
;
1973 entry
= ioapic_read_entry(apic
, pin
);
1975 /* If the interrupt line is enabled and in ExtInt mode
1976 * I have found the pin where the i8259 is connected.
1978 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1979 ioapic_i8259
.apic
= apic
;
1980 ioapic_i8259
.pin
= pin
;
1986 /* Look to see what if the MP table has reported the ExtINT */
1987 /* If we could not find the appropriate pin by looking at the ioapic
1988 * the i8259 probably is not connected the ioapic but give the
1989 * mptable a chance anyway.
1991 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1992 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1993 /* Trust the MP table if nothing is setup in the hardware */
1994 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1995 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1996 ioapic_i8259
.pin
= i8259_pin
;
1997 ioapic_i8259
.apic
= i8259_apic
;
1999 /* Complain if the MP table and the hardware disagree */
2000 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2001 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2003 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2007 * Do not trust the IO-APIC being empty at bootup
2013 * Not an __init, needed by the reboot code
2015 void disable_IO_APIC(void)
2018 * Clear the IO-APIC before rebooting:
2022 if (!legacy_pic
->nr_legacy_irqs
)
2026 * If the i8259 is routed through an IOAPIC
2027 * Put that IOAPIC in virtual wire mode
2028 * so legacy interrupts can be delivered.
2030 * With interrupt-remapping, for now we will use virtual wire A mode,
2031 * as virtual wire B is little complex (need to configure both
2032 * IOAPIC RTE aswell as interrupt-remapping table entry).
2033 * As this gets called during crash dump, keep this simple for now.
2035 if (ioapic_i8259
.pin
!= -1 && !intr_remapping_enabled
) {
2036 struct IO_APIC_route_entry entry
;
2038 memset(&entry
, 0, sizeof(entry
));
2039 entry
.mask
= 0; /* Enabled */
2040 entry
.trigger
= 0; /* Edge */
2042 entry
.polarity
= 0; /* High */
2043 entry
.delivery_status
= 0;
2044 entry
.dest_mode
= 0; /* Physical */
2045 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2047 entry
.dest
= read_apic_id();
2050 * Add it to the IO-APIC irq-routing table:
2052 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2056 * Use virtual wire A mode when interrupt remapping is enabled.
2058 if (cpu_has_apic
|| apic_from_smp_config())
2059 disconnect_bsp_APIC(!intr_remapping_enabled
&&
2060 ioapic_i8259
.pin
!= -1);
2063 #ifdef CONFIG_X86_32
2065 * function to set the IO-APIC physical IDs based on the
2066 * values stored in the MPC table.
2068 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2071 void __init
setup_ioapic_ids_from_mpc(void)
2073 union IO_APIC_reg_00 reg_00
;
2074 physid_mask_t phys_id_present_map
;
2077 unsigned char old_id
;
2078 unsigned long flags
;
2083 * Don't check I/O APIC IDs for xAPIC systems. They have
2084 * no meaning without the serial APIC bus.
2086 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2087 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2090 * This is broken; anything with a real cpu count has to
2091 * circumvent this idiocy regardless.
2093 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2096 * Set the IOAPIC ID to the value stored in the MPC table.
2098 for (apic_id
= 0; apic_id
< nr_ioapics
; apic_id
++) {
2100 /* Read the register 0 value */
2101 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2102 reg_00
.raw
= io_apic_read(apic_id
, 0);
2103 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2105 old_id
= mp_ioapics
[apic_id
].apicid
;
2107 if (mp_ioapics
[apic_id
].apicid
>= get_physical_broadcast()) {
2108 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2109 apic_id
, mp_ioapics
[apic_id
].apicid
);
2110 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2112 mp_ioapics
[apic_id
].apicid
= reg_00
.bits
.ID
;
2116 * Sanity check, is the ID really free? Every APIC in a
2117 * system must have a unique ID or we get lots of nice
2118 * 'stuck on smp_invalidate_needed IPI wait' messages.
2120 if (apic
->check_apicid_used(&phys_id_present_map
,
2121 mp_ioapics
[apic_id
].apicid
)) {
2122 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2123 apic_id
, mp_ioapics
[apic_id
].apicid
);
2124 for (i
= 0; i
< get_physical_broadcast(); i
++)
2125 if (!physid_isset(i
, phys_id_present_map
))
2127 if (i
>= get_physical_broadcast())
2128 panic("Max APIC ID exceeded!\n");
2129 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2131 physid_set(i
, phys_id_present_map
);
2132 mp_ioapics
[apic_id
].apicid
= i
;
2135 apic
->apicid_to_cpu_present(mp_ioapics
[apic_id
].apicid
, &tmp
);
2136 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2137 "phys_id_present_map\n",
2138 mp_ioapics
[apic_id
].apicid
);
2139 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2144 * We need to adjust the IRQ routing table
2145 * if the ID changed.
2147 if (old_id
!= mp_ioapics
[apic_id
].apicid
)
2148 for (i
= 0; i
< mp_irq_entries
; i
++)
2149 if (mp_irqs
[i
].dstapic
== old_id
)
2151 = mp_ioapics
[apic_id
].apicid
;
2154 * Read the right value from the MPC table and
2155 * write it into the ID register.
2157 apic_printk(APIC_VERBOSE
, KERN_INFO
2158 "...changing IO-APIC physical APIC ID to %d ...",
2159 mp_ioapics
[apic_id
].apicid
);
2161 reg_00
.bits
.ID
= mp_ioapics
[apic_id
].apicid
;
2162 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2163 io_apic_write(apic_id
, 0, reg_00
.raw
);
2164 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2169 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2170 reg_00
.raw
= io_apic_read(apic_id
, 0);
2171 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2172 if (reg_00
.bits
.ID
!= mp_ioapics
[apic_id
].apicid
)
2173 printk("could not set ID!\n");
2175 apic_printk(APIC_VERBOSE
, " ok.\n");
2180 int no_timer_check __initdata
;
2182 static int __init
notimercheck(char *s
)
2187 __setup("no_timer_check", notimercheck
);
2190 * There is a nasty bug in some older SMP boards, their mptable lies
2191 * about the timer IRQ. We do the following to work around the situation:
2193 * - timer IRQ defaults to IO-APIC IRQ
2194 * - if this function detects that timer IRQs are defunct, then we fall
2195 * back to ISA timer IRQs
2197 static int __init
timer_irq_works(void)
2199 unsigned long t1
= jiffies
;
2200 unsigned long flags
;
2205 local_save_flags(flags
);
2207 /* Let ten ticks pass... */
2208 mdelay((10 * 1000) / HZ
);
2209 local_irq_restore(flags
);
2212 * Expect a few ticks at least, to be sure some possible
2213 * glue logic does not lock up after one or two first
2214 * ticks in a non-ExtINT mode. Also the local APIC
2215 * might have cached one ExtINT interrupt. Finally, at
2216 * least one tick may be lost due to delays.
2220 if (time_after(jiffies
, t1
+ 4))
2226 * In the SMP+IOAPIC case it might happen that there are an unspecified
2227 * number of pending IRQ events unhandled. These cases are very rare,
2228 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2229 * better to do it this way as thus we do not have to be aware of
2230 * 'pending' interrupts in the IRQ path, except at this point.
2233 * Edge triggered needs to resend any interrupt
2234 * that was delayed but this is now handled in the device
2239 * Starting up a edge-triggered IO-APIC interrupt is
2240 * nasty - we need to make sure that we get the edge.
2241 * If it is already asserted for some reason, we need
2242 * return 1 to indicate that is was pending.
2244 * This is not complete - we should be able to fake
2245 * an edge even if it isn't on the 8259A...
2248 static unsigned int startup_ioapic_irq(unsigned int irq
)
2250 int was_pending
= 0;
2251 unsigned long flags
;
2252 struct irq_cfg
*cfg
;
2254 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2255 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2256 legacy_pic
->chip
->mask(irq
);
2257 if (legacy_pic
->irq_pending(irq
))
2261 __unmask_IO_APIC_irq(cfg
);
2262 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2267 static int ioapic_retrigger_irq(unsigned int irq
)
2270 struct irq_cfg
*cfg
= irq_cfg(irq
);
2271 unsigned long flags
;
2273 raw_spin_lock_irqsave(&vector_lock
, flags
);
2274 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2275 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2281 * Level and edge triggered IO-APIC interrupts need different handling,
2282 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2283 * handled with the level-triggered descriptor, but that one has slightly
2284 * more overhead. Level-triggered interrupts cannot be handled with the
2285 * edge-triggered handler, without risking IRQ storms and other ugly
2290 void send_cleanup_vector(struct irq_cfg
*cfg
)
2292 cpumask_var_t cleanup_mask
;
2294 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2296 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2297 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2299 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2300 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2301 free_cpumask_var(cleanup_mask
);
2303 cfg
->move_in_progress
= 0;
2306 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2309 struct irq_pin_list
*entry
;
2310 u8 vector
= cfg
->vector
;
2312 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2318 * With interrupt-remapping, destination information comes
2319 * from interrupt-remapping table entry.
2321 if (!irq_remapped(irq
))
2322 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2323 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2324 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2326 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2331 * Either sets desc->affinity to a valid value, and returns
2332 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2333 * leaves desc->affinity untouched.
2336 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
,
2337 unsigned int *dest_id
)
2339 struct irq_cfg
*cfg
;
2342 if (!cpumask_intersects(mask
, cpu_online_mask
))
2346 cfg
= desc
->chip_data
;
2347 if (assign_irq_vector(irq
, cfg
, mask
))
2350 cpumask_copy(desc
->affinity
, mask
);
2352 *dest_id
= apic
->cpu_mask_to_apicid_and(desc
->affinity
, cfg
->domain
);
2357 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2359 struct irq_cfg
*cfg
;
2360 unsigned long flags
;
2366 cfg
= desc
->chip_data
;
2368 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2369 ret
= set_desc_affinity(desc
, mask
, &dest
);
2371 /* Only the high 8 bits are valid. */
2372 dest
= SET_APIC_LOGICAL_ID(dest
);
2373 __target_IO_APIC_irq(irq
, dest
, cfg
);
2375 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2381 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
2383 struct irq_desc
*desc
;
2385 desc
= irq_to_desc(irq
);
2387 return set_ioapic_affinity_irq_desc(desc
, mask
);
2390 #ifdef CONFIG_INTR_REMAP
2393 * Migrate the IO-APIC irq in the presence of intr-remapping.
2395 * For both level and edge triggered, irq migration is a simple atomic
2396 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2398 * For level triggered, we eliminate the io-apic RTE modification (with the
2399 * updated vector information), by using a virtual vector (io-apic pin number).
2400 * Real vector that is used for interrupting cpu will be coming from
2401 * the interrupt-remapping table entry.
2404 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2406 struct irq_cfg
*cfg
;
2412 if (!cpumask_intersects(mask
, cpu_online_mask
))
2416 if (get_irte(irq
, &irte
))
2419 cfg
= desc
->chip_data
;
2420 if (assign_irq_vector(irq
, cfg
, mask
))
2423 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2425 irte
.vector
= cfg
->vector
;
2426 irte
.dest_id
= IRTE_DEST(dest
);
2429 * Modified the IRTE and flushes the Interrupt entry cache.
2431 modify_irte(irq
, &irte
);
2433 if (cfg
->move_in_progress
)
2434 send_cleanup_vector(cfg
);
2436 cpumask_copy(desc
->affinity
, mask
);
2442 * Migrates the IRQ destination in the process context.
2444 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2445 const struct cpumask
*mask
)
2447 return migrate_ioapic_irq_desc(desc
, mask
);
2449 static int set_ir_ioapic_affinity_irq(unsigned int irq
,
2450 const struct cpumask
*mask
)
2452 struct irq_desc
*desc
= irq_to_desc(irq
);
2454 return set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2457 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2458 const struct cpumask
*mask
)
2464 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2466 unsigned vector
, me
;
2472 me
= smp_processor_id();
2473 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2476 struct irq_desc
*desc
;
2477 struct irq_cfg
*cfg
;
2478 irq
= __get_cpu_var(vector_irq
)[vector
];
2483 desc
= irq_to_desc(irq
);
2488 raw_spin_lock(&desc
->lock
);
2491 * Check if the irq migration is in progress. If so, we
2492 * haven't received the cleanup request yet for this irq.
2494 if (cfg
->move_in_progress
)
2497 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2500 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2502 * Check if the vector that needs to be cleanedup is
2503 * registered at the cpu's IRR. If so, then this is not
2504 * the best time to clean it up. Lets clean it up in the
2505 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2508 if (irr
& (1 << (vector
% 32))) {
2509 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2512 __get_cpu_var(vector_irq
)[vector
] = -1;
2514 raw_spin_unlock(&desc
->lock
);
2520 static void __irq_complete_move(struct irq_desc
**descp
, unsigned vector
)
2522 struct irq_desc
*desc
= *descp
;
2523 struct irq_cfg
*cfg
= desc
->chip_data
;
2526 if (likely(!cfg
->move_in_progress
))
2529 me
= smp_processor_id();
2531 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2532 send_cleanup_vector(cfg
);
2535 static void irq_complete_move(struct irq_desc
**descp
)
2537 __irq_complete_move(descp
, ~get_irq_regs()->orig_ax
);
2540 void irq_force_complete_move(int irq
)
2542 struct irq_desc
*desc
= irq_to_desc(irq
);
2543 struct irq_cfg
*cfg
= desc
->chip_data
;
2545 __irq_complete_move(&desc
, cfg
->vector
);
2548 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2551 static void ack_apic_edge(unsigned int irq
)
2553 struct irq_desc
*desc
= irq_to_desc(irq
);
2555 irq_complete_move(&desc
);
2556 move_native_irq(irq
);
2560 atomic_t irq_mis_count
;
2563 * IO-APIC versions below 0x20 don't support EOI register.
2564 * For the record, here is the information about various versions:
2566 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2567 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2570 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2571 * version as 0x2. This is an error with documentation and these ICH chips
2572 * use io-apic's of version 0x20.
2574 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2575 * Otherwise, we simulate the EOI message manually by changing the trigger
2576 * mode to edge and then back to level, with RTE being masked during this.
2578 static void __eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
2580 struct irq_pin_list
*entry
;
2582 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2583 if (mp_ioapics
[entry
->apic
].apicver
>= 0x20) {
2585 * Intr-remapping uses pin number as the virtual vector
2586 * in the RTE. Actual vector is programmed in
2587 * intr-remapping table entry. Hence for the io-apic
2588 * EOI we use the pin number.
2590 if (irq_remapped(irq
))
2591 io_apic_eoi(entry
->apic
, entry
->pin
);
2593 io_apic_eoi(entry
->apic
, cfg
->vector
);
2595 __mask_and_edge_IO_APIC_irq(entry
);
2596 __unmask_and_level_IO_APIC_irq(entry
);
2601 static void eoi_ioapic_irq(struct irq_desc
*desc
)
2603 struct irq_cfg
*cfg
;
2604 unsigned long flags
;
2608 cfg
= desc
->chip_data
;
2610 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2611 __eoi_ioapic_irq(irq
, cfg
);
2612 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2615 static void ack_apic_level(unsigned int irq
)
2617 struct irq_desc
*desc
= irq_to_desc(irq
);
2620 struct irq_cfg
*cfg
;
2621 int do_unmask_irq
= 0;
2623 irq_complete_move(&desc
);
2624 #ifdef CONFIG_GENERIC_PENDING_IRQ
2625 /* If we are moving the irq we need to mask it */
2626 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2628 mask_IO_APIC_irq_desc(desc
);
2633 * It appears there is an erratum which affects at least version 0x11
2634 * of I/O APIC (that's the 82093AA and cores integrated into various
2635 * chipsets). Under certain conditions a level-triggered interrupt is
2636 * erroneously delivered as edge-triggered one but the respective IRR
2637 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2638 * message but it will never arrive and further interrupts are blocked
2639 * from the source. The exact reason is so far unknown, but the
2640 * phenomenon was observed when two consecutive interrupt requests
2641 * from a given source get delivered to the same CPU and the source is
2642 * temporarily disabled in between.
2644 * A workaround is to simulate an EOI message manually. We achieve it
2645 * by setting the trigger mode to edge and then to level when the edge
2646 * trigger mode gets detected in the TMR of a local APIC for a
2647 * level-triggered interrupt. We mask the source for the time of the
2648 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2649 * The idea is from Manfred Spraul. --macro
2651 * Also in the case when cpu goes offline, fixup_irqs() will forward
2652 * any unhandled interrupt on the offlined cpu to the new cpu
2653 * destination that is handling the corresponding interrupt. This
2654 * interrupt forwarding is done via IPI's. Hence, in this case also
2655 * level-triggered io-apic interrupt will be seen as an edge
2656 * interrupt in the IRR. And we can't rely on the cpu's EOI
2657 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2658 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2659 * supporting EOI register, we do an explicit EOI to clear the
2660 * remote IRR and on IO-APIC's which don't have an EOI register,
2661 * we use the above logic (mask+edge followed by unmask+level) from
2662 * Manfred Spraul to clear the remote IRR.
2664 cfg
= desc
->chip_data
;
2666 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2669 * We must acknowledge the irq before we move it or the acknowledge will
2670 * not propagate properly.
2675 * Tail end of clearing remote IRR bit (either by delivering the EOI
2676 * message via io-apic EOI register write or simulating it using
2677 * mask+edge followed by unnask+level logic) manually when the
2678 * level triggered interrupt is seen as the edge triggered interrupt
2681 if (!(v
& (1 << (i
& 0x1f)))) {
2682 atomic_inc(&irq_mis_count
);
2684 eoi_ioapic_irq(desc
);
2687 /* Now we can move and renable the irq */
2688 if (unlikely(do_unmask_irq
)) {
2689 /* Only migrate the irq if the ack has been received.
2691 * On rare occasions the broadcast level triggered ack gets
2692 * delayed going to ioapics, and if we reprogram the
2693 * vector while Remote IRR is still set the irq will never
2696 * To prevent this scenario we read the Remote IRR bit
2697 * of the ioapic. This has two effects.
2698 * - On any sane system the read of the ioapic will
2699 * flush writes (and acks) going to the ioapic from
2701 * - We get to see if the ACK has actually been delivered.
2703 * Based on failed experiments of reprogramming the
2704 * ioapic entry from outside of irq context starting
2705 * with masking the ioapic entry and then polling until
2706 * Remote IRR was clear before reprogramming the
2707 * ioapic I don't trust the Remote IRR bit to be
2708 * completey accurate.
2710 * However there appears to be no other way to plug
2711 * this race, so if the Remote IRR bit is not
2712 * accurate and is causing problems then it is a hardware bug
2713 * and you can go talk to the chipset vendor about it.
2715 cfg
= desc
->chip_data
;
2716 if (!io_apic_level_ack_pending(cfg
))
2717 move_masked_irq(irq
);
2718 unmask_IO_APIC_irq_desc(desc
);
2722 #ifdef CONFIG_INTR_REMAP
2723 static void ir_ack_apic_edge(unsigned int irq
)
2728 static void ir_ack_apic_level(unsigned int irq
)
2730 struct irq_desc
*desc
= irq_to_desc(irq
);
2733 eoi_ioapic_irq(desc
);
2735 #endif /* CONFIG_INTR_REMAP */
2737 static struct irq_chip ioapic_chip __read_mostly
= {
2739 .startup
= startup_ioapic_irq
,
2740 .mask
= mask_IO_APIC_irq
,
2741 .unmask
= unmask_IO_APIC_irq
,
2742 .ack
= ack_apic_edge
,
2743 .eoi
= ack_apic_level
,
2745 .set_affinity
= set_ioapic_affinity_irq
,
2747 .retrigger
= ioapic_retrigger_irq
,
2750 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2751 .name
= "IR-IO-APIC",
2752 .startup
= startup_ioapic_irq
,
2753 .mask
= mask_IO_APIC_irq
,
2754 .unmask
= unmask_IO_APIC_irq
,
2755 #ifdef CONFIG_INTR_REMAP
2756 .ack
= ir_ack_apic_edge
,
2757 .eoi
= ir_ack_apic_level
,
2759 .set_affinity
= set_ir_ioapic_affinity_irq
,
2762 .retrigger
= ioapic_retrigger_irq
,
2765 static inline void init_IO_APIC_traps(void)
2768 struct irq_desc
*desc
;
2769 struct irq_cfg
*cfg
;
2772 * NOTE! The local APIC isn't very good at handling
2773 * multiple interrupts at the same interrupt level.
2774 * As the interrupt level is determined by taking the
2775 * vector number and shifting that right by 4, we
2776 * want to spread these out a bit so that they don't
2777 * all fall in the same interrupt level.
2779 * Also, we've got to be careful not to trash gate
2780 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2782 for_each_irq_desc(irq
, desc
) {
2783 cfg
= desc
->chip_data
;
2784 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2786 * Hmm.. We don't have an entry for this,
2787 * so default to an old-fashioned 8259
2788 * interrupt if we can..
2790 if (irq
< legacy_pic
->nr_legacy_irqs
)
2791 legacy_pic
->make_irq(irq
);
2793 /* Strange. Oh, well.. */
2794 desc
->chip
= &no_irq_chip
;
2800 * The local APIC irq-chip implementation:
2803 static void mask_lapic_irq(unsigned int irq
)
2807 v
= apic_read(APIC_LVT0
);
2808 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2811 static void unmask_lapic_irq(unsigned int irq
)
2815 v
= apic_read(APIC_LVT0
);
2816 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2819 static void ack_lapic_irq(unsigned int irq
)
2824 static struct irq_chip lapic_chip __read_mostly
= {
2825 .name
= "local-APIC",
2826 .mask
= mask_lapic_irq
,
2827 .unmask
= unmask_lapic_irq
,
2828 .ack
= ack_lapic_irq
,
2831 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2833 desc
->status
&= ~IRQ_LEVEL
;
2834 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2838 static void __init
setup_nmi(void)
2841 * Dirty trick to enable the NMI watchdog ...
2842 * We put the 8259A master into AEOI mode and
2843 * unmask on all local APICs LVT0 as NMI.
2845 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2846 * is from Maciej W. Rozycki - so we do not have to EOI from
2847 * the NMI handler or the timer interrupt.
2849 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2851 enable_NMI_through_LVT0();
2853 apic_printk(APIC_VERBOSE
, " done.\n");
2857 * This looks a bit hackish but it's about the only one way of sending
2858 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2859 * not support the ExtINT mode, unfortunately. We need to send these
2860 * cycles as some i82489DX-based boards have glue logic that keeps the
2861 * 8259A interrupt line asserted until INTA. --macro
2863 static inline void __init
unlock_ExtINT_logic(void)
2866 struct IO_APIC_route_entry entry0
, entry1
;
2867 unsigned char save_control
, save_freq_select
;
2869 pin
= find_isa_irq_pin(8, mp_INT
);
2874 apic
= find_isa_irq_apic(8, mp_INT
);
2880 entry0
= ioapic_read_entry(apic
, pin
);
2881 clear_IO_APIC_pin(apic
, pin
);
2883 memset(&entry1
, 0, sizeof(entry1
));
2885 entry1
.dest_mode
= 0; /* physical delivery */
2886 entry1
.mask
= 0; /* unmask IRQ now */
2887 entry1
.dest
= hard_smp_processor_id();
2888 entry1
.delivery_mode
= dest_ExtINT
;
2889 entry1
.polarity
= entry0
.polarity
;
2893 ioapic_write_entry(apic
, pin
, entry1
);
2895 save_control
= CMOS_READ(RTC_CONTROL
);
2896 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2897 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2899 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2904 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2908 CMOS_WRITE(save_control
, RTC_CONTROL
);
2909 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2910 clear_IO_APIC_pin(apic
, pin
);
2912 ioapic_write_entry(apic
, pin
, entry0
);
2915 static int disable_timer_pin_1 __initdata
;
2916 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2917 static int __init
disable_timer_pin_setup(char *arg
)
2919 disable_timer_pin_1
= 1;
2922 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2924 int timer_through_8259 __initdata
;
2927 * This code may look a bit paranoid, but it's supposed to cooperate with
2928 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2929 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2930 * fanatically on his truly buggy board.
2932 * FIXME: really need to revamp this for all platforms.
2934 static inline void __init
check_timer(void)
2936 struct irq_desc
*desc
= irq_to_desc(0);
2937 struct irq_cfg
*cfg
= desc
->chip_data
;
2938 int node
= cpu_to_node(boot_cpu_id
);
2939 int apic1
, pin1
, apic2
, pin2
;
2940 unsigned long flags
;
2943 local_irq_save(flags
);
2946 * get/set the timer IRQ vector:
2948 legacy_pic
->chip
->mask(0);
2949 assign_irq_vector(0, cfg
, apic
->target_cpus());
2952 * As IRQ0 is to be enabled in the 8259A, the virtual
2953 * wire has to be disabled in the local APIC. Also
2954 * timer interrupts need to be acknowledged manually in
2955 * the 8259A for the i82489DX when using the NMI
2956 * watchdog as that APIC treats NMIs as level-triggered.
2957 * The AEOI mode will finish them in the 8259A
2960 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2961 legacy_pic
->init(1);
2962 #ifdef CONFIG_X86_32
2966 ver
= apic_read(APIC_LVR
);
2967 ver
= GET_APIC_VERSION(ver
);
2968 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2972 pin1
= find_isa_irq_pin(0, mp_INT
);
2973 apic1
= find_isa_irq_apic(0, mp_INT
);
2974 pin2
= ioapic_i8259
.pin
;
2975 apic2
= ioapic_i8259
.apic
;
2977 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2978 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2979 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2982 * Some BIOS writers are clueless and report the ExtINTA
2983 * I/O APIC input from the cascaded 8259A as the timer
2984 * interrupt input. So just in case, if only one pin
2985 * was found above, try it both directly and through the
2989 if (intr_remapping_enabled
)
2990 panic("BIOS bug: timer not connected to IO-APIC");
2994 } else if (pin2
== -1) {
3001 * Ok, does IRQ0 through the IOAPIC work?
3004 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
3005 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
3007 /* for edge trigger, setup_IO_APIC_irq already
3008 * leave it unmasked.
3009 * so only need to unmask if it is level-trigger
3010 * do we really have level trigger timer?
3013 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
3014 if (idx
!= -1 && irq_trigger(idx
))
3015 unmask_IO_APIC_irq_desc(desc
);
3017 if (timer_irq_works()) {
3018 if (nmi_watchdog
== NMI_IO_APIC
) {
3020 legacy_pic
->chip
->unmask(0);
3022 if (disable_timer_pin_1
> 0)
3023 clear_IO_APIC_pin(0, pin1
);
3026 if (intr_remapping_enabled
)
3027 panic("timer doesn't work through Interrupt-remapped IO-APIC");
3028 local_irq_disable();
3029 clear_IO_APIC_pin(apic1
, pin1
);
3031 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
3032 "8254 timer not connected to IO-APIC\n");
3034 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
3035 "(IRQ0) through the 8259A ...\n");
3036 apic_printk(APIC_QUIET
, KERN_INFO
3037 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
3039 * legacy devices should be connected to IO APIC #0
3041 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
3042 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
3043 legacy_pic
->chip
->unmask(0);
3044 if (timer_irq_works()) {
3045 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
3046 timer_through_8259
= 1;
3047 if (nmi_watchdog
== NMI_IO_APIC
) {
3048 legacy_pic
->chip
->mask(0);
3050 legacy_pic
->chip
->unmask(0);
3055 * Cleanup, just in case ...
3057 local_irq_disable();
3058 legacy_pic
->chip
->mask(0);
3059 clear_IO_APIC_pin(apic2
, pin2
);
3060 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
3063 if (nmi_watchdog
== NMI_IO_APIC
) {
3064 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
3065 "through the IO-APIC - disabling NMI Watchdog!\n");
3066 nmi_watchdog
= NMI_NONE
;
3068 #ifdef CONFIG_X86_32
3072 apic_printk(APIC_QUIET
, KERN_INFO
3073 "...trying to set up timer as Virtual Wire IRQ...\n");
3075 lapic_register_intr(0, desc
);
3076 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
3077 legacy_pic
->chip
->unmask(0);
3079 if (timer_irq_works()) {
3080 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3083 local_irq_disable();
3084 legacy_pic
->chip
->mask(0);
3085 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3086 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3088 apic_printk(APIC_QUIET
, KERN_INFO
3089 "...trying to set up timer as ExtINT IRQ...\n");
3091 legacy_pic
->init(0);
3092 legacy_pic
->make_irq(0);
3093 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3095 unlock_ExtINT_logic();
3097 if (timer_irq_works()) {
3098 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3101 local_irq_disable();
3102 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3103 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3104 "report. Then try booting with the 'noapic' option.\n");
3106 local_irq_restore(flags
);
3110 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3111 * to devices. However there may be an I/O APIC pin available for
3112 * this interrupt regardless. The pin may be left unconnected, but
3113 * typically it will be reused as an ExtINT cascade interrupt for
3114 * the master 8259A. In the MPS case such a pin will normally be
3115 * reported as an ExtINT interrupt in the MP table. With ACPI
3116 * there is no provision for ExtINT interrupts, and in the absence
3117 * of an override it would be treated as an ordinary ISA I/O APIC
3118 * interrupt, that is edge-triggered and unmasked by default. We
3119 * used to do this, but it caused problems on some systems because
3120 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3121 * the same ExtINT cascade interrupt to drive the local APIC of the
3122 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3123 * the I/O APIC in all cases now. No actual device should request
3124 * it anyway. --macro
3126 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3128 void __init
setup_IO_APIC(void)
3132 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3134 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
3136 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3138 * Set up IO-APIC IRQ routing.
3140 x86_init
.mpparse
.setup_ioapic_ids();
3143 setup_IO_APIC_irqs();
3144 init_IO_APIC_traps();
3145 if (legacy_pic
->nr_legacy_irqs
)
3150 * Called after all the initialization is done. If we didnt find any
3151 * APIC bugs then we can allow the modify fast path
3154 static int __init
io_apic_bug_finalize(void)
3156 if (sis_apic_bug
== -1)
3161 late_initcall(io_apic_bug_finalize
);
3163 struct sysfs_ioapic_data
{
3164 struct sys_device dev
;
3165 struct IO_APIC_route_entry entry
[0];
3167 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3169 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3171 struct IO_APIC_route_entry
*entry
;
3172 struct sysfs_ioapic_data
*data
;
3175 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3176 entry
= data
->entry
;
3177 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3178 *entry
= ioapic_read_entry(dev
->id
, i
);
3183 static int ioapic_resume(struct sys_device
*dev
)
3185 struct IO_APIC_route_entry
*entry
;
3186 struct sysfs_ioapic_data
*data
;
3187 unsigned long flags
;
3188 union IO_APIC_reg_00 reg_00
;
3191 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3192 entry
= data
->entry
;
3194 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3195 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3196 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].apicid
) {
3197 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].apicid
;
3198 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3200 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3201 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3202 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3207 static struct sysdev_class ioapic_sysdev_class
= {
3209 .suspend
= ioapic_suspend
,
3210 .resume
= ioapic_resume
,
3213 static int __init
ioapic_init_sysfs(void)
3215 struct sys_device
* dev
;
3218 error
= sysdev_class_register(&ioapic_sysdev_class
);
3222 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3223 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3224 * sizeof(struct IO_APIC_route_entry
);
3225 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3226 if (!mp_ioapic_data
[i
]) {
3227 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3230 dev
= &mp_ioapic_data
[i
]->dev
;
3232 dev
->cls
= &ioapic_sysdev_class
;
3233 error
= sysdev_register(dev
);
3235 kfree(mp_ioapic_data
[i
]);
3236 mp_ioapic_data
[i
] = NULL
;
3237 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3245 device_initcall(ioapic_init_sysfs
);
3248 * Dynamic irq allocate and deallocation
3250 unsigned int create_irq_nr(unsigned int irq_want
, int node
)
3252 /* Allocate an unused irq */
3255 unsigned long flags
;
3256 struct irq_cfg
*cfg_new
= NULL
;
3257 struct irq_desc
*desc_new
= NULL
;
3260 if (irq_want
< nr_irqs_gsi
)
3261 irq_want
= nr_irqs_gsi
;
3263 raw_spin_lock_irqsave(&vector_lock
, flags
);
3264 for (new = irq_want
; new < nr_irqs
; new++) {
3265 desc_new
= irq_to_desc_alloc_node(new, node
);
3267 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3270 cfg_new
= desc_new
->chip_data
;
3272 if (cfg_new
->vector
!= 0)
3275 desc_new
= move_irq_desc(desc_new
, node
);
3276 cfg_new
= desc_new
->chip_data
;
3278 if (__assign_irq_vector(new, cfg_new
, apic
->target_cpus()) == 0)
3282 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3285 dynamic_irq_init_keep_chip_data(irq
);
3290 int create_irq(void)
3292 int node
= cpu_to_node(boot_cpu_id
);
3293 unsigned int irq_want
;
3296 irq_want
= nr_irqs_gsi
;
3297 irq
= create_irq_nr(irq_want
, node
);
3305 void destroy_irq(unsigned int irq
)
3307 unsigned long flags
;
3309 dynamic_irq_cleanup_keep_chip_data(irq
);
3312 raw_spin_lock_irqsave(&vector_lock
, flags
);
3313 __clear_irq_vector(irq
, get_irq_chip_data(irq
));
3314 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3318 * MSI message composition
3320 #ifdef CONFIG_PCI_MSI
3321 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3322 struct msi_msg
*msg
, u8 hpet_id
)
3324 struct irq_cfg
*cfg
;
3332 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3336 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus());
3338 if (irq_remapped(irq
)) {
3343 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3344 BUG_ON(ir_index
== -1);
3346 memset (&irte
, 0, sizeof(irte
));
3349 irte
.dst_mode
= apic
->irq_dest_mode
;
3350 irte
.trigger_mode
= 0; /* edge */
3351 irte
.dlvry_mode
= apic
->irq_delivery_mode
;
3352 irte
.vector
= cfg
->vector
;
3353 irte
.dest_id
= IRTE_DEST(dest
);
3355 /* Set source-id of interrupt request */
3357 set_msi_sid(&irte
, pdev
);
3359 set_hpet_sid(&irte
, hpet_id
);
3361 modify_irte(irq
, &irte
);
3363 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3364 msg
->data
= sub_handle
;
3365 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3367 MSI_ADDR_IR_INDEX1(ir_index
) |
3368 MSI_ADDR_IR_INDEX2(ir_index
);
3370 if (x2apic_enabled())
3371 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3372 MSI_ADDR_EXT_DEST_ID(dest
);
3374 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3378 ((apic
->irq_dest_mode
== 0) ?
3379 MSI_ADDR_DEST_MODE_PHYSICAL
:
3380 MSI_ADDR_DEST_MODE_LOGICAL
) |
3381 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3382 MSI_ADDR_REDIRECTION_CPU
:
3383 MSI_ADDR_REDIRECTION_LOWPRI
) |
3384 MSI_ADDR_DEST_ID(dest
);
3387 MSI_DATA_TRIGGER_EDGE
|
3388 MSI_DATA_LEVEL_ASSERT
|
3389 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3390 MSI_DATA_DELIVERY_FIXED
:
3391 MSI_DATA_DELIVERY_LOWPRI
) |
3392 MSI_DATA_VECTOR(cfg
->vector
);
3398 static int set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3400 struct irq_desc
*desc
= irq_to_desc(irq
);
3401 struct irq_cfg
*cfg
;
3405 if (set_desc_affinity(desc
, mask
, &dest
))
3408 cfg
= desc
->chip_data
;
3410 read_msi_msg_desc(desc
, &msg
);
3412 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3413 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3414 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3415 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3417 write_msi_msg_desc(desc
, &msg
);
3421 #ifdef CONFIG_INTR_REMAP
3423 * Migrate the MSI irq to another cpumask. This migration is
3424 * done in the process context using interrupt-remapping hardware.
3427 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3429 struct irq_desc
*desc
= irq_to_desc(irq
);
3430 struct irq_cfg
*cfg
= desc
->chip_data
;
3434 if (get_irte(irq
, &irte
))
3437 if (set_desc_affinity(desc
, mask
, &dest
))
3440 irte
.vector
= cfg
->vector
;
3441 irte
.dest_id
= IRTE_DEST(dest
);
3444 * atomically update the IRTE with the new destination and vector.
3446 modify_irte(irq
, &irte
);
3449 * After this point, all the interrupts will start arriving
3450 * at the new destination. So, time to cleanup the previous
3451 * vector allocation.
3453 if (cfg
->move_in_progress
)
3454 send_cleanup_vector(cfg
);
3460 #endif /* CONFIG_SMP */
3463 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3464 * which implement the MSI or MSI-X Capability Structure.
3466 static struct irq_chip msi_chip
= {
3468 .unmask
= unmask_msi_irq
,
3469 .mask
= mask_msi_irq
,
3470 .ack
= ack_apic_edge
,
3472 .set_affinity
= set_msi_irq_affinity
,
3474 .retrigger
= ioapic_retrigger_irq
,
3477 static struct irq_chip msi_ir_chip
= {
3478 .name
= "IR-PCI-MSI",
3479 .unmask
= unmask_msi_irq
,
3480 .mask
= mask_msi_irq
,
3481 #ifdef CONFIG_INTR_REMAP
3482 .ack
= ir_ack_apic_edge
,
3484 .set_affinity
= ir_set_msi_irq_affinity
,
3487 .retrigger
= ioapic_retrigger_irq
,
3491 * Map the PCI dev to the corresponding remapping hardware unit
3492 * and allocate 'nvec' consecutive interrupt-remapping table entries
3495 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3497 struct intel_iommu
*iommu
;
3500 iommu
= map_dev_to_ir(dev
);
3503 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3507 index
= alloc_irte(iommu
, irq
, nvec
);
3510 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3517 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3522 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3526 set_irq_msi(irq
, msidesc
);
3527 write_msi_msg(irq
, &msg
);
3529 if (irq_remapped(irq
)) {
3530 struct irq_desc
*desc
= irq_to_desc(irq
);
3532 * irq migration in process context
3534 desc
->status
|= IRQ_MOVE_PCNTXT
;
3535 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3537 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3539 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3544 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3547 int ret
, sub_handle
;
3548 struct msi_desc
*msidesc
;
3549 unsigned int irq_want
;
3550 struct intel_iommu
*iommu
= NULL
;
3554 /* x86 doesn't support multiple MSI yet */
3555 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3558 node
= dev_to_node(&dev
->dev
);
3559 irq_want
= nr_irqs_gsi
;
3561 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3562 irq
= create_irq_nr(irq_want
, node
);
3566 if (!intr_remapping_enabled
)
3571 * allocate the consecutive block of IRTE's
3574 index
= msi_alloc_irte(dev
, irq
, nvec
);
3580 iommu
= map_dev_to_ir(dev
);
3586 * setup the mapping between the irq and the IRTE
3587 * base index, the sub_handle pointing to the
3588 * appropriate interrupt remap table entry.
3590 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3593 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3605 void arch_teardown_msi_irq(unsigned int irq
)
3610 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3612 static int dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3614 struct irq_desc
*desc
= irq_to_desc(irq
);
3615 struct irq_cfg
*cfg
;
3619 if (set_desc_affinity(desc
, mask
, &dest
))
3622 cfg
= desc
->chip_data
;
3624 dmar_msi_read(irq
, &msg
);
3626 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3627 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3628 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3629 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3631 dmar_msi_write(irq
, &msg
);
3636 #endif /* CONFIG_SMP */
3638 static struct irq_chip dmar_msi_type
= {
3640 .unmask
= dmar_msi_unmask
,
3641 .mask
= dmar_msi_mask
,
3642 .ack
= ack_apic_edge
,
3644 .set_affinity
= dmar_msi_set_affinity
,
3646 .retrigger
= ioapic_retrigger_irq
,
3649 int arch_setup_dmar_msi(unsigned int irq
)
3654 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3657 dmar_msi_write(irq
, &msg
);
3658 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3664 #ifdef CONFIG_HPET_TIMER
3667 static int hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3669 struct irq_desc
*desc
= irq_to_desc(irq
);
3670 struct irq_cfg
*cfg
;
3674 if (set_desc_affinity(desc
, mask
, &dest
))
3677 cfg
= desc
->chip_data
;
3679 hpet_msi_read(irq
, &msg
);
3681 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3682 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3683 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3684 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3686 hpet_msi_write(irq
, &msg
);
3691 #endif /* CONFIG_SMP */
3693 static struct irq_chip ir_hpet_msi_type
= {
3694 .name
= "IR-HPET_MSI",
3695 .unmask
= hpet_msi_unmask
,
3696 .mask
= hpet_msi_mask
,
3697 #ifdef CONFIG_INTR_REMAP
3698 .ack
= ir_ack_apic_edge
,
3700 .set_affinity
= ir_set_msi_irq_affinity
,
3703 .retrigger
= ioapic_retrigger_irq
,
3706 static struct irq_chip hpet_msi_type
= {
3708 .unmask
= hpet_msi_unmask
,
3709 .mask
= hpet_msi_mask
,
3710 .ack
= ack_apic_edge
,
3712 .set_affinity
= hpet_msi_set_affinity
,
3714 .retrigger
= ioapic_retrigger_irq
,
3717 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3721 struct irq_desc
*desc
= irq_to_desc(irq
);
3723 if (intr_remapping_enabled
) {
3724 struct intel_iommu
*iommu
= map_hpet_to_ir(id
);
3730 index
= alloc_irte(iommu
, irq
, 1);
3735 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3739 hpet_msi_write(irq
, &msg
);
3740 desc
->status
|= IRQ_MOVE_PCNTXT
;
3741 if (irq_remapped(irq
))
3742 set_irq_chip_and_handler_name(irq
, &ir_hpet_msi_type
,
3743 handle_edge_irq
, "edge");
3745 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
,
3746 handle_edge_irq
, "edge");
3752 #endif /* CONFIG_PCI_MSI */
3754 * Hypertransport interrupt support
3756 #ifdef CONFIG_HT_IRQ
3760 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3762 struct ht_irq_msg msg
;
3763 fetch_ht_irq_msg(irq
, &msg
);
3765 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3766 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3768 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3769 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3771 write_ht_irq_msg(irq
, &msg
);
3774 static int set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3776 struct irq_desc
*desc
= irq_to_desc(irq
);
3777 struct irq_cfg
*cfg
;
3780 if (set_desc_affinity(desc
, mask
, &dest
))
3783 cfg
= desc
->chip_data
;
3785 target_ht_irq(irq
, dest
, cfg
->vector
);
3792 static struct irq_chip ht_irq_chip
= {
3794 .mask
= mask_ht_irq
,
3795 .unmask
= unmask_ht_irq
,
3796 .ack
= ack_apic_edge
,
3798 .set_affinity
= set_ht_irq_affinity
,
3800 .retrigger
= ioapic_retrigger_irq
,
3803 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3805 struct irq_cfg
*cfg
;
3812 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3814 struct ht_irq_msg msg
;
3817 dest
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3818 apic
->target_cpus());
3820 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3824 HT_IRQ_LOW_DEST_ID(dest
) |
3825 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3826 ((apic
->irq_dest_mode
== 0) ?
3827 HT_IRQ_LOW_DM_PHYSICAL
:
3828 HT_IRQ_LOW_DM_LOGICAL
) |
3829 HT_IRQ_LOW_RQEOI_EDGE
|
3830 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3831 HT_IRQ_LOW_MT_FIXED
:
3832 HT_IRQ_LOW_MT_ARBITRATED
) |
3833 HT_IRQ_LOW_IRQ_MASKED
;
3835 write_ht_irq_msg(irq
, &msg
);
3837 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3838 handle_edge_irq
, "edge");
3840 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3844 #endif /* CONFIG_HT_IRQ */
3846 int __init
io_apic_get_redir_entries (int ioapic
)
3848 union IO_APIC_reg_01 reg_01
;
3849 unsigned long flags
;
3851 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3852 reg_01
.raw
= io_apic_read(ioapic
, 1);
3853 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3855 return reg_01
.bits
.entries
;
3858 void __init
probe_nr_irqs_gsi(void)
3862 nr
= acpi_probe_gsi();
3863 if (nr
> nr_irqs_gsi
) {
3866 /* for acpi=off or acpi is not compiled in */
3870 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3871 nr
+= io_apic_get_redir_entries(idx
) + 1;
3873 if (nr
> nr_irqs_gsi
)
3877 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3880 static int __io_apic_set_pci_routing(struct device
*dev
, int irq
,
3881 struct io_apic_irq_attr
*irq_attr
)
3883 struct irq_desc
*desc
;
3884 struct irq_cfg
*cfg
;
3887 int trigger
, polarity
;
3889 ioapic
= irq_attr
->ioapic
;
3890 if (!IO_APIC_IRQ(irq
)) {
3891 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3897 node
= dev_to_node(dev
);
3899 node
= cpu_to_node(boot_cpu_id
);
3901 desc
= irq_to_desc_alloc_node(irq
, node
);
3903 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3907 pin
= irq_attr
->ioapic_pin
;
3908 trigger
= irq_attr
->trigger
;
3909 polarity
= irq_attr
->polarity
;
3912 * IRQs < 16 are already in the irq_2_pin[] map
3914 if (irq
>= legacy_pic
->nr_legacy_irqs
) {
3915 cfg
= desc
->chip_data
;
3916 if (add_pin_to_irq_node_nopanic(cfg
, node
, ioapic
, pin
)) {
3917 printk(KERN_INFO
"can not add pin %d for irq %d\n",
3923 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, trigger
, polarity
);
3928 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3929 struct io_apic_irq_attr
*irq_attr
)
3933 * Avoid pin reprogramming. PRTs typically include entries
3934 * with redundant pin->gsi mappings (but unique PCI devices);
3935 * we only program the IOAPIC on the first.
3937 ioapic
= irq_attr
->ioapic
;
3938 pin
= irq_attr
->ioapic_pin
;
3939 if (test_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
)) {
3940 pr_debug("Pin %d-%d already programmed\n",
3941 mp_ioapics
[ioapic
].apicid
, pin
);
3944 set_bit(pin
, mp_ioapic_routing
[ioapic
].pin_programmed
);
3946 return __io_apic_set_pci_routing(dev
, irq
, irq_attr
);
3949 u8 __init
io_apic_unique_id(u8 id
)
3951 #ifdef CONFIG_X86_32
3952 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3953 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3954 return io_apic_get_unique_id(nr_ioapics
, id
);
3959 DECLARE_BITMAP(used
, 256);
3961 bitmap_zero(used
, 256);
3962 for (i
= 0; i
< nr_ioapics
; i
++) {
3963 struct mpc_ioapic
*ia
= &mp_ioapics
[i
];
3964 __set_bit(ia
->apicid
, used
);
3966 if (!test_bit(id
, used
))
3968 return find_first_zero_bit(used
, 256);
3972 #ifdef CONFIG_X86_32
3973 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3975 union IO_APIC_reg_00 reg_00
;
3976 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3978 unsigned long flags
;
3982 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3983 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3984 * supports up to 16 on one shared APIC bus.
3986 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3987 * advantage of new APIC bus architecture.
3990 if (physids_empty(apic_id_map
))
3991 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3993 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3994 reg_00
.raw
= io_apic_read(ioapic
, 0);
3995 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3997 if (apic_id
>= get_physical_broadcast()) {
3998 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3999 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
4000 apic_id
= reg_00
.bits
.ID
;
4004 * Every APIC in a system must have a unique ID or we get lots of nice
4005 * 'stuck on smp_invalidate_needed IPI wait' messages.
4007 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
4009 for (i
= 0; i
< get_physical_broadcast(); i
++) {
4010 if (!apic
->check_apicid_used(&apic_id_map
, i
))
4014 if (i
== get_physical_broadcast())
4015 panic("Max apic_id exceeded!\n");
4017 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
4018 "trying %d\n", ioapic
, apic_id
, i
);
4023 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
4024 physids_or(apic_id_map
, apic_id_map
, tmp
);
4026 if (reg_00
.bits
.ID
!= apic_id
) {
4027 reg_00
.bits
.ID
= apic_id
;
4029 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4030 io_apic_write(ioapic
, 0, reg_00
.raw
);
4031 reg_00
.raw
= io_apic_read(ioapic
, 0);
4032 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4035 if (reg_00
.bits
.ID
!= apic_id
) {
4036 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
4041 apic_printk(APIC_VERBOSE
, KERN_INFO
4042 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
4048 int __init
io_apic_get_version(int ioapic
)
4050 union IO_APIC_reg_01 reg_01
;
4051 unsigned long flags
;
4053 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
4054 reg_01
.raw
= io_apic_read(ioapic
, 1);
4055 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
4057 return reg_01
.bits
.version
;
4060 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
4064 if (skip_ioapic_setup
)
4067 for (i
= 0; i
< mp_irq_entries
; i
++)
4068 if (mp_irqs
[i
].irqtype
== mp_INT
&&
4069 mp_irqs
[i
].srcbusirq
== bus_irq
)
4071 if (i
>= mp_irq_entries
)
4074 *trigger
= irq_trigger(i
);
4075 *polarity
= irq_polarity(i
);
4080 * This function currently is only a helper for the i386 smp boot process where
4081 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4082 * so mask in all cases should simply be apic->target_cpus()
4085 void __init
setup_ioapic_dest(void)
4087 int pin
, ioapic
= 0, irq
, irq_entry
;
4088 struct irq_desc
*desc
;
4089 const struct cpumask
*mask
;
4091 if (skip_ioapic_setup
== 1)
4095 if (!acpi_disabled
&& acpi_ioapic
) {
4096 ioapic
= mp_find_ioapic(0);
4102 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4103 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4104 if (irq_entry
== -1)
4106 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4108 desc
= irq_to_desc(irq
);
4111 * Honour affinities which have been set in early boot
4114 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4115 mask
= desc
->affinity
;
4117 mask
= apic
->target_cpus();
4119 if (intr_remapping_enabled
)
4120 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4122 set_ioapic_affinity_irq_desc(desc
, mask
);
4128 #define IOAPIC_RESOURCE_NAME_SIZE 11
4130 static struct resource
*ioapic_resources
;
4132 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
4135 struct resource
*res
;
4139 if (nr_ioapics
<= 0)
4142 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4145 mem
= alloc_bootmem(n
);
4148 mem
+= sizeof(struct resource
) * nr_ioapics
;
4150 for (i
= 0; i
< nr_ioapics
; i
++) {
4152 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4153 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
4154 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4157 ioapic_resources
= res
;
4162 void __init
ioapic_init_mappings(void)
4164 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4165 struct resource
*ioapic_res
;
4168 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
4169 for (i
= 0; i
< nr_ioapics
; i
++) {
4170 if (smp_found_config
) {
4171 ioapic_phys
= mp_ioapics
[i
].apicaddr
;
4172 #ifdef CONFIG_X86_32
4175 "WARNING: bogus zero IO-APIC "
4176 "address found in MPTABLE, "
4177 "disabling IO/APIC support!\n");
4178 smp_found_config
= 0;
4179 skip_ioapic_setup
= 1;
4180 goto fake_ioapic_page
;
4184 #ifdef CONFIG_X86_32
4187 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
4188 ioapic_phys
= __pa(ioapic_phys
);
4190 set_fixmap_nocache(idx
, ioapic_phys
);
4191 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
4192 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
4196 ioapic_res
->start
= ioapic_phys
;
4197 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
4202 void __init
ioapic_insert_resources(void)
4205 struct resource
*r
= ioapic_resources
;
4210 "IO APIC resources couldn't be allocated.\n");
4214 for (i
= 0; i
< nr_ioapics
; i
++) {
4215 insert_resource(&iomem_resource
, r
);
4220 int mp_find_ioapic(int gsi
)
4224 /* Find the IOAPIC that manages this GSI. */
4225 for (i
= 0; i
< nr_ioapics
; i
++) {
4226 if ((gsi
>= mp_gsi_routing
[i
].gsi_base
)
4227 && (gsi
<= mp_gsi_routing
[i
].gsi_end
))
4231 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
4235 int mp_find_ioapic_pin(int ioapic
, int gsi
)
4237 if (WARN_ON(ioapic
== -1))
4239 if (WARN_ON(gsi
> mp_gsi_routing
[ioapic
].gsi_end
))
4242 return gsi
- mp_gsi_routing
[ioapic
].gsi_base
;
4245 static int bad_ioapic(unsigned long address
)
4247 if (nr_ioapics
>= MAX_IO_APICS
) {
4248 printk(KERN_WARNING
"WARING: Max # of I/O APICs (%d) exceeded "
4249 "(found %d), skipping\n", MAX_IO_APICS
, nr_ioapics
);
4253 printk(KERN_WARNING
"WARNING: Bogus (zero) I/O APIC address"
4254 " found in table, skipping!\n");
4260 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
4264 if (bad_ioapic(address
))
4269 mp_ioapics
[idx
].type
= MP_IOAPIC
;
4270 mp_ioapics
[idx
].flags
= MPC_APIC_USABLE
;
4271 mp_ioapics
[idx
].apicaddr
= address
;
4273 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
4274 mp_ioapics
[idx
].apicid
= io_apic_unique_id(id
);
4275 mp_ioapics
[idx
].apicver
= io_apic_get_version(idx
);
4278 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4279 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4281 mp_gsi_routing
[idx
].gsi_base
= gsi_base
;
4282 mp_gsi_routing
[idx
].gsi_end
= gsi_base
+
4283 io_apic_get_redir_entries(idx
);
4285 printk(KERN_INFO
"IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4286 "GSI %d-%d\n", idx
, mp_ioapics
[idx
].apicid
,
4287 mp_ioapics
[idx
].apicver
, mp_ioapics
[idx
].apicaddr
,
4288 mp_gsi_routing
[idx
].gsi_base
, mp_gsi_routing
[idx
].gsi_end
);
4293 /* Enable IOAPIC early just for system timer */
4294 void __init
pre_init_apic_IRQ0(void)
4296 struct irq_cfg
*cfg
;
4297 struct irq_desc
*desc
;
4299 printk(KERN_INFO
"Early APIC setup for system timer0\n");
4301 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
4303 desc
= irq_to_desc_alloc_node(0, 0);
4308 add_pin_to_irq_node(cfg
, 0, 0, 0);
4309 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
4311 setup_IO_APIC_irq(0, 0, 0, desc
, 0, 0);