2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list
);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops
;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
56 struct unity_map_entry
*e
);
57 static struct dma_ops_domain
*find_protection_domain(u16 devid
);
58 static u64
* alloc_pte(struct protection_domain
*dom
,
59 unsigned long address
, u64
60 **pte_page
, gfp_t gfp
);
62 #ifdef CONFIG_AMD_IOMMU_STATS
65 * Initialization code for statistics collection
68 DECLARE_STATS_COUNTER(compl_wait
);
69 DECLARE_STATS_COUNTER(cnt_map_single
);
70 DECLARE_STATS_COUNTER(cnt_unmap_single
);
71 DECLARE_STATS_COUNTER(cnt_map_sg
);
72 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
73 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
74 DECLARE_STATS_COUNTER(cnt_free_coherent
);
75 DECLARE_STATS_COUNTER(cross_page
);
76 DECLARE_STATS_COUNTER(domain_flush_single
);
77 DECLARE_STATS_COUNTER(domain_flush_all
);
78 DECLARE_STATS_COUNTER(alloced_io_mem
);
79 DECLARE_STATS_COUNTER(total_map_requests
);
81 static struct dentry
*stats_dir
;
82 static struct dentry
*de_isolate
;
83 static struct dentry
*de_fflush
;
85 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
87 if (stats_dir
== NULL
)
90 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
94 static void amd_iommu_stats_init(void)
96 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
97 if (stats_dir
== NULL
)
100 de_isolate
= debugfs_create_bool("isolation", 0444, stats_dir
,
101 (u32
*)&amd_iommu_isolate
);
103 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
104 (u32
*)&amd_iommu_unmap_flush
);
106 amd_iommu_stats_add(&compl_wait
);
107 amd_iommu_stats_add(&cnt_map_single
);
108 amd_iommu_stats_add(&cnt_unmap_single
);
109 amd_iommu_stats_add(&cnt_map_sg
);
110 amd_iommu_stats_add(&cnt_unmap_sg
);
111 amd_iommu_stats_add(&cnt_alloc_coherent
);
112 amd_iommu_stats_add(&cnt_free_coherent
);
113 amd_iommu_stats_add(&cross_page
);
114 amd_iommu_stats_add(&domain_flush_single
);
115 amd_iommu_stats_add(&domain_flush_all
);
116 amd_iommu_stats_add(&alloced_io_mem
);
117 amd_iommu_stats_add(&total_map_requests
);
122 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
123 static int iommu_has_npcache(struct amd_iommu
*iommu
)
125 return iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
);
128 /****************************************************************************
130 * Interrupt handling functions
132 ****************************************************************************/
134 static void iommu_print_event(void *__evt
)
137 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
138 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
139 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
140 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
141 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
143 printk(KERN_ERR
"AMD IOMMU: Event logged [");
146 case EVENT_TYPE_ILL_DEV
:
147 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
148 "address=0x%016llx flags=0x%04x]\n",
149 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
152 case EVENT_TYPE_IO_FAULT
:
153 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
154 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
155 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
156 domid
, address
, flags
);
158 case EVENT_TYPE_DEV_TAB_ERR
:
159 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
160 "address=0x%016llx flags=0x%04x]\n",
161 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
164 case EVENT_TYPE_PAGE_TAB_ERR
:
165 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
166 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
167 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
168 domid
, address
, flags
);
170 case EVENT_TYPE_ILL_CMD
:
171 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
173 case EVENT_TYPE_CMD_HARD_ERR
:
174 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
175 "flags=0x%04x]\n", address
, flags
);
177 case EVENT_TYPE_IOTLB_INV_TO
:
178 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
179 "address=0x%016llx]\n",
180 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
183 case EVENT_TYPE_INV_DEV_REQ
:
184 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
190 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
194 static void iommu_poll_events(struct amd_iommu
*iommu
)
199 spin_lock_irqsave(&iommu
->lock
, flags
);
201 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
202 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
204 while (head
!= tail
) {
205 iommu_print_event(iommu
->evt_buf
+ head
);
206 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
209 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
211 spin_unlock_irqrestore(&iommu
->lock
, flags
);
214 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
216 struct amd_iommu
*iommu
;
218 list_for_each_entry(iommu
, &amd_iommu_list
, list
)
219 iommu_poll_events(iommu
);
224 /****************************************************************************
226 * IOMMU command queuing functions
228 ****************************************************************************/
231 * Writes the command to the IOMMUs command buffer and informs the
232 * hardware about the new command. Must be called with iommu->lock held.
234 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
239 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
240 target
= iommu
->cmd_buf
+ tail
;
241 memcpy_toio(target
, cmd
, sizeof(*cmd
));
242 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
243 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
246 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
252 * General queuing function for commands. Takes iommu->lock and calls
253 * __iommu_queue_command().
255 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
260 spin_lock_irqsave(&iommu
->lock
, flags
);
261 ret
= __iommu_queue_command(iommu
, cmd
);
263 iommu
->need_sync
= true;
264 spin_unlock_irqrestore(&iommu
->lock
, flags
);
270 * This function waits until an IOMMU has completed a completion
273 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
279 INC_STATS_COUNTER(compl_wait
);
281 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
283 /* wait for the bit to become one */
284 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
285 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
288 /* set bit back to zero */
289 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
290 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
292 if (unlikely(i
== EXIT_LOOP_COUNT
))
293 panic("AMD IOMMU: Completion wait loop failed\n");
297 * This function queues a completion wait command into the command
300 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
302 struct iommu_cmd cmd
;
304 memset(&cmd
, 0, sizeof(cmd
));
305 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
306 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
308 return __iommu_queue_command(iommu
, &cmd
);
312 * This function is called whenever we need to ensure that the IOMMU has
313 * completed execution of all commands we sent. It sends a
314 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
315 * us about that by writing a value to a physical address we pass with
318 static int iommu_completion_wait(struct amd_iommu
*iommu
)
323 spin_lock_irqsave(&iommu
->lock
, flags
);
325 if (!iommu
->need_sync
)
328 ret
= __iommu_completion_wait(iommu
);
330 iommu
->need_sync
= false;
335 __iommu_wait_for_completion(iommu
);
338 spin_unlock_irqrestore(&iommu
->lock
, flags
);
344 * Command send function for invalidating a device table entry
346 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
348 struct iommu_cmd cmd
;
351 BUG_ON(iommu
== NULL
);
353 memset(&cmd
, 0, sizeof(cmd
));
354 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
357 ret
= iommu_queue_command(iommu
, &cmd
);
362 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
363 u16 domid
, int pde
, int s
)
365 memset(cmd
, 0, sizeof(*cmd
));
366 address
&= PAGE_MASK
;
367 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
368 cmd
->data
[1] |= domid
;
369 cmd
->data
[2] = lower_32_bits(address
);
370 cmd
->data
[3] = upper_32_bits(address
);
371 if (s
) /* size bit - we flush more than one 4kb page */
372 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
373 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
374 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
378 * Generic command send function for invalidaing TLB entries
380 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
381 u64 address
, u16 domid
, int pde
, int s
)
383 struct iommu_cmd cmd
;
386 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
388 ret
= iommu_queue_command(iommu
, &cmd
);
394 * TLB invalidation function which is called from the mapping functions.
395 * It invalidates a single PTE if the range to flush is within a single
396 * page. Otherwise it flushes the whole TLB of the IOMMU.
398 static int iommu_flush_pages(struct amd_iommu
*iommu
, u16 domid
,
399 u64 address
, size_t size
)
402 unsigned pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
404 address
&= PAGE_MASK
;
408 * If we have to flush more than one page, flush all
409 * TLB entries for this domain
411 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
415 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, s
);
420 /* Flush the whole IO/TLB for a given protection domain */
421 static void iommu_flush_tlb(struct amd_iommu
*iommu
, u16 domid
)
423 u64 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
425 INC_STATS_COUNTER(domain_flush_single
);
427 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, 1);
431 * This function is used to flush the IO/TLB for a given protection domain
432 * on every IOMMU in the system
434 static void iommu_flush_domain(u16 domid
)
437 struct amd_iommu
*iommu
;
438 struct iommu_cmd cmd
;
440 INC_STATS_COUNTER(domain_flush_all
);
442 __iommu_build_inv_iommu_pages(&cmd
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
445 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
446 spin_lock_irqsave(&iommu
->lock
, flags
);
447 __iommu_queue_command(iommu
, &cmd
);
448 __iommu_completion_wait(iommu
);
449 __iommu_wait_for_completion(iommu
);
450 spin_unlock_irqrestore(&iommu
->lock
, flags
);
454 /****************************************************************************
456 * The functions below are used the create the page table mappings for
457 * unity mapped regions.
459 ****************************************************************************/
462 * Generic mapping functions. It maps a physical address into a DMA
463 * address space. It allocates the page table pages if necessary.
464 * In the future it can be extended to a generic mapping function
465 * supporting all features of AMD IOMMU page tables like level skipping
466 * and full 64 bit address spaces.
468 static int iommu_map_page(struct protection_domain
*dom
,
469 unsigned long bus_addr
,
470 unsigned long phys_addr
,
475 bus_addr
= PAGE_ALIGN(bus_addr
);
476 phys_addr
= PAGE_ALIGN(phys_addr
);
478 /* only support 512GB address spaces for now */
479 if (bus_addr
> IOMMU_MAP_SIZE_L3
|| !(prot
& IOMMU_PROT_MASK
))
482 pte
= alloc_pte(dom
, bus_addr
, NULL
, GFP_KERNEL
);
484 if (IOMMU_PTE_PRESENT(*pte
))
487 __pte
= phys_addr
| IOMMU_PTE_P
;
488 if (prot
& IOMMU_PROT_IR
)
489 __pte
|= IOMMU_PTE_IR
;
490 if (prot
& IOMMU_PROT_IW
)
491 __pte
|= IOMMU_PTE_IW
;
498 static void iommu_unmap_page(struct protection_domain
*dom
,
499 unsigned long bus_addr
)
503 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(bus_addr
)];
505 if (!IOMMU_PTE_PRESENT(*pte
))
508 pte
= IOMMU_PTE_PAGE(*pte
);
509 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
511 if (!IOMMU_PTE_PRESENT(*pte
))
514 pte
= IOMMU_PTE_PAGE(*pte
);
515 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
521 * This function checks if a specific unity mapping entry is needed for
522 * this specific IOMMU.
524 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
525 struct unity_map_entry
*entry
)
529 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
530 bdf
= amd_iommu_alias_table
[i
];
531 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
539 * Init the unity mappings for a specific IOMMU in the system
541 * Basically iterates over all unity mapping entries and applies them to
542 * the default domain DMA of that IOMMU if necessary.
544 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
546 struct unity_map_entry
*entry
;
549 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
550 if (!iommu_for_unity_map(iommu
, entry
))
552 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
561 * This function actually applies the mapping to the page table of the
564 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
565 struct unity_map_entry
*e
)
570 for (addr
= e
->address_start
; addr
< e
->address_end
;
572 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
);
576 * if unity mapping is in aperture range mark the page
577 * as allocated in the aperture
579 if (addr
< dma_dom
->aperture_size
)
580 __set_bit(addr
>> PAGE_SHIFT
,
581 dma_dom
->aperture
.bitmap
);
588 * Inits the unity mappings required for a specific device
590 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
593 struct unity_map_entry
*e
;
596 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
597 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
599 ret
= dma_ops_unity_map(dma_dom
, e
);
607 /****************************************************************************
609 * The next functions belong to the address allocator for the dma_ops
610 * interface functions. They work like the allocators in the other IOMMU
611 * drivers. Its basically a bitmap which marks the allocated pages in
612 * the aperture. Maybe it could be enhanced in the future to a more
613 * efficient allocator.
615 ****************************************************************************/
618 * The address allocator core function.
620 * called with domain->lock held
622 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
623 struct dma_ops_domain
*dom
,
625 unsigned long align_mask
,
629 unsigned long address
;
630 unsigned long boundary_size
;
632 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
633 PAGE_SIZE
) >> PAGE_SHIFT
;
634 limit
= iommu_device_max_index(dom
->aperture_size
>> PAGE_SHIFT
, 0,
635 dma_mask
>> PAGE_SHIFT
);
637 if (dom
->next_bit
>= limit
) {
639 dom
->need_flush
= true;
642 address
= iommu_area_alloc(dom
->aperture
.bitmap
, limit
, dom
->next_bit
,
643 pages
, 0 , boundary_size
, align_mask
);
645 address
= iommu_area_alloc(dom
->aperture
.bitmap
, limit
, 0,
646 pages
, 0, boundary_size
,
648 dom
->need_flush
= true;
651 if (likely(address
!= -1)) {
652 dom
->next_bit
= address
+ pages
;
653 address
<<= PAGE_SHIFT
;
655 address
= bad_dma_address
;
657 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
663 * The address free function.
665 * called with domain->lock held
667 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
668 unsigned long address
,
671 address
>>= PAGE_SHIFT
;
672 iommu_area_free(dom
->aperture
.bitmap
, address
, pages
);
674 if (address
>= dom
->next_bit
)
675 dom
->need_flush
= true;
678 /****************************************************************************
680 * The next functions belong to the domain allocation. A domain is
681 * allocated for every IOMMU as the default domain. If device isolation
682 * is enabled, every device get its own domain. The most important thing
683 * about domains is the page table mapping the DMA address space they
686 ****************************************************************************/
688 static u16
domain_id_alloc(void)
693 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
694 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
696 if (id
> 0 && id
< MAX_DOMAIN_ID
)
697 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
700 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
705 static void domain_id_free(int id
)
709 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
710 if (id
> 0 && id
< MAX_DOMAIN_ID
)
711 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
712 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
716 * Used to reserve address ranges in the aperture (e.g. for exclusion
719 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
720 unsigned long start_page
,
723 unsigned int last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
725 if (start_page
+ pages
> last_page
)
726 pages
= last_page
- start_page
;
728 iommu_area_reserve(dom
->aperture
.bitmap
, start_page
, pages
);
731 static void free_pagetable(struct protection_domain
*domain
)
736 p1
= domain
->pt_root
;
741 for (i
= 0; i
< 512; ++i
) {
742 if (!IOMMU_PTE_PRESENT(p1
[i
]))
745 p2
= IOMMU_PTE_PAGE(p1
[i
]);
746 for (j
= 0; j
< 512; ++j
) {
747 if (!IOMMU_PTE_PRESENT(p2
[j
]))
749 p3
= IOMMU_PTE_PAGE(p2
[j
]);
750 free_page((unsigned long)p3
);
753 free_page((unsigned long)p2
);
756 free_page((unsigned long)p1
);
758 domain
->pt_root
= NULL
;
762 * Free a domain, only used if something went wrong in the
763 * allocation path and we need to free an already allocated page table
765 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
770 free_pagetable(&dom
->domain
);
772 free_page((unsigned long)dom
->aperture
.bitmap
);
778 * Allocates a new protection domain usable for the dma_ops functions.
779 * It also intializes the page table and the address allocator data
780 * structures required for the dma_ops interface
782 static struct dma_ops_domain
*dma_ops_domain_alloc(struct amd_iommu
*iommu
,
785 struct dma_ops_domain
*dma_dom
;
786 unsigned i
, num_pte_pages
;
791 * Currently the DMA aperture must be between 32 MB and 1GB in size
793 if ((order
< 25) || (order
> 30))
796 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
800 spin_lock_init(&dma_dom
->domain
.lock
);
802 dma_dom
->domain
.id
= domain_id_alloc();
803 if (dma_dom
->domain
.id
== 0)
805 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
806 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
807 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
808 dma_dom
->domain
.priv
= dma_dom
;
809 if (!dma_dom
->domain
.pt_root
)
811 dma_dom
->aperture_size
= APERTURE_RANGE_SIZE
;
812 dma_dom
->aperture
.bitmap
= (void *)get_zeroed_page(GFP_KERNEL
);
813 if (!dma_dom
->aperture
.bitmap
)
816 * mark the first page as allocated so we never return 0 as
817 * a valid dma-address. So we can use 0 as error value
819 dma_dom
->aperture
.bitmap
[0] = 1;
820 dma_dom
->next_bit
= 0;
822 dma_dom
->need_flush
= false;
823 dma_dom
->target_dev
= 0xffff;
825 /* Intialize the exclusion range if necessary */
826 if (iommu
->exclusion_start
&&
827 iommu
->exclusion_start
< dma_dom
->aperture_size
) {
828 unsigned long startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
829 int pages
= iommu_num_pages(iommu
->exclusion_start
,
830 iommu
->exclusion_length
,
832 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
836 * At the last step, build the page tables so we don't need to
837 * allocate page table pages in the dma_ops mapping/unmapping
838 * path for the first 128MB of dma address space.
840 num_pte_pages
= dma_dom
->aperture_size
/ (PAGE_SIZE
* 512);
842 l2_pde
= (u64
*)get_zeroed_page(GFP_KERNEL
);
846 dma_dom
->domain
.pt_root
[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde
));
848 for (i
= 0; i
< num_pte_pages
; ++i
) {
849 u64
**pte_page
= &dma_dom
->aperture
.pte_pages
[i
];
850 *pte_page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
853 address
= virt_to_phys(*pte_page
);
854 l2_pde
[i
] = IOMMU_L1_PDE(address
);
860 dma_ops_domain_free(dma_dom
);
866 * little helper function to check whether a given protection domain is a
869 static bool dma_ops_domain(struct protection_domain
*domain
)
871 return domain
->flags
& PD_DMA_OPS_MASK
;
875 * Find out the protection domain structure for a given PCI device. This
876 * will give us the pointer to the page table root for example.
878 static struct protection_domain
*domain_for_device(u16 devid
)
880 struct protection_domain
*dom
;
883 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
884 dom
= amd_iommu_pd_table
[devid
];
885 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
891 * If a device is not yet associated with a domain, this function does
892 * assigns it visible for the hardware
894 static void attach_device(struct amd_iommu
*iommu
,
895 struct protection_domain
*domain
,
899 u64 pte_root
= virt_to_phys(domain
->pt_root
);
901 domain
->dev_cnt
+= 1;
903 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
904 << DEV_ENTRY_MODE_SHIFT
;
905 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
907 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
908 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
909 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
910 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
912 amd_iommu_pd_table
[devid
] = domain
;
913 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
915 iommu_queue_inv_dev_entry(iommu
, devid
);
919 * Removes a device from a protection domain (unlocked)
921 static void __detach_device(struct protection_domain
*domain
, u16 devid
)
925 spin_lock(&domain
->lock
);
927 /* remove domain from the lookup table */
928 amd_iommu_pd_table
[devid
] = NULL
;
930 /* remove entry from the device table seen by the hardware */
931 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
932 amd_iommu_dev_table
[devid
].data
[1] = 0;
933 amd_iommu_dev_table
[devid
].data
[2] = 0;
935 /* decrease reference counter */
936 domain
->dev_cnt
-= 1;
939 spin_unlock(&domain
->lock
);
943 * Removes a device from a protection domain (with devtable_lock held)
945 static void detach_device(struct protection_domain
*domain
, u16 devid
)
949 /* lock device table */
950 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
951 __detach_device(domain
, devid
);
952 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
955 static int device_change_notifier(struct notifier_block
*nb
,
956 unsigned long action
, void *data
)
958 struct device
*dev
= data
;
959 struct pci_dev
*pdev
= to_pci_dev(dev
);
960 u16 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
961 struct protection_domain
*domain
;
962 struct dma_ops_domain
*dma_domain
;
963 struct amd_iommu
*iommu
;
964 int order
= amd_iommu_aperture_order
;
967 if (devid
> amd_iommu_last_bdf
)
970 devid
= amd_iommu_alias_table
[devid
];
972 iommu
= amd_iommu_rlookup_table
[devid
];
976 domain
= domain_for_device(devid
);
978 if (domain
&& !dma_ops_domain(domain
))
979 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
980 "to a non-dma-ops domain\n", dev_name(dev
));
983 case BUS_NOTIFY_BOUND_DRIVER
:
986 dma_domain
= find_protection_domain(devid
);
988 dma_domain
= iommu
->default_dom
;
989 attach_device(iommu
, &dma_domain
->domain
, devid
);
990 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
991 "device %s\n", dma_domain
->domain
.id
, dev_name(dev
));
993 case BUS_NOTIFY_UNBIND_DRIVER
:
996 detach_device(domain
, devid
);
998 case BUS_NOTIFY_ADD_DEVICE
:
999 /* allocate a protection domain if a device is added */
1000 dma_domain
= find_protection_domain(devid
);
1003 dma_domain
= dma_ops_domain_alloc(iommu
, order
);
1006 dma_domain
->target_dev
= devid
;
1008 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1009 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1010 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1017 iommu_queue_inv_dev_entry(iommu
, devid
);
1018 iommu_completion_wait(iommu
);
1024 struct notifier_block device_nb
= {
1025 .notifier_call
= device_change_notifier
,
1028 /*****************************************************************************
1030 * The next functions belong to the dma_ops mapping/unmapping code.
1032 *****************************************************************************/
1035 * This function checks if the driver got a valid device from the caller to
1036 * avoid dereferencing invalid pointers.
1038 static bool check_device(struct device
*dev
)
1040 if (!dev
|| !dev
->dma_mask
)
1047 * In this function the list of preallocated protection domains is traversed to
1048 * find the domain for a specific device
1050 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
1052 struct dma_ops_domain
*entry
, *ret
= NULL
;
1053 unsigned long flags
;
1055 if (list_empty(&iommu_pd_list
))
1058 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1060 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
1061 if (entry
->target_dev
== devid
) {
1067 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1073 * In the dma_ops path we only have the struct device. This function
1074 * finds the corresponding IOMMU, the protection domain and the
1075 * requestor id for a given device.
1076 * If the device is not yet associated with a domain this is also done
1079 static int get_device_resources(struct device
*dev
,
1080 struct amd_iommu
**iommu
,
1081 struct protection_domain
**domain
,
1084 struct dma_ops_domain
*dma_dom
;
1085 struct pci_dev
*pcidev
;
1092 if (dev
->bus
!= &pci_bus_type
)
1095 pcidev
= to_pci_dev(dev
);
1096 _bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
1098 /* device not translated by any IOMMU in the system? */
1099 if (_bdf
> amd_iommu_last_bdf
)
1102 *bdf
= amd_iommu_alias_table
[_bdf
];
1104 *iommu
= amd_iommu_rlookup_table
[*bdf
];
1107 *domain
= domain_for_device(*bdf
);
1108 if (*domain
== NULL
) {
1109 dma_dom
= find_protection_domain(*bdf
);
1111 dma_dom
= (*iommu
)->default_dom
;
1112 *domain
= &dma_dom
->domain
;
1113 attach_device(*iommu
, *domain
, *bdf
);
1114 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
1115 "device %s\n", (*domain
)->id
, dev_name(dev
));
1118 if (domain_for_device(_bdf
) == NULL
)
1119 attach_device(*iommu
, *domain
, _bdf
);
1125 * If the pte_page is not yet allocated this function is called
1127 static u64
* alloc_pte(struct protection_domain
*dom
,
1128 unsigned long address
, u64
**pte_page
, gfp_t gfp
)
1132 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(address
)];
1134 if (!IOMMU_PTE_PRESENT(*pte
)) {
1135 page
= (u64
*)get_zeroed_page(gfp
);
1138 *pte
= IOMMU_L2_PDE(virt_to_phys(page
));
1141 pte
= IOMMU_PTE_PAGE(*pte
);
1142 pte
= &pte
[IOMMU_PTE_L1_INDEX(address
)];
1144 if (!IOMMU_PTE_PRESENT(*pte
)) {
1145 page
= (u64
*)get_zeroed_page(gfp
);
1148 *pte
= IOMMU_L1_PDE(virt_to_phys(page
));
1151 pte
= IOMMU_PTE_PAGE(*pte
);
1156 pte
= &pte
[IOMMU_PTE_L0_INDEX(address
)];
1162 * This function fetches the PTE for a given address in the aperture
1164 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
1165 unsigned long address
)
1167 struct aperture_range
*aperture
= &dom
->aperture
;
1168 u64
*pte
, *pte_page
;
1170 pte
= aperture
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
1172 pte
= alloc_pte(&dom
->domain
, address
, &pte_page
, GFP_ATOMIC
);
1173 aperture
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)] = pte_page
;
1180 * This is the generic map function. It maps one 4kb page at paddr to
1181 * the given address in the DMA address space for the domain.
1183 static dma_addr_t
dma_ops_domain_map(struct amd_iommu
*iommu
,
1184 struct dma_ops_domain
*dom
,
1185 unsigned long address
,
1191 WARN_ON(address
> dom
->aperture_size
);
1195 pte
= dma_ops_get_pte(dom
, address
);
1197 return bad_dma_address
;
1199 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1201 if (direction
== DMA_TO_DEVICE
)
1202 __pte
|= IOMMU_PTE_IR
;
1203 else if (direction
== DMA_FROM_DEVICE
)
1204 __pte
|= IOMMU_PTE_IW
;
1205 else if (direction
== DMA_BIDIRECTIONAL
)
1206 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1212 return (dma_addr_t
)address
;
1216 * The generic unmapping function for on page in the DMA address space.
1218 static void dma_ops_domain_unmap(struct amd_iommu
*iommu
,
1219 struct dma_ops_domain
*dom
,
1220 unsigned long address
)
1224 if (address
>= dom
->aperture_size
)
1227 WARN_ON(address
& ~PAGE_MASK
|| address
>= dom
->aperture_size
);
1229 pte
= dom
->aperture
.pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
1230 pte
+= IOMMU_PTE_L0_INDEX(address
);
1238 * This function contains common code for mapping of a physically
1239 * contiguous memory region into DMA address space. It is used by all
1240 * mapping functions provided with this IOMMU driver.
1241 * Must be called with the domain lock held.
1243 static dma_addr_t
__map_single(struct device
*dev
,
1244 struct amd_iommu
*iommu
,
1245 struct dma_ops_domain
*dma_dom
,
1252 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1253 dma_addr_t address
, start
, ret
;
1255 unsigned long align_mask
= 0;
1258 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1261 INC_STATS_COUNTER(total_map_requests
);
1264 INC_STATS_COUNTER(cross_page
);
1267 align_mask
= (1UL << get_order(size
)) - 1;
1269 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1271 if (unlikely(address
== bad_dma_address
))
1275 for (i
= 0; i
< pages
; ++i
) {
1276 ret
= dma_ops_domain_map(iommu
, dma_dom
, start
, paddr
, dir
);
1277 if (ret
== bad_dma_address
)
1285 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1287 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1288 iommu_flush_tlb(iommu
, dma_dom
->domain
.id
);
1289 dma_dom
->need_flush
= false;
1290 } else if (unlikely(iommu_has_npcache(iommu
)))
1291 iommu_flush_pages(iommu
, dma_dom
->domain
.id
, address
, size
);
1298 for (--i
; i
>= 0; --i
) {
1300 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
1303 dma_ops_free_addresses(dma_dom
, address
, pages
);
1305 return bad_dma_address
;
1309 * Does the reverse of the __map_single function. Must be called with
1310 * the domain lock held too
1312 static void __unmap_single(struct amd_iommu
*iommu
,
1313 struct dma_ops_domain
*dma_dom
,
1314 dma_addr_t dma_addr
,
1318 dma_addr_t i
, start
;
1321 if ((dma_addr
== bad_dma_address
) ||
1322 (dma_addr
+ size
> dma_dom
->aperture_size
))
1325 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1326 dma_addr
&= PAGE_MASK
;
1329 for (i
= 0; i
< pages
; ++i
) {
1330 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
1334 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1336 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1338 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
1339 iommu_flush_pages(iommu
, dma_dom
->domain
.id
, dma_addr
, size
);
1340 dma_dom
->need_flush
= false;
1345 * The exported map_single function for dma_ops.
1347 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
1348 unsigned long offset
, size_t size
,
1349 enum dma_data_direction dir
,
1350 struct dma_attrs
*attrs
)
1352 unsigned long flags
;
1353 struct amd_iommu
*iommu
;
1354 struct protection_domain
*domain
;
1358 phys_addr_t paddr
= page_to_phys(page
) + offset
;
1360 INC_STATS_COUNTER(cnt_map_single
);
1362 if (!check_device(dev
))
1363 return bad_dma_address
;
1365 dma_mask
= *dev
->dma_mask
;
1367 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1369 if (iommu
== NULL
|| domain
== NULL
)
1370 /* device not handled by any AMD IOMMU */
1371 return (dma_addr_t
)paddr
;
1373 if (!dma_ops_domain(domain
))
1374 return bad_dma_address
;
1376 spin_lock_irqsave(&domain
->lock
, flags
);
1377 addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
, size
, dir
, false,
1379 if (addr
== bad_dma_address
)
1382 iommu_completion_wait(iommu
);
1385 spin_unlock_irqrestore(&domain
->lock
, flags
);
1391 * The exported unmap_single function for dma_ops.
1393 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
1394 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
1396 unsigned long flags
;
1397 struct amd_iommu
*iommu
;
1398 struct protection_domain
*domain
;
1401 INC_STATS_COUNTER(cnt_unmap_single
);
1403 if (!check_device(dev
) ||
1404 !get_device_resources(dev
, &iommu
, &domain
, &devid
))
1405 /* device not handled by any AMD IOMMU */
1408 if (!dma_ops_domain(domain
))
1411 spin_lock_irqsave(&domain
->lock
, flags
);
1413 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, dir
);
1415 iommu_completion_wait(iommu
);
1417 spin_unlock_irqrestore(&domain
->lock
, flags
);
1421 * This is a special map_sg function which is used if we should map a
1422 * device which is not handled by an AMD IOMMU in the system.
1424 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
1425 int nelems
, int dir
)
1427 struct scatterlist
*s
;
1430 for_each_sg(sglist
, s
, nelems
, i
) {
1431 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
1432 s
->dma_length
= s
->length
;
1439 * The exported map_sg function for dma_ops (handles scatter-gather
1442 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
1443 int nelems
, enum dma_data_direction dir
,
1444 struct dma_attrs
*attrs
)
1446 unsigned long flags
;
1447 struct amd_iommu
*iommu
;
1448 struct protection_domain
*domain
;
1451 struct scatterlist
*s
;
1453 int mapped_elems
= 0;
1456 INC_STATS_COUNTER(cnt_map_sg
);
1458 if (!check_device(dev
))
1461 dma_mask
= *dev
->dma_mask
;
1463 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1465 if (!iommu
|| !domain
)
1466 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
1468 if (!dma_ops_domain(domain
))
1471 spin_lock_irqsave(&domain
->lock
, flags
);
1473 for_each_sg(sglist
, s
, nelems
, i
) {
1476 s
->dma_address
= __map_single(dev
, iommu
, domain
->priv
,
1477 paddr
, s
->length
, dir
, false,
1480 if (s
->dma_address
) {
1481 s
->dma_length
= s
->length
;
1487 iommu_completion_wait(iommu
);
1490 spin_unlock_irqrestore(&domain
->lock
, flags
);
1492 return mapped_elems
;
1494 for_each_sg(sglist
, s
, mapped_elems
, i
) {
1496 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
1497 s
->dma_length
, dir
);
1498 s
->dma_address
= s
->dma_length
= 0;
1507 * The exported map_sg function for dma_ops (handles scatter-gather
1510 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
1511 int nelems
, enum dma_data_direction dir
,
1512 struct dma_attrs
*attrs
)
1514 unsigned long flags
;
1515 struct amd_iommu
*iommu
;
1516 struct protection_domain
*domain
;
1517 struct scatterlist
*s
;
1521 INC_STATS_COUNTER(cnt_unmap_sg
);
1523 if (!check_device(dev
) ||
1524 !get_device_resources(dev
, &iommu
, &domain
, &devid
))
1527 if (!dma_ops_domain(domain
))
1530 spin_lock_irqsave(&domain
->lock
, flags
);
1532 for_each_sg(sglist
, s
, nelems
, i
) {
1533 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
1534 s
->dma_length
, dir
);
1535 s
->dma_address
= s
->dma_length
= 0;
1538 iommu_completion_wait(iommu
);
1540 spin_unlock_irqrestore(&domain
->lock
, flags
);
1544 * The exported alloc_coherent function for dma_ops.
1546 static void *alloc_coherent(struct device
*dev
, size_t size
,
1547 dma_addr_t
*dma_addr
, gfp_t flag
)
1549 unsigned long flags
;
1551 struct amd_iommu
*iommu
;
1552 struct protection_domain
*domain
;
1555 u64 dma_mask
= dev
->coherent_dma_mask
;
1557 INC_STATS_COUNTER(cnt_alloc_coherent
);
1559 if (!check_device(dev
))
1562 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
1563 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
1566 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
1570 paddr
= virt_to_phys(virt_addr
);
1572 if (!iommu
|| !domain
) {
1573 *dma_addr
= (dma_addr_t
)paddr
;
1577 if (!dma_ops_domain(domain
))
1581 dma_mask
= *dev
->dma_mask
;
1583 spin_lock_irqsave(&domain
->lock
, flags
);
1585 *dma_addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
,
1586 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
1588 if (*dma_addr
== bad_dma_address
)
1591 iommu_completion_wait(iommu
);
1593 spin_unlock_irqrestore(&domain
->lock
, flags
);
1599 free_pages((unsigned long)virt_addr
, get_order(size
));
1605 * The exported free_coherent function for dma_ops.
1607 static void free_coherent(struct device
*dev
, size_t size
,
1608 void *virt_addr
, dma_addr_t dma_addr
)
1610 unsigned long flags
;
1611 struct amd_iommu
*iommu
;
1612 struct protection_domain
*domain
;
1615 INC_STATS_COUNTER(cnt_free_coherent
);
1617 if (!check_device(dev
))
1620 get_device_resources(dev
, &iommu
, &domain
, &devid
);
1622 if (!iommu
|| !domain
)
1625 if (!dma_ops_domain(domain
))
1628 spin_lock_irqsave(&domain
->lock
, flags
);
1630 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
1632 iommu_completion_wait(iommu
);
1634 spin_unlock_irqrestore(&domain
->lock
, flags
);
1637 free_pages((unsigned long)virt_addr
, get_order(size
));
1641 * This function is called by the DMA layer to find out if we can handle a
1642 * particular device. It is part of the dma_ops.
1644 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
1647 struct pci_dev
*pcidev
;
1649 /* No device or no PCI device */
1650 if (!dev
|| dev
->bus
!= &pci_bus_type
)
1653 pcidev
= to_pci_dev(dev
);
1655 bdf
= calc_devid(pcidev
->bus
->number
, pcidev
->devfn
);
1657 /* Out of our scope? */
1658 if (bdf
> amd_iommu_last_bdf
)
1665 * The function for pre-allocating protection domains.
1667 * If the driver core informs the DMA layer if a driver grabs a device
1668 * we don't need to preallocate the protection domains anymore.
1669 * For now we have to.
1671 static void prealloc_protection_domains(void)
1673 struct pci_dev
*dev
= NULL
;
1674 struct dma_ops_domain
*dma_dom
;
1675 struct amd_iommu
*iommu
;
1676 int order
= amd_iommu_aperture_order
;
1679 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1680 devid
= calc_devid(dev
->bus
->number
, dev
->devfn
);
1681 if (devid
> amd_iommu_last_bdf
)
1683 devid
= amd_iommu_alias_table
[devid
];
1684 if (domain_for_device(devid
))
1686 iommu
= amd_iommu_rlookup_table
[devid
];
1689 dma_dom
= dma_ops_domain_alloc(iommu
, order
);
1692 init_unity_mappings_for_device(dma_dom
, devid
);
1693 dma_dom
->target_dev
= devid
;
1695 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
1699 static struct dma_map_ops amd_iommu_dma_ops
= {
1700 .alloc_coherent
= alloc_coherent
,
1701 .free_coherent
= free_coherent
,
1702 .map_page
= map_page
,
1703 .unmap_page
= unmap_page
,
1705 .unmap_sg
= unmap_sg
,
1706 .dma_supported
= amd_iommu_dma_supported
,
1710 * The function which clues the AMD IOMMU driver into dma_ops.
1712 int __init
amd_iommu_init_dma_ops(void)
1714 struct amd_iommu
*iommu
;
1715 int order
= amd_iommu_aperture_order
;
1719 * first allocate a default protection domain for every IOMMU we
1720 * found in the system. Devices not assigned to any other
1721 * protection domain will be assigned to the default one.
1723 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
1724 iommu
->default_dom
= dma_ops_domain_alloc(iommu
, order
);
1725 if (iommu
->default_dom
== NULL
)
1727 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
1728 ret
= iommu_init_unity_mappings(iommu
);
1734 * If device isolation is enabled, pre-allocate the protection
1735 * domains for each device.
1737 if (amd_iommu_isolate
)
1738 prealloc_protection_domains();
1742 bad_dma_address
= 0;
1743 #ifdef CONFIG_GART_IOMMU
1744 gart_iommu_aperture_disabled
= 1;
1745 gart_iommu_aperture
= 0;
1748 /* Make the driver finally visible to the drivers */
1749 dma_ops
= &amd_iommu_dma_ops
;
1751 register_iommu(&amd_iommu_ops
);
1753 bus_register_notifier(&pci_bus_type
, &device_nb
);
1755 amd_iommu_stats_init();
1761 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
1762 if (iommu
->default_dom
)
1763 dma_ops_domain_free(iommu
->default_dom
);
1769 /*****************************************************************************
1771 * The following functions belong to the exported interface of AMD IOMMU
1773 * This interface allows access to lower level functions of the IOMMU
1774 * like protection domain handling and assignement of devices to domains
1775 * which is not possible with the dma_ops interface.
1777 *****************************************************************************/
1779 static void cleanup_domain(struct protection_domain
*domain
)
1781 unsigned long flags
;
1784 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1786 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
)
1787 if (amd_iommu_pd_table
[devid
] == domain
)
1788 __detach_device(domain
, devid
);
1790 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1793 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
1795 struct protection_domain
*domain
;
1797 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
1801 spin_lock_init(&domain
->lock
);
1802 domain
->mode
= PAGE_MODE_3_LEVEL
;
1803 domain
->id
= domain_id_alloc();
1806 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1807 if (!domain
->pt_root
)
1820 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
1822 struct protection_domain
*domain
= dom
->priv
;
1827 if (domain
->dev_cnt
> 0)
1828 cleanup_domain(domain
);
1830 BUG_ON(domain
->dev_cnt
!= 0);
1832 free_pagetable(domain
);
1834 domain_id_free(domain
->id
);
1841 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
1844 struct protection_domain
*domain
= dom
->priv
;
1845 struct amd_iommu
*iommu
;
1846 struct pci_dev
*pdev
;
1849 if (dev
->bus
!= &pci_bus_type
)
1852 pdev
= to_pci_dev(dev
);
1854 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
1857 detach_device(domain
, devid
);
1859 iommu
= amd_iommu_rlookup_table
[devid
];
1863 iommu_queue_inv_dev_entry(iommu
, devid
);
1864 iommu_completion_wait(iommu
);
1867 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
1870 struct protection_domain
*domain
= dom
->priv
;
1871 struct protection_domain
*old_domain
;
1872 struct amd_iommu
*iommu
;
1873 struct pci_dev
*pdev
;
1876 if (dev
->bus
!= &pci_bus_type
)
1879 pdev
= to_pci_dev(dev
);
1881 devid
= calc_devid(pdev
->bus
->number
, pdev
->devfn
);
1883 if (devid
>= amd_iommu_last_bdf
||
1884 devid
!= amd_iommu_alias_table
[devid
])
1887 iommu
= amd_iommu_rlookup_table
[devid
];
1891 old_domain
= domain_for_device(devid
);
1895 attach_device(iommu
, domain
, devid
);
1897 iommu_completion_wait(iommu
);
1902 static int amd_iommu_map_range(struct iommu_domain
*dom
,
1903 unsigned long iova
, phys_addr_t paddr
,
1904 size_t size
, int iommu_prot
)
1906 struct protection_domain
*domain
= dom
->priv
;
1907 unsigned long i
, npages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1911 if (iommu_prot
& IOMMU_READ
)
1912 prot
|= IOMMU_PROT_IR
;
1913 if (iommu_prot
& IOMMU_WRITE
)
1914 prot
|= IOMMU_PROT_IW
;
1919 for (i
= 0; i
< npages
; ++i
) {
1920 ret
= iommu_map_page(domain
, iova
, paddr
, prot
);
1931 static void amd_iommu_unmap_range(struct iommu_domain
*dom
,
1932 unsigned long iova
, size_t size
)
1935 struct protection_domain
*domain
= dom
->priv
;
1936 unsigned long i
, npages
= iommu_num_pages(iova
, size
, PAGE_SIZE
);
1940 for (i
= 0; i
< npages
; ++i
) {
1941 iommu_unmap_page(domain
, iova
);
1945 iommu_flush_domain(domain
->id
);
1948 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
1951 struct protection_domain
*domain
= dom
->priv
;
1952 unsigned long offset
= iova
& ~PAGE_MASK
;
1956 pte
= &domain
->pt_root
[IOMMU_PTE_L2_INDEX(iova
)];
1958 if (!IOMMU_PTE_PRESENT(*pte
))
1961 pte
= IOMMU_PTE_PAGE(*pte
);
1962 pte
= &pte
[IOMMU_PTE_L1_INDEX(iova
)];
1964 if (!IOMMU_PTE_PRESENT(*pte
))
1967 pte
= IOMMU_PTE_PAGE(*pte
);
1968 pte
= &pte
[IOMMU_PTE_L0_INDEX(iova
)];
1970 if (!IOMMU_PTE_PRESENT(*pte
))
1973 paddr
= *pte
& IOMMU_PAGE_MASK
;
1979 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
1985 static struct iommu_ops amd_iommu_ops
= {
1986 .domain_init
= amd_iommu_domain_init
,
1987 .domain_destroy
= amd_iommu_domain_destroy
,
1988 .attach_dev
= amd_iommu_attach_device
,
1989 .detach_dev
= amd_iommu_detach_device
,
1990 .map
= amd_iommu_map_range
,
1991 .unmap
= amd_iommu_unmap_range
,
1992 .iova_to_phys
= amd_iommu_iova_to_phys
,
1993 .domain_has_cap
= amd_iommu_domain_has_cap
,