include/asm-x86/processor_32.h

   1 /*
   2  * Copyright (C) 1994 Linus Torvalds
   3  */
   4
   5 #ifndef __ASM_I386_PROCESSOR_H
   6 #define __ASM_I386_PROCESSOR_H
   7
   8 #include <asm/vm86.h>
   9 #include <asm/math_emu.h>
  10 #include <asm/segment.h>
  11 #include <asm/page.h>
  12 #include <asm/types.h>
  13 #include <asm/sigcontext.h>
  14 #include <asm/cpufeature.h>
  15 #include <asm/msr.h>
  16 #include <asm/system.h>
  17 #include <linux/cache.h>
  18 #include <linux/threads.h>
  19 #include <asm/percpu.h>
  20 #include <linux/cpumask.h>
  21 #include <linux/init.h>
  22 #include <asm/desc_defs.h>
  23
  24 /*
  25  * Default implementation of macro that returns current
  26  * instruction pointer ("program counter").
  27  */
  28 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
  29
  30 /*
  31  *  CPU type and hardware bug flags. Kept separately for each CPU.
  32  *  Members of this structure are referenced in head.S, so think twice
  33  *  before touching them. [mj]
  34  */
  35
  36 struct cpuinfo_x86 {
  37         __u8    x86;            /* CPU family */
  38         __u8    x86_vendor;     /* CPU vendor */
  39         __u8    x86_model;
  40         __u8    x86_mask;
  41         char    wp_works_ok;    /* It doesn't on 386's */
  42         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
  43         char    hard_math;
  44         char    rfu;
  45         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
  46         unsigned long   x86_capability[NCAPINTS];
  47         char    x86_vendor_id[16];
  48         char    x86_model_id[64];
  49         int     x86_cache_size;  /* in KB - valid for CPUS which support this
  50                                     call  */
  51         int     x86_cache_alignment;    /* In bytes */
  52         char    fdiv_bug;
  53         char    f00f_bug;
  54         char    coma_bug;
  55         char    pad0;
  56         int     x86_power;
  57         unsigned long loops_per_jiffy;
  58 #ifdef CONFIG_SMP
  59         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
  60 #endif
  61         unsigned char x86_max_cores;    /* cpuid returned max cores value */
  62         unsigned char apicid;
  63         unsigned short x86_clflush_size;
  64 #ifdef CONFIG_SMP
  65         unsigned char booted_cores;     /* number of cores as seen by OS */
  66         __u8 phys_proc_id;              /* Physical processor id. */
  67         __u8 cpu_core_id;               /* Core id */
  68         __u8 cpu_index;                 /* index into per_cpu list */
  69 #endif
  70 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
  71
  72 #define X86_VENDOR_INTEL 0
  73 #define X86_VENDOR_CYRIX 1
  74 #define X86_VENDOR_AMD 2
  75 #define X86_VENDOR_UMC 3
  76 #define X86_VENDOR_NEXGEN 4
  77 #define X86_VENDOR_CENTAUR 5
  78 #define X86_VENDOR_TRANSMETA 7
  79 #define X86_VENDOR_NSC 8
  80 #define X86_VENDOR_NUM 9
  81 #define X86_VENDOR_UNKNOWN 0xff
  82
  83 /*
  84  * capabilities of CPUs
  85  */
  86
  87 extern struct cpuinfo_x86 boot_cpu_data;
  88 extern struct cpuinfo_x86 new_cpu_data;
  89 extern struct tss_struct doublefault_tss;
  90 DECLARE_PER_CPU(struct tss_struct, init_tss);
  91
  92 #ifdef CONFIG_SMP
  93 DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
  94 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
  95 #define current_cpu_data        cpu_data(smp_processor_id())
  96 #else
  97 #define cpu_data(cpu)           boot_cpu_data
  98 #define current_cpu_data        boot_cpu_data
  99 #endif
 100
 101 /*
 102  * the following now lives in the per cpu area:
 103  * extern       int cpu_llc_id[NR_CPUS];
 104  */
 105 DECLARE_PER_CPU(u8, cpu_llc_id);
 106 extern char ignore_fpu_irq;
 107
 108 void __init cpu_detect(struct cpuinfo_x86 *c);
 109
 110 extern void identify_boot_cpu(void);
 111 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
 112 extern void print_cpu_info(struct cpuinfo_x86 *);
 113 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 114 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 115 extern unsigned short num_cache_leaves;
 116
 117 #ifdef CONFIG_X86_HT
 118 extern void detect_ht(struct cpuinfo_x86 *c);
 119 #else
 120 static inline void detect_ht(struct cpuinfo_x86 *c) {}
 121 #endif
 122
 123
 124 /*
 125  * Save the cr4 feature set we're using (ie
 126  * Pentium 4MB enable and PPro Global page
 127  * enable), so that any CPU's that boot up
 128  * after us can get the correct flags.
 129  */
 130 extern unsigned long mmu_cr4_features;
 131
 132 static inline void set_in_cr4 (unsigned long mask)
 133 {
 134         unsigned cr4;
 135         mmu_cr4_features |= mask;
 136         cr4 = read_cr4();
 137         cr4 |= mask;
 138         write_cr4(cr4);
 139 }
 140
 141 static inline void clear_in_cr4 (unsigned long mask)
 142 {
 143         unsigned cr4;
 144         mmu_cr4_features &= ~mask;
 145         cr4 = read_cr4();
 146         cr4 &= ~mask;
 147         write_cr4(cr4);
 148 }
 149
 150 /* Stop speculative execution */
 151 static inline void sync_core(void)
 152 {
 153         int tmp;
 154         asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
 155 }
 156
 157 static inline void __monitor(const void *eax, unsigned long ecx,
 158                 unsigned long edx)
 159 {
 160         /* "monitor %eax,%ecx,%edx;" */
 161         asm volatile(
 162                 ".byte 0x0f,0x01,0xc8;"
 163                 : :"a" (eax), "c" (ecx), "d"(edx));
 164 }
 165
 166 static inline void __mwait(unsigned long eax, unsigned long ecx)
 167 {
 168         /* "mwait %eax,%ecx;" */
 169         asm volatile(
 170                 ".byte 0x0f,0x01,0xc9;"
 171                 : :"a" (eax), "c" (ecx));
 172 }
 173
 174 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 175
 176 /* from system description table in BIOS.  Mostly for MCA use, but
 177 others may find it useful. */
 178 extern unsigned int machine_id;
 179 extern unsigned int machine_submodel_id;
 180 extern unsigned int BIOS_revision;
 181 extern unsigned int mca_pentium_flag;
 182
 183 /* Boot loader type from the setup header */
 184 extern int bootloader_type;
 185
 186 /*
 187  * User space process size: 3GB (default).
 188  */
 189 #define TASK_SIZE       (PAGE_OFFSET)
 190
 191 /* This decides where the kernel will search for a free chunk of vm
 192  * space during mmap's.
 193  */
 194 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 195
 196 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 197
 198 /*
 199  * Size of io_bitmap.
 200  */
 201 #define IO_BITMAP_BITS  65536
 202 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
 203 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
 204 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
 205 #define INVALID_IO_BITMAP_OFFSET 0x8000
 206 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
 207
 208 struct i387_fsave_struct {
 209         long    cwd;
 210         long    swd;
 211         long    twd;
 212         long    fip;
 213         long    fcs;
 214         long    foo;
 215         long    fos;
 216         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 217         long    status;         /* software status information */
 218 };
 219
 220 struct i387_fxsave_struct {
 221         unsigned short  cwd;
 222         unsigned short  swd;
 223         unsigned short  twd;
 224         unsigned short  fop;
 225         long    fip;
 226         long    fcs;
 227         long    foo;
 228         long    fos;
 229         long    mxcsr;
 230         long    mxcsr_mask;
 231         long    st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
 232         long    xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
 233         long    padding[56];
 234 } __attribute__ ((aligned (16)));
 235
 236 struct i387_soft_struct {
 237         long    cwd;
 238         long    swd;
 239         long    twd;
 240         long    fip;
 241         long    fcs;
 242         long    foo;
 243         long    fos;
 244         long    st_space[20];   /* 8*10 bytes for each FP-reg = 80 bytes */
 245         unsigned char   ftop, changed, lookahead, no_update, rm, alimit;
 246         struct info     *info;
 247         unsigned long   entry_eip;
 248 };
 249
 250 union i387_union {
 251         struct i387_fsave_struct        fsave;
 252         struct i387_fxsave_struct       fxsave;
 253         struct i387_soft_struct soft;
 254 };
 255
 256 typedef struct {
 257         unsigned long seg;
 258 } mm_segment_t;
 259
 260 struct thread_struct;
 261
 262 /* This is the TSS defined by the hardware. */
 263 struct i386_hw_tss {
 264         unsigned short  back_link,__blh;
 265         unsigned long   sp0;
 266         unsigned short  ss0,__ss0h;
 267         unsigned long   sp1;
 268         unsigned short  ss1,__ss1h;     /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
 269         unsigned long   sp2;
 270         unsigned short  ss2,__ss2h;
 271         unsigned long   __cr3;
 272         unsigned long   ip;
 273         unsigned long   flags;
 274         unsigned long   ax, cx, dx, bx;
 275         unsigned long   sp, bp, si, di;
 276         unsigned short  es, __esh;
 277         unsigned short  cs, __csh;
 278         unsigned short  ss, __ssh;
 279         unsigned short  ds, __dsh;
 280         unsigned short  fs, __fsh;
 281         unsigned short  gs, __gsh;
 282         unsigned short  ldt, __ldth;
 283         unsigned short  trace, io_bitmap_base;
 284 } __attribute__((packed));
 285
 286 struct tss_struct {
 287         struct i386_hw_tss x86_tss;
 288
 289         /*
 290          * The extra 1 is there because the CPU will access an
 291          * additional byte beyond the end of the IO permission
 292          * bitmap. The extra byte must be all 1 bits, and must
 293          * be within the limit.
 294          */
 295         unsigned long   io_bitmap[IO_BITMAP_LONGS + 1];
 296         /*
 297          * Cache the current maximum and the last task that used the bitmap:
 298          */
 299         unsigned long io_bitmap_max;
 300         struct thread_struct *io_bitmap_owner;
 301         /*
 302          * pads the TSS to be cacheline-aligned (size is 0x100)
 303          */
 304         unsigned long __cacheline_filler[35];
 305         /*
 306          * .. and then another 0x100 bytes for emergency kernel stack
 307          */
 308         unsigned long stack[64];
 309 } __attribute__((packed));
 310
 311 #define ARCH_MIN_TASKALIGN      16
 312
 313 struct thread_struct {
 314 /* cached TLS descriptors. */
 315         struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
 316         unsigned long   sp0;
 317         unsigned long   sysenter_cs;
 318         unsigned long   ip;
 319         unsigned long   sp;
 320         unsigned long   fs;
 321         unsigned long   gs;
 322 /* Hardware debugging registers */
 323         unsigned long   debugreg0;
 324         unsigned long   debugreg1;
 325         unsigned long   debugreg2;
 326         unsigned long   debugreg3;
 327         unsigned long   debugreg6;
 328         unsigned long   debugreg7;
 329 /* fault info */
 330         unsigned long   cr2, trap_no, error_code;
 331 /* floating point info */
 332         union i387_union        i387;
 333 /* virtual 86 mode info */
 334         struct vm86_struct __user * vm86_info;
 335         unsigned long           screen_bitmap;
 336         unsigned long           v86flags, v86mask, saved_sp0;
 337         unsigned int            saved_fs, saved_gs;
 338 /* IO permissions */
 339         unsigned long   *io_bitmap_ptr;
 340         unsigned long   iopl;
 341 /* max allowed port in the bitmap, in bytes: */
 342         unsigned long   io_bitmap_max;
 343 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
 344         unsigned long   debugctlmsr;
 345 /* Debug Store - if not 0 points to a DS Save Area configuration;
 346  *               goes into MSR_IA32_DS_AREA */
 347         unsigned long   ds_area_msr;
 348 };
 349
 350 #define INIT_THREAD  {                                                  \
 351         .sp0 = sizeof(init_stack) + (long)&init_stack,                  \
 352         .vm86_info = NULL,                                              \
 353         .sysenter_cs = __KERNEL_CS,                                     \
 354         .io_bitmap_ptr = NULL,                                          \
 355         .fs = __KERNEL_PERCPU,                                          \
 356 }
 357
 358 /*
 359  * Note that the .io_bitmap member must be extra-big. This is because
 360  * the CPU will access an additional byte beyond the end of the IO
 361  * permission bitmap. The extra byte must be all 1 bits, and must
 362  * be within the limit.
 363  */
 364 #define INIT_TSS  {                                                     \
 365         .x86_tss = {                                                    \
 366                 .sp0            = sizeof(init_stack) + (long)&init_stack, \
 367                 .ss0            = __KERNEL_DS,                          \
 368                 .ss1            = __KERNEL_CS,                          \
 369                 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,             \
 370          },                                                             \
 371         .io_bitmap      = { [ 0 ... IO_BITMAP_LONGS] = ~0 },            \
 372 }
 373
 374 #define start_thread(regs, new_eip, new_esp) do {               \
 375         __asm__("movl %0,%%gs": :"r" (0));                      \
 376         regs->fs = 0;                                           \
 377         set_fs(USER_DS);                                        \
 378         regs->ds = __USER_DS;                                   \
 379         regs->es = __USER_DS;                                   \
 380         regs->ss = __USER_DS;                                   \
 381         regs->cs = __USER_CS;                                   \
 382         regs->ip = new_eip;                                     \
 383         regs->sp = new_esp;                                     \
 384 } while (0)
 385
 386 /* Forward declaration, a strange C thing */
 387 struct task_struct;
 388 struct mm_struct;
 389
 390 /* Free all resources held by a thread. */
 391 extern void release_thread(struct task_struct *);
 392
 393 /* Prepare to copy thread state - unlazy all lazy status */
 394 extern void prepare_to_copy(struct task_struct *tsk);
 395
 396 /*
 397  * create a kernel thread without removing it from tasklists
 398  */
 399 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 400
 401 extern unsigned long thread_saved_pc(struct task_struct *tsk);
 402
 403 unsigned long get_wchan(struct task_struct *p);
 404
 405 #define THREAD_SIZE_LONGS      (THREAD_SIZE/sizeof(unsigned long))
 406 #define KSTK_TOP(info)                                                 \
 407 ({                                                                     \
 408        unsigned long *__ptr = (unsigned long *)(info);                 \
 409        (unsigned long)(&__ptr[THREAD_SIZE_LONGS]);                     \
 410 })
 411
 412 /*
 413  * The below -8 is to reserve 8 bytes on top of the ring0 stack.
 414  * This is necessary to guarantee that the entire "struct pt_regs"
 415  * is accessable even if the CPU haven't stored the SS/ESP registers
 416  * on the stack (interrupt gate does not save these registers
 417  * when switching to the same priv ring).
 418  * Therefore beware: accessing the ss/esp fields of the
 419  * "struct pt_regs" is possible, but they may contain the
 420  * completely wrong values.
 421  */
 422 #define task_pt_regs(task)                                             \
 423 ({                                                                     \
 424        struct pt_regs *__regs__;                                       \
 425        __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
 426        __regs__ - 1;                                                   \
 427 })
 428
 429 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
 430 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
 431
 432
 433 struct microcode_header {
 434         unsigned int hdrver;
 435         unsigned int rev;
 436         unsigned int date;
 437         unsigned int sig;
 438         unsigned int cksum;
 439         unsigned int ldrver;
 440         unsigned int pf;
 441         unsigned int datasize;
 442         unsigned int totalsize;
 443         unsigned int reserved[3];
 444 };
 445
 446 struct microcode {
 447         struct microcode_header hdr;
 448         unsigned int bits[0];
 449 };
 450
 451 typedef struct microcode microcode_t;
 452 typedef struct microcode_header microcode_header_t;
 453
 454 /* microcode format is extended from prescott processors */
 455 struct extended_signature {
 456         unsigned int sig;
 457         unsigned int pf;
 458         unsigned int cksum;
 459 };
 460
 461 struct extended_sigtable {
 462         unsigned int count;
 463         unsigned int cksum;
 464         unsigned int reserved[3];
 465         struct extended_signature sigs[0];
 466 };
 467
 468 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
 469 static inline void rep_nop(void)
 470 {
 471         __asm__ __volatile__("rep;nop": : :"memory");
 472 }
 473
 474 #define cpu_relax()     rep_nop()
 475
 476 static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 477 {
 478         tss->x86_tss.sp0 = thread->sp0;
 479         /* This can only happen when SEP is enabled, no need to test "SEP"arately */
 480         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
 481                 tss->x86_tss.ss1 = thread->sysenter_cs;
 482                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
 483         }
 484 }
 485
 486
 487 static inline unsigned long native_get_debugreg(int regno)
 488 {
 489         unsigned long val = 0;  /* Damn you, gcc! */
 490
 491         switch (regno) {
 492         case 0:
 493                 asm("movl %%db0, %0" :"=r" (val)); break;
 494         case 1:
 495                 asm("movl %%db1, %0" :"=r" (val)); break;
 496         case 2:
 497                 asm("movl %%db2, %0" :"=r" (val)); break;
 498         case 3:
 499                 asm("movl %%db3, %0" :"=r" (val)); break;
 500         case 6:
 501                 asm("movl %%db6, %0" :"=r" (val)); break;
 502         case 7:
 503                 asm("movl %%db7, %0" :"=r" (val)); break;
 504         default:
 505                 BUG();
 506         }
 507         return val;
 508 }
 509
 510 static inline void native_set_debugreg(int regno, unsigned long value)
 511 {
 512         switch (regno) {
 513         case 0:
 514                 asm("movl %0,%%db0"     : /* no output */ :"r" (value));
 515                 break;
 516         case 1:
 517                 asm("movl %0,%%db1"     : /* no output */ :"r" (value));
 518                 break;
 519         case 2:
 520                 asm("movl %0,%%db2"     : /* no output */ :"r" (value));
 521                 break;
 522         case 3:
 523                 asm("movl %0,%%db3"     : /* no output */ :"r" (value));
 524                 break;
 525         case 6:
 526                 asm("movl %0,%%db6"     : /* no output */ :"r" (value));
 527                 break;
 528         case 7:
 529                 asm("movl %0,%%db7"     : /* no output */ :"r" (value));
 530                 break;
 531         default:
 532                 BUG();
 533         }
 534 }
 535
 536 /*
 537  * Set IOPL bits in EFLAGS from given mask
 538  */
 539 static inline void native_set_iopl_mask(unsigned mask)
 540 {
 541         unsigned int reg;
 542         __asm__ __volatile__ ("pushfl;"
 543                               "popl %0;"
 544                               "andl %1, %0;"
 545                               "orl %2, %0;"
 546                               "pushl %0;"
 547                               "popfl"
 548                                 : "=&r" (reg)
 549                                 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
 550 }
 551
 552 #ifdef CONFIG_PARAVIRT
 553 #include <asm/paravirt.h>
 554 #else
 555 #define paravirt_enabled() 0
 556
 557 static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
 558 {
 559         native_load_sp0(tss, thread);
 560 }
 561
 562 /*
 563  * These special macros can be used to get or set a debugging register
 564  */
 565 #define get_debugreg(var, register)                             \
 566         (var) = native_get_debugreg(register)
 567 #define set_debugreg(value, register)                           \
 568         native_set_debugreg(register, value)
 569
 570 #define set_iopl_mask native_set_iopl_mask
 571 #endif /* CONFIG_PARAVIRT */
 572
 573 /* generic versions from gas */
 574 #define GENERIC_NOP1    ".byte 0x90\n"
 575 #define GENERIC_NOP2            ".byte 0x89,0xf6\n"
 576 #define GENERIC_NOP3        ".byte 0x8d,0x76,0x00\n"
 577 #define GENERIC_NOP4        ".byte 0x8d,0x74,0x26,0x00\n"
 578 #define GENERIC_NOP5        GENERIC_NOP1 GENERIC_NOP4
 579 #define GENERIC_NOP6    ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
 580 #define GENERIC_NOP7    ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
 581 #define GENERIC_NOP8    GENERIC_NOP1 GENERIC_NOP7
 582
 583 /* Opteron nops */
 584 #define K8_NOP1 GENERIC_NOP1
 585 #define K8_NOP2 ".byte 0x66,0x90\n"
 586 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
 587 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
 588 #define K8_NOP5 K8_NOP3 K8_NOP2
 589 #define K8_NOP6 K8_NOP3 K8_NOP3
 590 #define K8_NOP7 K8_NOP4 K8_NOP3
 591 #define K8_NOP8 K8_NOP4 K8_NOP4
 592
 593 /* K7 nops */
 594 /* uses eax dependencies (arbitary choice) */
 595 #define K7_NOP1  GENERIC_NOP1
 596 #define K7_NOP2 ".byte 0x8b,0xc0\n"
 597 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
 598 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
 599 #define K7_NOP5 K7_NOP4 ASM_NOP1
 600 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
 601 #define K7_NOP7        ".byte 0x8D,0x04,0x05,0,0,0,0\n"
 602 #define K7_NOP8        K7_NOP7 ASM_NOP1
 603
 604 /* P6 nops */
 605 /* uses eax dependencies (Intel-recommended choice) */
 606 #define P6_NOP1 GENERIC_NOP1
 607 #define P6_NOP2 ".byte 0x66,0x90\n"
 608 #define P6_NOP3 ".byte 0x0f,0x1f,0x00\n"
 609 #define P6_NOP4 ".byte 0x0f,0x1f,0x40,0\n"
 610 #define P6_NOP5 ".byte 0x0f,0x1f,0x44,0x00,0\n"
 611 #define P6_NOP6 ".byte 0x66,0x0f,0x1f,0x44,0x00,0\n"
 612 #define P6_NOP7 ".byte 0x0f,0x1f,0x80,0,0,0,0\n"
 613 #define P6_NOP8 ".byte 0x0f,0x1f,0x84,0x00,0,0,0,0\n"
 614
 615 #ifdef CONFIG_MK8
 616 #define ASM_NOP1 K8_NOP1
 617 #define ASM_NOP2 K8_NOP2
 618 #define ASM_NOP3 K8_NOP3
 619 #define ASM_NOP4 K8_NOP4
 620 #define ASM_NOP5 K8_NOP5
 621 #define ASM_NOP6 K8_NOP6
 622 #define ASM_NOP7 K8_NOP7
 623 #define ASM_NOP8 K8_NOP8
 624 #elif defined(CONFIG_MK7)
 625 #define ASM_NOP1 K7_NOP1
 626 #define ASM_NOP2 K7_NOP2
 627 #define ASM_NOP3 K7_NOP3
 628 #define ASM_NOP4 K7_NOP4
 629 #define ASM_NOP5 K7_NOP5
 630 #define ASM_NOP6 K7_NOP6
 631 #define ASM_NOP7 K7_NOP7
 632 #define ASM_NOP8 K7_NOP8
 633 #elif defined(CONFIG_M686) || defined(CONFIG_MPENTIUMII) || \
 634       defined(CONFIG_MPENTIUMIII) || defined(CONFIG_MPENTIUMM) || \
 635       defined(CONFIG_MCORE2) || defined(CONFIG_PENTIUM4)
 636 #define ASM_NOP1 P6_NOP1
 637 #define ASM_NOP2 P6_NOP2
 638 #define ASM_NOP3 P6_NOP3
 639 #define ASM_NOP4 P6_NOP4
 640 #define ASM_NOP5 P6_NOP5
 641 #define ASM_NOP6 P6_NOP6
 642 #define ASM_NOP7 P6_NOP7
 643 #define ASM_NOP8 P6_NOP8
 644 #else
 645 #define ASM_NOP1 GENERIC_NOP1
 646 #define ASM_NOP2 GENERIC_NOP2
 647 #define ASM_NOP3 GENERIC_NOP3
 648 #define ASM_NOP4 GENERIC_NOP4
 649 #define ASM_NOP5 GENERIC_NOP5
 650 #define ASM_NOP6 GENERIC_NOP6
 651 #define ASM_NOP7 GENERIC_NOP7
 652 #define ASM_NOP8 GENERIC_NOP8
 653 #endif
 654
 655 #define ASM_NOP_MAX 8
 656
 657 /* Prefetch instructions for Pentium III and AMD Athlon */
 658 /* It's not worth to care about 3dnow! prefetches for the K6
 659    because they are microcoded there and very slow.
 660    However we don't do prefetches for pre XP Athlons currently
 661    That should be fixed. */
 662 #define ARCH_HAS_PREFETCH
 663 static inline void prefetch(const void *x)
 664 {
 665         alternative_input(ASM_NOP4,
 666                           "prefetchnta (%1)",
 667                           X86_FEATURE_XMM,
 668                           "r" (x));
 669 }
 670
 671 #define ARCH_HAS_PREFETCH
 672 #define ARCH_HAS_PREFETCHW
 673 #define ARCH_HAS_SPINLOCK_PREFETCH
 674
 675 /* 3dnow! prefetch to get an exclusive cache line. Useful for
 676    spinlocks to avoid one state transition in the cache coherency protocol. */
 677 static inline void prefetchw(const void *x)
 678 {
 679         alternative_input(ASM_NOP4,
 680                           "prefetchw (%1)",
 681                           X86_FEATURE_3DNOW,
 682                           "r" (x));
 683 }
 684 #define spin_lock_prefetch(x)   prefetchw(x)
 685
 686 extern void select_idle_routine(const struct cpuinfo_x86 *c);
 687
 688 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
 689
 690 extern unsigned long boot_option_idle_override;
 691 extern void enable_sep_cpu(void);
 692 extern int sysenter_setup(void);
 693
 694 /* Defined in head.S */
 695 extern struct desc_ptr early_gdt_descr;
 696
 697 extern void cpu_set_gdt(int);
 698 extern void switch_to_new_gdt(void);
 699 extern void cpu_init(void);
 700 extern void init_gdt(int cpu);
 701
 702 extern int force_mwait;
 703
 704 #endif /* __ASM_I386_PROCESSOR_H */