include/asm-arm/arch-s3c2410/regs-clock.h

   1 /* linux/include/asm/arch-s3c2410/regs-clock.h
   2  *
   3  * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
   4  *                    http://armlinux.simtec.co.uk/
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * S3C2410 clock register definitions
  11  *
  12  *  Changelog:
  13  *    18-Aug-2004 Ben Dooks         Added 2440 definitions
  14  *    08-Aug-2004 Herbert Pötzl     Added CLKCON definitions
  15  *    19-06-2003  Ben Dooks         Created file
  16  *    12-03-2004  Ben Dooks         Updated include protection
  17  *    29-Sep-2004 Ben Dooks         Fixed usage for assembly inclusion
  18  *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
  19  *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
  20  *    27-Aug-2005 Ben Dooks         Add clock-slow info
  21  *    20-Oct-2005 Ben Dooks         Fixed overflow in PLL (Guillaume Gourat)
  22 */
  23
  24 #ifndef __ASM_ARM_REGS_CLOCK
  25 #define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
  26
  27 #define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
  28
  29 #define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
  30
  31 #define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
  32 #define S3C2410_MPLLCON     S3C2410_CLKREG(0x04)
  33 #define S3C2410_UPLLCON     S3C2410_CLKREG(0x08)
  34 #define S3C2410_CLKCON      S3C2410_CLKREG(0x0C)
  35 #define S3C2410_CLKSLOW     S3C2410_CLKREG(0x10)
  36 #define S3C2410_CLKDIVN     S3C2410_CLKREG(0x14)
  37
  38 #define S3C2410_CLKCON_IDLE          (1<<2)
  39 #define S3C2410_CLKCON_POWER         (1<<3)
  40 #define S3C2410_CLKCON_NAND          (1<<4)
  41 #define S3C2410_CLKCON_LCDC          (1<<5)
  42 #define S3C2410_CLKCON_USBH          (1<<6)
  43 #define S3C2410_CLKCON_USBD          (1<<7)
  44 #define S3C2410_CLKCON_PWMT          (1<<8)
  45 #define S3C2410_CLKCON_SDI           (1<<9)
  46 #define S3C2410_CLKCON_UART0         (1<<10)
  47 #define S3C2410_CLKCON_UART1         (1<<11)
  48 #define S3C2410_CLKCON_UART2         (1<<12)
  49 #define S3C2410_CLKCON_GPIO          (1<<13)
  50 #define S3C2410_CLKCON_RTC           (1<<14)
  51 #define S3C2410_CLKCON_ADC           (1<<15)
  52 #define S3C2410_CLKCON_IIC           (1<<16)
  53 #define S3C2410_CLKCON_IIS           (1<<17)
  54 #define S3C2410_CLKCON_SPI           (1<<18)
  55
  56 #define S3C2410_PLLCON_MDIVSHIFT     12
  57 #define S3C2410_PLLCON_PDIVSHIFT     4
  58 #define S3C2410_PLLCON_SDIVSHIFT     0
  59 #define S3C2410_PLLCON_MDIVMASK      ((1<<(1+(19-12)))-1)
  60 #define S3C2410_PLLCON_PDIVMASK      ((1<<5)-1)
  61 #define S3C2410_PLLCON_SDIVMASK      3
  62
  63 /* DCLKCON register addresses in gpio.h */
  64
  65 #define S3C2410_DCLKCON_DCLK0EN      (1<<0)
  66 #define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
  67 #define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
  68 #define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
  69 #define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
  70
  71 #define S3C2410_DCLKCON_DCLK1EN      (1<<16)
  72 #define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
  73 #define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
  74 #define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
  75
  76 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
  77 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
  78
  79 #define S3C2410_CLKSLOW_UCLK_OFF        (1<<7)
  80 #define S3C2410_CLKSLOW_MPLL_OFF        (1<<5)
  81 #define S3C2410_CLKSLOW_SLOW            (1<<4)
  82 #define S3C2410_CLKSLOW_SLOWVAL(x)      (x)
  83 #define S3C2410_CLKSLOW_GET_SLOWVAL(x)  ((x) & 7)
  84
  85 #ifndef __ASSEMBLY__
  86
  87 #include <asm/div64.h>
  88
  89 static inline unsigned int
  90 s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
  91 {
  92         unsigned int mdiv, pdiv, sdiv;
  93         uint64_t fvco;
  94
  95         mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
  96         pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
  97         sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
  98
  99         mdiv &= S3C2410_PLLCON_MDIVMASK;
 100         pdiv &= S3C2410_PLLCON_PDIVMASK;
 101         sdiv &= S3C2410_PLLCON_SDIVMASK;
 102
 103         fvco = (uint64_t)baseclk * (mdiv + 8);
 104         do_div(fvco, (pdiv + 2) << sdiv);
 105
 106         return (unsigned int)fvco;
 107 }
 108
 109 #endif /* __ASSEMBLY__ */
 110
 111 #ifdef CONFIG_CPU_S3C2440
 112
 113 /* extra registers */
 114 #define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
 115
 116 #define S3C2440_CLKCON_CAMERA        (1<<19)
 117 #define S3C2440_CLKCON_AC97          (1<<20)
 118
 119 #define S3C2440_CLKDIVN_PDIVN        (1<<0)
 120 #define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
 121 #define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
 122 #define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
 123 #define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
 124 #define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
 125 #define S3C2440_CLKDIVN_UCLK         (1<<3)
 126
 127 #define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
 128 #define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
 129 #define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
 130 #define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
 131 #define S3C2440_CAMDIVN_DVSEN        (1<<12)
 132
 133 #endif /* CONFIG_CPU_S3C2440 */
 134
 135
 136 #endif /* __ASM_ARM_REGS_CLOCK */