2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/sysdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/amba/bus.h>
28 #include <linux/amba/clcd.h>
30 #include <asm/cnt32_to_63.h>
31 #include <asm/system.h>
32 #include <asm/hardware.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
38 #include <asm/hardware/vic.h>
39 #include <asm/mach-types.h>
41 #include <asm/mach/arch.h>
42 #include <asm/mach/flash.h>
43 #include <asm/mach/irq.h>
44 #include <asm/mach/time.h>
45 #include <asm/mach/map.h>
46 #include <asm/mach/mmc.h>
52 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
55 * Setup a VA for the Versatile Vectored Interrupt Controller.
57 #define __io_address(n) __io(IO_ADDRESS(n))
58 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
59 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
61 static void sic_mask_irq(unsigned int irq
)
64 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
67 static void sic_unmask_irq(unsigned int irq
)
70 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_SET
);
73 static struct irq_chip sic_chip
= {
77 .unmask
= sic_unmask_irq
,
81 sic_handle_irq(unsigned int irq
, struct irqdesc
*desc
)
83 unsigned long status
= readl(VA_SIC_BASE
+ SIC_IRQ_STATUS
);
86 do_bad_IRQ(irq
, desc
);
91 irq
= ffs(status
) - 1;
92 status
&= ~(1 << irq
);
96 desc
= irq_desc
+ irq
;
97 desc_handle_irq(irq
, desc
);
102 #define IRQ_MMCI0A IRQ_VICSOURCE22
103 #define IRQ_AACI IRQ_VICSOURCE24
104 #define IRQ_ETH IRQ_VICSOURCE25
105 #define PIC_MASK 0xFFD00000
107 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
108 #define IRQ_AACI IRQ_SIC_AACI
109 #define IRQ_ETH IRQ_SIC_ETH
113 void __init
versatile_init_irq(void)
117 vic_init(VA_VIC_BASE
, IRQ_VIC_START
, ~0);
119 set_irq_chained_handler(IRQ_VICSOURCE31
, sic_handle_irq
);
121 /* Do second interrupt controller */
122 writel(~0, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
124 for (i
= IRQ_SIC_START
; i
<= IRQ_SIC_END
; i
++) {
125 if ((PIC_MASK
& (1 << (i
- IRQ_SIC_START
))) == 0) {
126 set_irq_chip(i
, &sic_chip
);
127 set_irq_handler(i
, do_level_IRQ
);
128 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
133 * Interrupts on secondary controller from 0 to 8 are routed to
135 * Interrupts from 21 to 31 are routed directly to the VIC on
136 * the corresponding number on primary controller. This is controlled
137 * by setting PIC_ENABLEx.
139 writel(PIC_MASK
, VA_SIC_BASE
+ SIC_INT_PIC_ENABLE
);
142 static struct map_desc versatile_io_desc
[] __initdata
= {
144 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE
),
145 .pfn
= __phys_to_pfn(VERSATILE_SYS_BASE
),
149 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE
),
150 .pfn
= __phys_to_pfn(VERSATILE_SIC_BASE
),
154 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE
),
155 .pfn
= __phys_to_pfn(VERSATILE_VIC_BASE
),
159 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE
),
160 .pfn
= __phys_to_pfn(VERSATILE_SCTL_BASE
),
164 #ifdef CONFIG_MACH_VERSATILE_AB
166 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE
),
167 .pfn
= __phys_to_pfn(VERSATILE_GPIO0_BASE
),
171 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE
),
172 .pfn
= __phys_to_pfn(VERSATILE_IB2_BASE
),
177 #ifdef CONFIG_DEBUG_LL
179 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE
),
180 .pfn
= __phys_to_pfn(VERSATILE_UART0_BASE
),
187 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE
),
188 .pfn
= __phys_to_pfn(VERSATILE_PCI_CORE_BASE
),
192 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE
,
193 .pfn
= __phys_to_pfn(VERSATILE_PCI_BASE
),
194 .length
= VERSATILE_PCI_BASE_SIZE
,
197 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE
,
198 .pfn
= __phys_to_pfn(VERSATILE_PCI_CFG_BASE
),
199 .length
= VERSATILE_PCI_CFG_BASE_SIZE
,
204 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0
,
205 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0
),
209 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1
,
210 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1
),
214 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2
,
215 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2
),
223 void __init
versatile_map_io(void)
225 iotable_init(versatile_io_desc
, ARRAY_SIZE(versatile_io_desc
));
228 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
231 * This is the Versatile sched_clock implementation. This has
232 * a resolution of 41.7ns, and a maximum value of about 35583 days.
234 * The return value is guaranteed to be monotonic in that range as
235 * long as there is always less than 89 seconds between successive
236 * calls to this function.
238 unsigned long long sched_clock(void)
240 unsigned long long v
= cnt32_to_63(readl(VERSATILE_REFCOUNTER
));
242 /* the <<1 gets rid of the cnt_32_to_63 top bit saving on a bic insn */
250 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
252 static int versatile_flash_init(void)
256 val
= __raw_readl(VERSATILE_FLASHCTRL
);
257 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
258 __raw_writel(val
, VERSATILE_FLASHCTRL
);
263 static void versatile_flash_exit(void)
267 val
= __raw_readl(VERSATILE_FLASHCTRL
);
268 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
269 __raw_writel(val
, VERSATILE_FLASHCTRL
);
272 static void versatile_flash_set_vpp(int on
)
276 val
= __raw_readl(VERSATILE_FLASHCTRL
);
278 val
|= VERSATILE_FLASHPROG_FLVPPEN
;
280 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
281 __raw_writel(val
, VERSATILE_FLASHCTRL
);
284 static struct flash_platform_data versatile_flash_data
= {
285 .map_name
= "cfi_probe",
287 .init
= versatile_flash_init
,
288 .exit
= versatile_flash_exit
,
289 .set_vpp
= versatile_flash_set_vpp
,
292 static struct resource versatile_flash_resource
= {
293 .start
= VERSATILE_FLASH_BASE
,
294 .end
= VERSATILE_FLASH_BASE
+ VERSATILE_FLASH_SIZE
- 1,
295 .flags
= IORESOURCE_MEM
,
298 static struct platform_device versatile_flash_device
= {
302 .platform_data
= &versatile_flash_data
,
305 .resource
= &versatile_flash_resource
,
308 static struct resource smc91x_resources
[] = {
310 .start
= VERSATILE_ETH_BASE
,
311 .end
= VERSATILE_ETH_BASE
+ SZ_64K
- 1,
312 .flags
= IORESOURCE_MEM
,
317 .flags
= IORESOURCE_IRQ
,
321 static struct platform_device smc91x_device
= {
324 .num_resources
= ARRAY_SIZE(smc91x_resources
),
325 .resource
= smc91x_resources
,
328 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
330 unsigned int mmc_status(struct device
*dev
)
332 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
335 if (adev
->res
.start
== VERSATILE_MMCI0_BASE
)
340 return readl(VERSATILE_SYSMCI
) & mask
;
343 static struct mmc_platform_data mmc0_plat_data
= {
344 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
345 .status
= mmc_status
,
351 static const struct icst307_params versatile_oscvco_params
= {
360 static void versatile_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
362 void __iomem
*sys_lock
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_LOCK_OFFSET
;
363 void __iomem
*sys_osc
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_OSCCLCD_OFFSET
;
366 val
= readl(sys_osc
) & ~0x7ffff;
367 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
369 writel(0xa05f, sys_lock
);
370 writel(val
, sys_osc
);
374 static struct clk versatile_clcd_clk
= {
376 .params
= &versatile_oscvco_params
,
377 .setvco
= versatile_oscvco_set
,
383 #define SYS_CLCD_MODE_MASK (3 << 0)
384 #define SYS_CLCD_MODE_888 (0 << 0)
385 #define SYS_CLCD_MODE_5551 (1 << 0)
386 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
387 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
388 #define SYS_CLCD_NLCDIOON (1 << 2)
389 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
390 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
391 #define SYS_CLCD_ID_MASK (0x1f << 8)
392 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
393 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
394 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
395 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
396 #define SYS_CLCD_ID_VGA (0x1f << 8)
398 static struct clcd_panel vga
= {
412 .vmode
= FB_VMODE_NONINTERLACED
,
416 .tim2
= TIM2_BCD
| TIM2_IPC
,
417 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
421 static struct clcd_panel sanyo_3_8_in
= {
423 .name
= "Sanyo QVGA",
435 .vmode
= FB_VMODE_NONINTERLACED
,
440 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
444 static struct clcd_panel sanyo_2_5_in
= {
446 .name
= "Sanyo QVGA Portrait",
457 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
458 .vmode
= FB_VMODE_NONINTERLACED
,
462 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
463 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
467 static struct clcd_panel epson_2_2_in
= {
469 .name
= "Epson QCIF",
481 .vmode
= FB_VMODE_NONINTERLACED
,
485 .tim2
= TIM2_BCD
| TIM2_IPC
,
486 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
491 * Detect which LCD panel is connected, and return the appropriate
492 * clcd_panel structure. Note: we do not have any information on
493 * the required timings for the 8.4in panel, so we presently assume
496 static struct clcd_panel
*versatile_clcd_panel(void)
498 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
499 struct clcd_panel
*panel
= &vga
;
502 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
503 if (val
== SYS_CLCD_ID_SANYO_3_8
)
504 panel
= &sanyo_3_8_in
;
505 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
506 panel
= &sanyo_2_5_in
;
507 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
508 panel
= &epson_2_2_in
;
509 else if (val
== SYS_CLCD_ID_VGA
)
512 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
521 * Disable all display connectors on the interface module.
523 static void versatile_clcd_disable(struct clcd_fb
*fb
)
525 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
528 val
= readl(sys_clcd
);
529 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
530 writel(val
, sys_clcd
);
532 #ifdef CONFIG_MACH_VERSATILE_AB
534 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
536 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
537 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
540 ctrl
= readl(versatile_ib2_ctrl
);
542 writel(ctrl
, versatile_ib2_ctrl
);
548 * Enable the relevant connector on the interface module.
550 static void versatile_clcd_enable(struct clcd_fb
*fb
)
552 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
555 val
= readl(sys_clcd
);
556 val
&= ~SYS_CLCD_MODE_MASK
;
558 switch (fb
->fb
.var
.green
.length
) {
560 val
|= SYS_CLCD_MODE_5551
;
563 val
|= SYS_CLCD_MODE_565_RLSB
;
566 val
|= SYS_CLCD_MODE_888
;
573 writel(val
, sys_clcd
);
576 * And now enable the PSUs
578 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
579 writel(val
, sys_clcd
);
581 #ifdef CONFIG_MACH_VERSATILE_AB
583 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
585 if (machine_is_versatile_ab() && fb
->panel
== &sanyo_2_5_in
) {
586 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
589 ctrl
= readl(versatile_ib2_ctrl
);
591 writel(ctrl
, versatile_ib2_ctrl
);
596 static unsigned long framesize
= SZ_1M
;
598 static int versatile_clcd_setup(struct clcd_fb
*fb
)
602 fb
->panel
= versatile_clcd_panel();
604 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
606 if (!fb
->fb
.screen_base
) {
607 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
611 fb
->fb
.fix
.smem_start
= dma
;
612 fb
->fb
.fix
.smem_len
= framesize
;
617 static int versatile_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
619 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
621 fb
->fb
.fix
.smem_start
,
622 fb
->fb
.fix
.smem_len
);
625 static void versatile_clcd_remove(struct clcd_fb
*fb
)
627 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
628 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
631 static struct clcd_board clcd_plat_data
= {
633 .check
= clcdfb_check
,
634 .decode
= clcdfb_decode
,
635 .disable
= versatile_clcd_disable
,
636 .enable
= versatile_clcd_enable
,
637 .setup
= versatile_clcd_setup
,
638 .mmap
= versatile_clcd_mmap
,
639 .remove
= versatile_clcd_remove
,
642 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
643 #define AACI_DMA { 0x80, 0x81 }
644 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
645 #define MMCI0_DMA { 0x84, 0 }
646 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
647 #define KMI0_DMA { 0, 0 }
648 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
649 #define KMI1_DMA { 0, 0 }
652 * These devices are connected directly to the multi-layer AHB switch
654 #define SMC_IRQ { NO_IRQ, NO_IRQ }
655 #define SMC_DMA { 0, 0 }
656 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
657 #define MPMC_DMA { 0, 0 }
658 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
659 #define CLCD_DMA { 0, 0 }
660 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
661 #define DMAC_DMA { 0, 0 }
664 * These devices are connected via the core APB bridge
666 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
667 #define SCTL_DMA { 0, 0 }
668 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
669 #define WATCHDOG_DMA { 0, 0 }
670 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
671 #define GPIO0_DMA { 0, 0 }
672 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
673 #define GPIO1_DMA { 0, 0 }
674 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
675 #define RTC_DMA { 0, 0 }
678 * These devices are connected via the DMA APB bridge
680 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
681 #define SCI_DMA { 7, 6 }
682 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
683 #define UART0_DMA { 15, 14 }
684 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
685 #define UART1_DMA { 13, 12 }
686 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
687 #define UART2_DMA { 11, 10 }
688 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
689 #define SSP_DMA { 9, 8 }
691 /* FPGA Primecells */
692 AMBA_DEVICE(aaci
, "fpga:04", AACI
, NULL
);
693 AMBA_DEVICE(mmc0
, "fpga:05", MMCI0
, &mmc0_plat_data
);
694 AMBA_DEVICE(kmi0
, "fpga:06", KMI0
, NULL
);
695 AMBA_DEVICE(kmi1
, "fpga:07", KMI1
, NULL
);
697 /* DevChip Primecells */
698 AMBA_DEVICE(smc
, "dev:00", SMC
, NULL
);
699 AMBA_DEVICE(mpmc
, "dev:10", MPMC
, NULL
);
700 AMBA_DEVICE(clcd
, "dev:20", CLCD
, &clcd_plat_data
);
701 AMBA_DEVICE(dmac
, "dev:30", DMAC
, NULL
);
702 AMBA_DEVICE(sctl
, "dev:e0", SCTL
, NULL
);
703 AMBA_DEVICE(wdog
, "dev:e1", WATCHDOG
, NULL
);
704 AMBA_DEVICE(gpio0
, "dev:e4", GPIO0
, NULL
);
705 AMBA_DEVICE(gpio1
, "dev:e5", GPIO1
, NULL
);
706 AMBA_DEVICE(rtc
, "dev:e8", RTC
, NULL
);
707 AMBA_DEVICE(sci0
, "dev:f0", SCI
, NULL
);
708 AMBA_DEVICE(uart0
, "dev:f1", UART0
, NULL
);
709 AMBA_DEVICE(uart1
, "dev:f2", UART1
, NULL
);
710 AMBA_DEVICE(uart2
, "dev:f3", UART2
, NULL
);
711 AMBA_DEVICE(ssp0
, "dev:f4", SSP
, NULL
);
713 static struct amba_device
*amba_devs
[] __initdata
= {
735 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
737 static void versatile_leds_event(led_event_t ledevt
)
742 local_irq_save(flags
);
743 val
= readl(VA_LEDS_BASE
);
747 val
= val
& ~VERSATILE_SYS_LED0
;
751 val
= val
| VERSATILE_SYS_LED0
;
755 val
= val
^ VERSATILE_SYS_LED1
;
766 writel(val
, VA_LEDS_BASE
);
767 local_irq_restore(flags
);
769 #endif /* CONFIG_LEDS */
771 void __init
versatile_init(void)
775 clk_register(&versatile_clcd_clk
);
777 platform_device_register(&versatile_flash_device
);
778 platform_device_register(&smc91x_device
);
780 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
781 struct amba_device
*d
= amba_devs
[i
];
782 amba_device_register(d
, &iomem_resource
);
786 leds_event
= versatile_leds_event
;
791 * Where is the timer (VA)?
793 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
794 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
795 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
796 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
797 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
800 * How long is the timer interval?
802 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
803 #if TIMER_INTERVAL >= 0x100000
804 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
805 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
806 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
807 #elif TIMER_INTERVAL >= 0x10000
808 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
809 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
810 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
812 #define TIMER_RELOAD (TIMER_INTERVAL)
813 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
814 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
818 * Returns number of ms since last clock interrupt. Note that interrupts
819 * will have been disabled by do_gettimeoffset()
821 static unsigned long versatile_gettimeoffset(void)
823 unsigned long ticks1
, ticks2
, status
;
826 * Get the current number of ticks. Note that there is a race
827 * condition between us reading the timer and checking for
828 * an interrupt. We get around this by ensuring that the
829 * counter has not reloaded between our two reads.
831 ticks2
= readl(TIMER0_VA_BASE
+ TIMER_VALUE
) & 0xffff;
834 status
= __raw_readl(VA_IC_BASE
+ VIC_RAW_STATUS
);
835 ticks2
= readl(TIMER0_VA_BASE
+ TIMER_VALUE
) & 0xffff;
836 } while (ticks2
> ticks1
);
839 * Number of ticks since last interrupt.
841 ticks1
= TIMER_RELOAD
- ticks2
;
844 * Interrupt pending? If so, we've reloaded once already.
846 * FIXME: Need to check this is effectively timer 0 that expires
848 if (status
& IRQMASK_TIMERINT0_1
)
849 ticks1
+= TIMER_RELOAD
;
852 * Convert the ticks to usecs
854 return TICKS2USECS(ticks1
);
858 * IRQ handler for the timer
860 static irqreturn_t
versatile_timer_interrupt(int irq
, void *dev_id
)
862 write_seqlock(&xtime_lock
);
864 // ...clear the interrupt
865 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
869 write_sequnlock(&xtime_lock
);
874 static struct irqaction versatile_timer_irq
= {
875 .name
= "Versatile Timer Tick",
876 .flags
= IRQF_DISABLED
| IRQF_TIMER
,
877 .handler
= versatile_timer_interrupt
,
881 * Set up timer interrupt, and return the current time in seconds.
883 static void __init
versatile_timer_init(void)
888 * set clock frequency:
889 * VERSATILE_REFCLK is 32KHz
890 * VERSATILE_TIMCLK is 1MHz
892 val
= readl(__io_address(VERSATILE_SCTL_BASE
));
893 writel((VERSATILE_TIMCLK
<< VERSATILE_TIMER1_EnSel
) |
894 (VERSATILE_TIMCLK
<< VERSATILE_TIMER2_EnSel
) |
895 (VERSATILE_TIMCLK
<< VERSATILE_TIMER3_EnSel
) |
896 (VERSATILE_TIMCLK
<< VERSATILE_TIMER4_EnSel
) | val
,
897 __io_address(VERSATILE_SCTL_BASE
));
900 * Initialise to a known state (all timers off)
902 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
903 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
904 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
905 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
907 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
908 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_VALUE
);
909 writel(TIMER_DIVISOR
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
|
910 TIMER_CTRL_IE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
913 * Make irqs happen for the system timer
915 setup_irq(IRQ_TIMERINT0_1
, &versatile_timer_irq
);
918 struct sys_timer versatile_timer
= {
919 .init
= versatile_timer_init
,
920 .offset
= versatile_gettimeoffset
,