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[PATCH] CREDITS update
[linux-2.6/history.git] / drivers / net / e100.c
blob8855b20e3d8e31f9bd715ff0f3ff4d584a55a426
1 /*******************************************************************************
2
3
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt, or
91 * in dev->poll in the case where NAPI is enabled. cbs_avail keeps
92 * track of number of free CB resources available.
93 *
94 * Hardware padding of short packets to minimum packet size is
95 * enabled. 82557 pads with 7Eh, while the later controllers pad
96 * with 00h.
97 *
98 * IV. Recieve
99 *
100 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
101 * Descriptors (RFD) + data buffer, thus forming the simplified mode
102 * memory structure. Rx skbs are allocated to contain both the RFD
103 * and the data buffer, but the RFD is pulled off before the skb is
104 * indicated. The data buffer is aligned such that encapsulated
105 * protocol headers are u32-aligned. Since the RFD is part of the
106 * mapped shared memory, and completion status is contained within
107 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
108 * view from software and hardware.
109 *
110 * Under typical operation, the receive unit (RU) is start once,
111 * and the controller happily fills RFDs as frames arrive. If
112 * replacement RFDs cannot be allocated, or the RU goes non-active,
113 * the RU must be restarted. Frame arrival generates an interrupt,
114 * and Rx indication and re-allocation happen in the same context,
115 * therefore no locking is required. If NAPI is enabled, this work
116 * happens in dev->poll. A software-generated interrupt is gen-
117 * erated from the watchdog to recover from a failed allocation
118 * senario where all Rx resources have been indicated and none re-
119 * placed.
120 *
121 * V. Miscellaneous
122 *
123 * VLAN offloading of tagging, stripping and filtering is not
124 * supported, but driver will accommodate the extra 4-byte VLAN tag
125 * for processing by upper layers. Tx/Rx Checksum offloading is not
126 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
127 * not supported (hardware limitation).
128 *
129 * NAPI support is enabled with CONFIG_E100_NAPI.
130 *
131 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
132 *
133 * Thanks to JC (jchapman@katalix.com) for helping with
134 * testing/troubleshooting the development driver.
135 *
136 * TODO:
137 * o several entry points race with dev->close
138 * o check for tx-no-resources/stop Q races with tx clean/wake Q
139 */
140
141 #include <linux/config.h>
142 #include <linux/module.h>
143 #include <linux/moduleparam.h>
144 #include <linux/kernel.h>
145 #include <linux/types.h>
146 #include <linux/slab.h>
147 #include <linux/delay.h>
148 #include <linux/init.h>
149 #include <linux/pci.h>
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/mii.h>
153 #include <linux/if_vlan.h>
154 #include <linux/skbuff.h>
155 #include <linux/ethtool.h>
156 #include <linux/string.h>
157 #include <asm/unaligned.h>
158
159
160 #define DRV_NAME "e100"
161 #define DRV_VERSION "3.0.18"
162 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
163 #define DRV_COPYRIGHT "Copyright(c) 1999-2004 Intel Corporation"
164 #define PFX DRV_NAME ": "
165
166 #define E100_WATCHDOG_PERIOD (2 * HZ)
167 #define E100_NAPI_WEIGHT 16
168
169 MODULE_DESCRIPTION(DRV_DESCRIPTION);
170 MODULE_AUTHOR(DRV_COPYRIGHT);
171 MODULE_LICENSE("GPL");
172
173 static int debug = 3;
174 module_param(debug, int, 0);
175 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
176 #define DPRINTK(nlevel, klevel, fmt, args...) \
177 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
178 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
179 __FUNCTION__ , ## args))
180
181 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
182 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
183 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
184 static struct pci_device_id e100_id_table[] = {
185 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
187 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
192 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
198 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
205 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
206 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
213 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
214 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
215 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
216 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
217 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
218 { 0, }
219 };
220 MODULE_DEVICE_TABLE(pci, e100_id_table);
221
222 enum mac {
223 mac_82557_D100_A = 0,
224 mac_82557_D100_B = 1,
225 mac_82557_D100_C = 2,
226 mac_82558_D101_A4 = 4,
227 mac_82558_D101_B0 = 5,
228 mac_82559_D101M = 8,
229 mac_82559_D101S = 9,
230 mac_82550_D102 = 12,
231 mac_82550_D102_C = 13,
232 mac_82551_E = 14,
233 mac_82551_F = 15,
234 mac_82551_10 = 16,
235 mac_unknown = 0xFF,
236 };
237
238 enum phy {
239 phy_100a = 0x000003E0,
240 phy_100c = 0x035002A8,
241 phy_82555_tx = 0x015002A8,
242 phy_nsc_tx = 0x5C002000,
243 phy_82562_et = 0x033002A8,
244 phy_82562_em = 0x032002A8,
245 phy_82562_eh = 0x017002A8,
246 phy_unknown = 0xFFFFFFFF,
247 };
248
249 /* CSR (Control/Status Registers) */
250 struct csr {
251 struct {
252 u8 status;
253 u8 stat_ack;
254 u8 cmd_lo;
255 u8 cmd_hi;
256 u32 gen_ptr;
257 } scb;
258 u32 port;
259 u16 flash_ctrl;
260 u8 eeprom_ctrl_lo;
261 u8 eeprom_ctrl_hi;
262 u32 mdi_ctrl;
263 u32 rx_dma_count;
264 };
265
266 enum scb_status {
267 rus_ready = 0x10,
268 rus_mask = 0x3C,
269 };
270
271 enum scb_stat_ack {
272 stat_ack_not_ours = 0x00,
273 stat_ack_sw_gen = 0x04,
274 stat_ack_rnr = 0x10,
275 stat_ack_cu_idle = 0x20,
276 stat_ack_frame_rx = 0x40,
277 stat_ack_cu_cmd_done = 0x80,
278 stat_ack_not_present = 0xFF,
279 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
280 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
281 };
282
283 enum scb_cmd_hi {
284 irq_mask_none = 0x00,
285 irq_mask_all = 0x01,
286 irq_sw_gen = 0x02,
287 };
288
289 enum scb_cmd_lo {
290 cuc_nop = 0x00,
291 ruc_start = 0x01,
292 ruc_load_base = 0x06,
293 cuc_start = 0x10,
294 cuc_resume = 0x20,
295 cuc_dump_addr = 0x40,
296 cuc_dump_stats = 0x50,
297 cuc_load_base = 0x60,
298 cuc_dump_reset = 0x70,
299 };
300
301 enum cuc_dump {
302 cuc_dump_complete = 0x0000A005,
303 cuc_dump_reset_complete = 0x0000A007,
304 };
305
306 enum port {
307 software_reset = 0x0000,
308 selftest = 0x0001,
309 selective_reset = 0x0002,
310 };
311
312 enum eeprom_ctrl_lo {
313 eesk = 0x01,
314 eecs = 0x02,
315 eedi = 0x04,
316 eedo = 0x08,
317 };
318
319 enum mdi_ctrl {
320 mdi_write = 0x04000000,
321 mdi_read = 0x08000000,
322 mdi_ready = 0x10000000,
323 };
324
325 enum eeprom_op {
326 op_write = 0x05,
327 op_read = 0x06,
328 op_ewds = 0x10,
329 op_ewen = 0x13,
330 };
331
332 enum eeprom_offsets {
333 eeprom_id = 0x0A,
334 eeprom_config_asf = 0x0D,
335 eeprom_smbus_addr = 0x90,
336 };
337
338 enum eeprom_id {
339 eeprom_id_wol = 0x0020,
340 };
341
342 enum eeprom_config_asf {
343 eeprom_asf = 0x8000,
344 eeprom_gcl = 0x4000,
345 };
346
347 enum cb_status {
348 cb_complete = 0x8000,
349 cb_ok = 0x2000,
350 };
351
352 enum cb_command {
353 cb_iaaddr = 0x0001,
354 cb_config = 0x0002,
355 cb_multi = 0x0003,
356 cb_tx = 0x0004,
357 cb_dump = 0x0006,
358 cb_tx_sf = 0x0008,
359 cb_cid = 0x1f00,
360 cb_i = 0x2000,
361 cb_s = 0x4000,
362 cb_el = 0x8000,
363 };
364
365 struct rfd {
366 u16 status;
367 u16 command;
368 u32 link;
369 u32 rbd;
370 u16 actual_size;
371 u16 size;
372 };
373
374 struct rx {
375 struct rx *next, *prev;
376 struct sk_buff *skb;
377 dma_addr_t dma_addr;
378 };
379
380 #if defined(__BIG_ENDIAN_BITFIELD)
381 #define X(a,b) b,a
382 #else
383 #define X(a,b) a,b
384 #endif
385 struct config {
386 /*0*/ u8 X(byte_count:6, pad0:2);
387 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
388 /*2*/ u8 adaptive_ifs;
389 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
390 term_write_cache_line:1), pad3:4);
391 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
392 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
393 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
394 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
395 rx_discard_overruns:1), rx_save_bad_frames:1);
396 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
397 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
398 tx_dynamic_tbd:1);
399 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
400 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
401 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
402 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
403 loopback:2);
404 /*11*/ u8 X(linear_priority:3, pad11:5);
405 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
406 /*13*/ u8 ip_addr_lo;
407 /*14*/ u8 ip_addr_hi;
408 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
409 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
410 pad15_2:1), crs_or_cdt:1);
411 /*16*/ u8 fc_delay_lo;
412 /*17*/ u8 fc_delay_hi;
413 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
414 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
415 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
416 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
417 full_duplex_force:1), full_duplex_pin:1);
418 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
419 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
420 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
421 u8 pad_d102[9];
422 };
423
424 #define E100_MAX_MULTICAST_ADDRS 64
425 struct multi {
426 u16 count;
427 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
428 };
429
430 /* Important: keep total struct u32-aligned */
431 struct cb {
432 u16 status;
433 u16 command;
434 u32 link;
435 union {
436 u8 iaaddr[ETH_ALEN];
437 struct config config;
438 struct multi multi;
439 struct {
440 u32 tbd_array;
441 u16 tcb_byte_count;
442 u8 threshold;
443 u8 tbd_count;
444 struct {
445 u32 buf_addr;
446 u16 size;
447 u16 eol;
448 } tbd;
449 } tcb;
450 u32 dump_buffer_addr;
451 } u;
452 struct cb *next, *prev;
453 dma_addr_t dma_addr;
454 struct sk_buff *skb;
455 };
456
457 enum loopback {
458 lb_none = 0, lb_mac = 1, lb_phy = 3,
459 };
460
461 struct stats {
462 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
463 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
464 tx_multiple_collisions, tx_total_collisions;
465 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
466 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
467 rx_short_frame_errors;
468 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
469 u16 xmt_tco_frames, rcv_tco_frames;
470 u32 complete;
471 };
472
473 struct mem {
474 struct {
475 u32 signature;
476 u32 result;
477 } selftest;
478 struct stats stats;
479 u8 dump_buf[596];
480 };
481
482 struct param_range {
483 u32 min;
484 u32 max;
485 u32 count;
486 };
487
488 struct params {
489 struct param_range rfds;
490 struct param_range cbs;
491 };
492
493 struct nic {
494 /* Begin: frequently used values: keep adjacent for cache effect */
495 u32 msg_enable ____cacheline_aligned;
496 struct net_device *netdev;
497 struct pci_dev *pdev;
498
499 struct rx *rxs ____cacheline_aligned;
500 struct rx *rx_to_use;
501 struct rx *rx_to_clean;
502 struct rfd blank_rfd;
503 int ru_running;
504
505 spinlock_t cb_lock ____cacheline_aligned;
506 spinlock_t cmd_lock;
507 struct csr *csr;
508 enum scb_cmd_lo cuc_cmd;
509 unsigned int cbs_avail;
510 struct cb *cbs;
511 struct cb *cb_to_use;
512 struct cb *cb_to_send;
513 struct cb *cb_to_clean;
514 u16 tx_command;
515 /* End: frequently used values: keep adjacent for cache effect */
516
517 enum {
518 ich = (1 << 0),
519 promiscuous = (1 << 1),
520 multicast_all = (1 << 2),
521 wol_magic = (1 << 3),
522 ich_10h_workaround = (1 << 4),
523 } flags ____cacheline_aligned;
524
525 enum mac mac;
526 enum phy phy;
527 struct params params;
528 struct net_device_stats net_stats;
529 struct timer_list watchdog;
530 struct timer_list blink_timer;
531 struct mii_if_info mii;
532 enum loopback loopback;
533
534 struct mem *mem;
535 dma_addr_t dma_addr;
536
537 dma_addr_t cbs_dma_addr;
538 u8 adaptive_ifs;
539 u8 tx_threshold;
540 u32 tx_frames;
541 u32 tx_collisions;
542 u32 tx_deferred;
543 u32 tx_single_collisions;
544 u32 tx_multiple_collisions;
545 u32 tx_fc_pause;
546 u32 tx_tco_frames;
547
548 u32 rx_fc_pause;
549 u32 rx_fc_unsupported;
550 u32 rx_tco_frames;
551
552 u8 rev_id;
553 u16 leds;
554 u16 eeprom_wc;
555 u16 eeprom[256];
556 u32 pm_state[16];
557 };
558
559 static inline void e100_write_flush(struct nic *nic)
560 {
561 /* Flush previous PCI writes through intermediate bridges
562 * by doing a benign read */
563 (void)readb(&nic->csr->scb.status);
564 }
565
566 static inline void e100_enable_irq(struct nic *nic)
567 {
568 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
569 e100_write_flush(nic);
570 }
571
572 static inline void e100_disable_irq(struct nic *nic)
573 {
574 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
575 e100_write_flush(nic);
576 }
577
578 static void e100_hw_reset(struct nic *nic)
579 {
580 /* Put CU and RU into idle with a selective reset to get
581 * device off of PCI bus */
582 writel(selective_reset, &nic->csr->port);
583 e100_write_flush(nic); udelay(20);
584
585 /* Now fully reset device */
586 writel(software_reset, &nic->csr->port);
587 e100_write_flush(nic); udelay(20);
588
589 /* TCO workaround - 82559 and greater */
590 if(nic->mac >= mac_82559_D101M) {
591 /* Issue a redundant CU load base without setting
592 * general pointer, and without waiting for scb to
593 * clear. This gets us into post-driver. Finally,
594 * wait 20 msec for reset to take effect. */
595 writeb(cuc_load_base, &nic->csr->scb.cmd_lo);
596 mdelay(20);
597 }
598
599 /* Mask off our interrupt line - it's unmasked after reset */
600 e100_disable_irq(nic);
601 }
602
603 static int e100_self_test(struct nic *nic)
604 {
605 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
606
607 /* Passing the self-test is a pretty good indication
608 * that the device can DMA to/from host memory */
609
610 nic->mem->selftest.signature = 0;
611 nic->mem->selftest.result = 0xFFFFFFFF;
612
613 writel(selftest | dma_addr, &nic->csr->port);
614 e100_write_flush(nic);
615 /* Wait 10 msec for self-test to complete */
616 set_current_state(TASK_UNINTERRUPTIBLE);
617 schedule_timeout(HZ / 100 + 1);
618
619 /* Interrupts are enabled after self-test */
620 e100_disable_irq(nic);
621
622 /* Check results of self-test */
623 if(nic->mem->selftest.result != 0) {
624 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
625 nic->mem->selftest.result);
626 return -ETIMEDOUT;
627 }
628 if(nic->mem->selftest.signature == 0) {
629 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
630 return -ETIMEDOUT;
631 }
632
633 return 0;
634 }
635
636 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
637 {
638 u32 cmd_addr_data[3];
639 u8 ctrl;
640 int i, j;
641
642 /* Three cmds: write/erase enable, write data, write/erase disable */
643 cmd_addr_data[0] = op_ewen << (addr_len - 2);
644 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
645 cpu_to_le16(data);
646 cmd_addr_data[2] = op_ewds << (addr_len - 2);
647
648 /* Bit-bang cmds to write word to eeprom */
649 for(j = 0; j < 3; j++) {
650
651 /* Chip select */
652 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
653 e100_write_flush(nic); udelay(4);
654
655 for(i = 31; i >= 0; i--) {
656 ctrl = (cmd_addr_data[j] & (1 << i)) ?
657 eecs | eedi : eecs;
658 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
659 e100_write_flush(nic); udelay(4);
660
661 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
662 e100_write_flush(nic); udelay(4);
663 }
664 /* Wait 10 msec for cmd to complete */
665 set_current_state(TASK_UNINTERRUPTIBLE);
666 schedule_timeout(HZ / 100 + 1);
667
668 /* Chip deselect */
669 writeb(0, &nic->csr->eeprom_ctrl_lo);
670 e100_write_flush(nic); udelay(4);
671 }
672 };
673
674 /* General technique stolen from the eepro100 driver - very clever */
675 static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
676 {
677 u32 cmd_addr_data;
678 u16 data = 0;
679 u8 ctrl;
680 int i;
681
682 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
683
684 /* Chip select */
685 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
686 e100_write_flush(nic); udelay(4);
687
688 /* Bit-bang to read word from eeprom */
689 for(i = 31; i >= 0; i--) {
690 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
691 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
692 e100_write_flush(nic); udelay(4);
693
694 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
695 e100_write_flush(nic); udelay(4);
696
697 /* Eeprom drives a dummy zero to EEDO after receiving
698 * complete address. Use this to adjust addr_len. */
699 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
700 if(!(ctrl & eedo) && i > 16) {
701 *addr_len -= (i - 16);
702 i = 17;
703 }
704
705 data = (data << 1) | (ctrl & eedo ? 1 : 0);
706 }
707
708 /* Chip deselect */
709 writeb(0, &nic->csr->eeprom_ctrl_lo);
710 e100_write_flush(nic); udelay(4);
711
712 return le16_to_cpu(data);
713 };
714
715 /* Load entire EEPROM image into driver cache and validate checksum */
716 static int e100_eeprom_load(struct nic *nic)
717 {
718 u16 addr, addr_len = 8, checksum = 0;
719
720 /* Try reading with an 8-bit addr len to discover actual addr len */
721 e100_eeprom_read(nic, &addr_len, 0);
722 nic->eeprom_wc = 1 << addr_len;
723
724 for(addr = 0; addr < nic->eeprom_wc; addr++) {
725 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
726 if(addr < nic->eeprom_wc - 1)
727 checksum += cpu_to_le16(nic->eeprom[addr]);
728 }
729
730 /* The checksum, stored in the last word, is calculated such that
731 * the sum of words should be 0xBABA */
732 checksum = le16_to_cpu(0xBABA - checksum);
733 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
734 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
735 return -EAGAIN;
736 }
737
738 return 0;
739 }
740
741 /* Save (portion of) driver EEPROM cache to device and update checksum */
742 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
743 {
744 u16 addr, addr_len = 8, checksum = 0;
745
746 /* Try reading with an 8-bit addr len to discover actual addr len */
747 e100_eeprom_read(nic, &addr_len, 0);
748 nic->eeprom_wc = 1 << addr_len;
749
750 if(start + count >= nic->eeprom_wc)
751 return -EINVAL;
752
753 for(addr = start; addr < start + count; addr++)
754 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
755
756 /* The checksum, stored in the last word, is calculated such that
757 * the sum of words should be 0xBABA */
758 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
759 checksum += cpu_to_le16(nic->eeprom[addr]);
760 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
761 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
762 nic->eeprom[nic->eeprom_wc - 1]);
763
764 return 0;
765 }
766
767 #define E100_WAIT_SCB_TIMEOUT 40
768 static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
769 {
770 unsigned long flags;
771 unsigned int i;
772 int err = 0;
773
774 spin_lock_irqsave(&nic->cmd_lock, flags);
775
776 /* Previous command is accepted when SCB clears */
777 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
778 if(likely(!readb(&nic->csr->scb.cmd_lo)))
779 break;
780 cpu_relax();
781 if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
782 udelay(5);
783 }
784 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
785 err = -EAGAIN;
786 goto err_unlock;
787 }
788
789 if(unlikely(cmd != cuc_resume))
790 writel(dma_addr, &nic->csr->scb.gen_ptr);
791 writeb(cmd, &nic->csr->scb.cmd_lo);
792
793 err_unlock:
794 spin_unlock_irqrestore(&nic->cmd_lock, flags);
795
796 return err;
797 }
798
799 static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
800 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
801 {
802 struct cb *cb;
803 unsigned long flags;
804 int err = 0;
805
806 spin_lock_irqsave(&nic->cb_lock, flags);
807
808 if(unlikely(!nic->cbs_avail)) {
809 err = -ENOMEM;
810 goto err_unlock;
811 }
812
813 cb = nic->cb_to_use;
814 nic->cb_to_use = cb->next;
815 nic->cbs_avail--;
816 cb->skb = skb;
817
818 if(unlikely(!nic->cbs_avail))
819 err = -ENOSPC;
820
821 cb_prepare(nic, cb, skb);
822
823 /* Order is important otherwise we'll be in a race with h/w:
824 * set S-bit in current first, then clear S-bit in previous. */
825 cb->command |= cpu_to_le16(cb_s);
826 wmb();
827 cb->prev->command &= cpu_to_le16(~cb_s);
828
829 while(nic->cb_to_send != nic->cb_to_use) {
830 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
831 nic->cb_to_send->dma_addr))) {
832 /* Ok, here's where things get sticky. It's
833 * possible that we can't schedule the command
834 * because the controller is too busy, so
835 * let's just queue the command and try again
836 * when another command is scheduled. */
837 break;
838 } else {
839 nic->cuc_cmd = cuc_resume;
840 nic->cb_to_send = nic->cb_to_send->next;
841 }
842 }
843
844 err_unlock:
845 spin_unlock_irqrestore(&nic->cb_lock, flags);
846
847 return err;
848 }
849
850 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
851 {
852 u32 data_out = 0;
853 unsigned int i;
854
855 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
856
857 for(i = 0; i < 100; i++) {
858 udelay(20);
859 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
860 break;
861 }
862
863 DPRINTK(HW, DEBUG,
864 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
865 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
866 return (u16)data_out;
867 }
868
869 static int mdio_read(struct net_device *netdev, int addr, int reg)
870 {
871 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
872 }
873
874 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
875 {
876 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
877 }
878
879 static void e100_get_defaults(struct nic *nic)
880 {
881 struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
882 struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
883
884 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
885 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
886 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
887 if(nic->mac == mac_unknown)
888 nic->mac = mac_82557_D100_A;
889
890 nic->params.rfds = rfds;
891 nic->params.cbs = cbs;
892
893 /* Quadwords to DMA into FIFO before starting frame transmit */
894 nic->tx_threshold = 0xE0;
895
896 nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
897 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));
898
899 /* Template for a freshly allocated RFD */
900 nic->blank_rfd.command = cpu_to_le16(cb_el);
901 nic->blank_rfd.rbd = 0xFFFFFFFF;
902 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
903
904 /* MII setup */
905 nic->mii.phy_id_mask = 0x1F;
906 nic->mii.reg_num_mask = 0x1F;
907 nic->mii.dev = nic->netdev;
908 nic->mii.mdio_read = mdio_read;
909 nic->mii.mdio_write = mdio_write;
910 }
911
912 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
913 {
914 struct config *config = &cb->u.config;
915 u8 *c = (u8 *)config;
916
917 cb->command = cpu_to_le16(cb_config);
918
919 memset(config, 0, sizeof(struct config));
920
921 config->byte_count = 0x16; /* bytes in this struct */
922 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
923 config->direct_rx_dma = 0x1; /* reserved */
924 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
925 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
926 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
927 config->tx_underrun_retry = 0x3; /* # of underrun retries */
928 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
929 config->pad10 = 0x6;
930 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
931 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
932 config->ifs = 0x6; /* x16 = inter frame spacing */
933 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
934 config->pad15_1 = 0x1;
935 config->pad15_2 = 0x1;
936 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
937 config->fc_delay_hi = 0x40; /* time delay for fc frame */
938 config->tx_padding = 0x1; /* 1=pad short frames */
939 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
940 config->pad18 = 0x1;
941 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
942 config->pad20_1 = 0x1F;
943 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
944 config->pad21_1 = 0x5;
945
946 config->adaptive_ifs = nic->adaptive_ifs;
947 config->loopback = nic->loopback;
948
949 if(nic->mii.force_media && nic->mii.full_duplex)
950 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
951
952 if(nic->flags & promiscuous || nic->loopback) {
953 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
954 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
955 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
956 }
957
958 if(nic->flags & multicast_all)
959 config->multicast_all = 0x1; /* 1=accept, 0=no */
960
961 if(!(nic->flags & wol_magic))
962 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
963
964 if(nic->mac >= mac_82558_D101_A4) {
965 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
966 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
967 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
968 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
969 if(nic->mac >= mac_82559_D101M)
970 config->tno_intr = 0x1; /* TCO stats enable */
971 else
972 config->standard_stat_counter = 0x0;
973 }
974
975 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
976 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
977 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
978 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
979 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
980 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
981 }
982
983 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
984 struct sk_buff *skb)
985 {
986 cb->command = cpu_to_le16(cb_iaaddr);
987 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
988 }
989
990 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
991 {
992 cb->command = cpu_to_le16(cb_dump);
993 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
994 offsetof(struct mem, dump_buf));
995 }
996
997 #define NCONFIG_AUTO_SWITCH 0x0080
998 #define MII_NSC_CONG MII_RESV1
999 #define NSC_CONG_ENABLE 0x0100
1000 #define NSC_CONG_TXREADY 0x0400
1001 #define ADVERTISE_FC_SUPPORTED 0x0400
1002 static int e100_phy_init(struct nic *nic)
1003 {
1004 struct net_device *netdev = nic->netdev;
1005 u32 addr;
1006 u16 bmcr, stat, id_lo, id_hi, cong;
1007
1008 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1009 for(addr = 0; addr < 32; addr++) {
1010 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1011 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1012 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1013 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1014 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1015 break;
1016 }
1017 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1018 if(addr == 32)
1019 return -EAGAIN;
1020
1021 /* Selected the phy and isolate the rest */
1022 for(addr = 0; addr < 32; addr++) {
1023 if(addr != nic->mii.phy_id) {
1024 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1025 } else {
1026 bmcr = mdio_read(netdev, addr, MII_BMCR);
1027 mdio_write(netdev, addr, MII_BMCR,
1028 bmcr & ~BMCR_ISOLATE);
1029 }
1030 }
1031
1032 /* Get phy ID */
1033 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1034 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1035 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1036 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1037
1038 /* Handle National tx phys */
1039 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1040 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1041 /* Disable congestion control */
1042 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1043 cong |= NSC_CONG_TXREADY;
1044 cong &= ~NSC_CONG_ENABLE;
1045 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1046 }
1047
1048 if(nic->mac >= mac_82550_D102)
1049 /* enable/disable MDI/MDI-X auto-switching */
1050 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1051 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1052
1053 return 0;
1054 }
1055
1056 static int e100_hw_init(struct nic *nic)
1057 {
1058 int err;
1059
1060 e100_hw_reset(nic);
1061
1062 DPRINTK(HW, ERR, "e100_hw_init\n");
1063 if(!in_interrupt() && (err = e100_self_test(nic)))
1064 return err;
1065
1066 if((err = e100_phy_init(nic)))
1067 return err;
1068 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1069 return err;
1070 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1071 return err;
1072 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1073 return err;
1074 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1075 return err;
1076 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1077 nic->dma_addr + offsetof(struct mem, stats))))
1078 return err;
1079 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1080 return err;
1081
1082 e100_disable_irq(nic);
1083
1084 return 0;
1085 }
1086
1087 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1088 {
1089 struct net_device *netdev = nic->netdev;
1090 struct dev_mc_list *list = netdev->mc_list;
1091 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1092
1093 cb->command = cpu_to_le16(cb_multi);
1094 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1095 for(i = 0; list && i < count; i++, list = list->next)
1096 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1097 ETH_ALEN);
1098 }
1099
1100 static void e100_set_multicast_list(struct net_device *netdev)
1101 {
1102 struct nic *nic = netdev_priv(netdev);
1103
1104 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1105 netdev->mc_count, netdev->flags);
1106
1107 if(netdev->flags & IFF_PROMISC)
1108 nic->flags |= promiscuous;
1109 else
1110 nic->flags &= ~promiscuous;
1111
1112 if(netdev->flags & IFF_ALLMULTI ||
1113 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1114 nic->flags |= multicast_all;
1115 else
1116 nic->flags &= ~multicast_all;
1117
1118 e100_exec_cb(nic, NULL, e100_configure);
1119 e100_exec_cb(nic, NULL, e100_multi);
1120 }
1121
1122 static void e100_update_stats(struct nic *nic)
1123 {
1124 struct net_device_stats *ns = &nic->net_stats;
1125 struct stats *s = &nic->mem->stats;
1126 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1127 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1128 &s->complete;
1129
1130 /* Device's stats reporting may take several microseconds to
1131 * complete, so where always waiting for results of the
1132 * previous command. */
1133
1134 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1135 *complete = 0;
1136 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1137 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1138 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1139 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1140 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1141 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1142 ns->collisions += nic->tx_collisions;
1143 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1144 le32_to_cpu(s->tx_lost_crs);
1145 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1146 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors);
1147 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1148 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1149 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1150 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1151 le32_to_cpu(s->rx_alignment_errors) +
1152 le32_to_cpu(s->rx_short_frame_errors) +
1153 le32_to_cpu(s->rx_cdt_errors);
1154 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1155 nic->tx_single_collisions +=
1156 le32_to_cpu(s->tx_single_collisions);
1157 nic->tx_multiple_collisions +=
1158 le32_to_cpu(s->tx_multiple_collisions);
1159 if(nic->mac >= mac_82558_D101_A4) {
1160 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1161 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1162 nic->rx_fc_unsupported +=
1163 le32_to_cpu(s->fc_rcv_unsupported);
1164 if(nic->mac >= mac_82559_D101M) {
1165 nic->tx_tco_frames +=
1166 le16_to_cpu(s->xmt_tco_frames);
1167 nic->rx_tco_frames +=
1168 le16_to_cpu(s->rcv_tco_frames);
1169 }
1170 }
1171 }
1172
1173 e100_exec_cmd(nic, cuc_dump_reset, 0);
1174 }
1175
1176 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1177 {
1178 /* Adjust inter-frame-spacing (IFS) between two transmits if
1179 * we're getting collisions on a half-duplex connection. */
1180
1181 if(duplex == DUPLEX_HALF) {
1182 u32 prev = nic->adaptive_ifs;
1183 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1184
1185 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1186 (nic->tx_frames > min_frames)) {
1187 if(nic->adaptive_ifs < 60)
1188 nic->adaptive_ifs += 5;
1189 } else if (nic->tx_frames < min_frames) {
1190 if(nic->adaptive_ifs >= 5)
1191 nic->adaptive_ifs -= 5;
1192 }
1193 if(nic->adaptive_ifs != prev)
1194 e100_exec_cb(nic, NULL, e100_configure);
1195 }
1196 }
1197
1198 static void e100_watchdog(unsigned long data)
1199 {
1200 struct nic *nic = (struct nic *)data;
1201 struct ethtool_cmd cmd;
1202
1203 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1204
1205 /* mii library handles link maintenance tasks */
1206
1207 mii_ethtool_gset(&nic->mii, &cmd);
1208
1209 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1210 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1211 cmd.speed == SPEED_100 ? "100" : "10",
1212 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1213 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1214 DPRINTK(LINK, INFO, "link down\n");
1215 }
1216
1217 mii_check_link(&nic->mii);
1218
1219 /* Software generated interrupt to recover from (rare) Rx
1220 * allocation failure */
1221 writeb(irq_sw_gen, &nic->csr->scb.cmd_hi);
1222 e100_write_flush(nic);
1223
1224 e100_update_stats(nic);
1225 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1226
1227 if(nic->mac <= mac_82557_D100_C)
1228 /* Issue a multicast command to workaround a 557 lock up */
1229 e100_set_multicast_list(nic->netdev);
1230
1231 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1232 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1233 nic->flags |= ich_10h_workaround;
1234 else
1235 nic->flags &= ~ich_10h_workaround;
1236
1237 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1238 }
1239
1240 static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1241 struct sk_buff *skb)
1242 {
1243 cb->command = nic->tx_command;
1244 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1245 cb->u.tcb.tcb_byte_count = 0;
1246 cb->u.tcb.threshold = nic->tx_threshold;
1247 cb->u.tcb.tbd_count = 1;
1248 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1249 skb->data, skb->len, PCI_DMA_TODEVICE));
1250 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1251 }
1252
1253 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1254 {
1255 struct nic *nic = netdev_priv(netdev);
1256 int err;
1257
1258 if(nic->flags & ich_10h_workaround) {
1259 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1260 Issue a NOP command followed by a 1us delay before
1261 issuing the Tx command. */
1262 e100_exec_cmd(nic, cuc_nop, 0);
1263 udelay(1);
1264 }
1265
1266 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1267
1268 switch(err) {
1269 case -ENOSPC:
1270 /* We queued the skb, but now we're out of space. */
1271 netif_stop_queue(netdev);
1272 break;
1273 case -ENOMEM:
1274 /* This is a hard error - log it. */
1275 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1276 netif_stop_queue(netdev);
1277 return 1;
1278 }
1279
1280 netdev->trans_start = jiffies;
1281 return 0;
1282 }
1283
1284 static inline int e100_tx_clean(struct nic *nic)
1285 {
1286 struct cb *cb;
1287 int tx_cleaned = 0;
1288
1289 spin_lock(&nic->cb_lock);
1290
1291 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1292 nic->cb_to_clean->status);
1293
1294 /* Clean CBs marked complete */
1295 for(cb = nic->cb_to_clean;
1296 cb->status & cpu_to_le16(cb_complete);
1297 cb = nic->cb_to_clean = cb->next) {
1298 if(likely(cb->skb != NULL)) {
1299 nic->net_stats.tx_packets++;
1300 nic->net_stats.tx_bytes += cb->skb->len;
1301
1302 pci_unmap_single(nic->pdev,
1303 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1304 le16_to_cpu(cb->u.tcb.tbd.size),
1305 PCI_DMA_TODEVICE);
1306 dev_kfree_skb_any(cb->skb);
1307 cb->skb = NULL;
1308 tx_cleaned = 1;
1309 }
1310 cb->status = 0;
1311 nic->cbs_avail++;
1312 }
1313
1314 spin_unlock(&nic->cb_lock);
1315
1316 /* Recover from running out of Tx resources in xmit_frame */
1317 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1318 netif_wake_queue(nic->netdev);
1319
1320 return tx_cleaned;
1321 }
1322
1323 static void e100_clean_cbs(struct nic *nic)
1324 {
1325 if(nic->cbs) {
1326 while(nic->cbs_avail != nic->params.cbs.count) {
1327 struct cb *cb = nic->cb_to_clean;
1328 if(cb->skb) {
1329 pci_unmap_single(nic->pdev,
1330 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1331 le16_to_cpu(cb->u.tcb.tbd.size),
1332 PCI_DMA_TODEVICE);
1333 dev_kfree_skb(cb->skb);
1334 }
1335 nic->cb_to_clean = nic->cb_to_clean->next;
1336 nic->cbs_avail++;
1337 }
1338 pci_free_consistent(nic->pdev,
1339 sizeof(struct cb) * nic->params.cbs.count,
1340 nic->cbs, nic->cbs_dma_addr);
1341 nic->cbs = NULL;
1342 nic->cbs_avail = 0;
1343 }
1344 nic->cuc_cmd = cuc_start;
1345 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1346 nic->cbs;
1347 }
1348
1349 static int e100_alloc_cbs(struct nic *nic)
1350 {
1351 struct cb *cb;
1352 unsigned int i, count = nic->params.cbs.count;
1353
1354 nic->cuc_cmd = cuc_start;
1355 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1356 nic->cbs_avail = 0;
1357
1358 nic->cbs = pci_alloc_consistent(nic->pdev,
1359 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1360 if(!nic->cbs)
1361 return -ENOMEM;
1362
1363 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1364 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1365 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1366
1367 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1368 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1369 ((i+1) % count) * sizeof(struct cb));
1370 cb->skb = NULL;
1371 }
1372
1373 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1374 nic->cbs_avail = count;
1375
1376 return 0;
1377 }
1378
1379 static inline void e100_start_receiver(struct nic *nic)
1380 {
1381 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1382 if(!nic->ru_running && nic->rx_to_clean->skb) {
1383 e100_exec_cmd(nic, ruc_start, nic->rx_to_clean->dma_addr);
1384 nic->ru_running = 1;
1385 }
1386 }
1387
1388 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1389 static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1390 {
1391 unsigned int rx_offset = 2; /* u32 align protocol headers */
1392
1393 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + rx_offset)))
1394 return -ENOMEM;
1395
1396 /* Align, init, and map the RFD. */
1397 rx->skb->dev = nic->netdev;
1398 skb_reserve(rx->skb, rx_offset);
1399 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1400 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1401 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1402
1403 /* Link the RFD to end of RFA by linking previous RFD to
1404 * this one, and clearing EL bit of previous. */
1405 if(rx->prev->skb) {
1406 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1407 put_unaligned(cpu_to_le32(rx->dma_addr),
1408 (u32 *)&prev_rfd->link);
1409 wmb();
1410 prev_rfd->command &= ~cpu_to_le16(cb_el);
1411 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1412 sizeof(struct rfd), PCI_DMA_TODEVICE);
1413 }
1414
1415 return 0;
1416 }
1417
1418 static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1419 unsigned int *work_done, unsigned int work_to_do)
1420 {
1421 struct sk_buff *skb = rx->skb;
1422 struct rfd *rfd = (struct rfd *)skb->data;
1423 u16 rfd_status, actual_size;
1424
1425 if(unlikely(work_done && *work_done >= work_to_do))
1426 return -EAGAIN;
1427
1428 /* Need to sync before taking a peek at cb_complete bit */
1429 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1430 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1431 rfd_status = le16_to_cpu(rfd->status);
1432
1433 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1434
1435 /* If data isn't ready, nothing to indicate */
1436 if(unlikely(!(rfd_status & cb_complete)))
1437 return -EAGAIN;
1438
1439 /* Get actual data size */
1440 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1441 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1442 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1443
1444 /* Get data */
1445 pci_unmap_single(nic->pdev, rx->dma_addr,
1446 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1447
1448 /* Pull off the RFD and put the actual data (minus eth hdr) */
1449 skb_reserve(skb, sizeof(struct rfd));
1450 skb_put(skb, actual_size);
1451 skb->protocol = eth_type_trans(skb, nic->netdev);
1452
1453 if(unlikely(!(rfd_status & cb_ok))) {
1454 /* Don't indicate if hardware indicates errors */
1455 nic->net_stats.rx_dropped++;
1456 dev_kfree_skb_any(skb);
1457 } else if(actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
1458 /* Don't indicate oversized frames */
1459 nic->net_stats.rx_over_errors++;
1460 nic->net_stats.rx_dropped++;
1461 dev_kfree_skb_any(skb);
1462 } else {
1463 nic->net_stats.rx_packets++;
1464 nic->net_stats.rx_bytes += actual_size;
1465 nic->netdev->last_rx = jiffies;
1466 #ifdef CONFIG_E100_NAPI
1467 netif_receive_skb(skb);
1468 #else
1469 netif_rx(skb);
1470 #endif
1471 if(work_done)
1472 (*work_done)++;
1473 }
1474
1475 rx->skb = NULL;
1476
1477 return 0;
1478 }
1479
1480 static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1481 unsigned int work_to_do)
1482 {
1483 struct rx *rx;
1484
1485 /* Indicate newly arrived packets */
1486 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1487 if(e100_rx_indicate(nic, rx, work_done, work_to_do))
1488 break; /* No more to clean */
1489 }
1490
1491 /* Alloc new skbs to refill list */
1492 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1493 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1494 break; /* Better luck next time (see watchdog) */
1495 }
1496
1497 e100_start_receiver(nic);
1498 }
1499
1500 static void e100_rx_clean_list(struct nic *nic)
1501 {
1502 struct rx *rx;
1503 unsigned int i, count = nic->params.rfds.count;
1504
1505 if(nic->rxs) {
1506 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1507 if(rx->skb) {
1508 pci_unmap_single(nic->pdev, rx->dma_addr,
1509 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1510 dev_kfree_skb(rx->skb);
1511 }
1512 }
1513 kfree(nic->rxs);
1514 nic->rxs = NULL;
1515 }
1516
1517 nic->rx_to_use = nic->rx_to_clean = NULL;
1518 nic->ru_running = 0;
1519 }
1520
1521 static int e100_rx_alloc_list(struct nic *nic)
1522 {
1523 struct rx *rx;
1524 unsigned int i, count = nic->params.rfds.count;
1525
1526 nic->rx_to_use = nic->rx_to_clean = NULL;
1527
1528 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1529 return -ENOMEM;
1530 memset(nic->rxs, 0, sizeof(struct rx) * count);
1531
1532 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1533 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1534 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1535 if(e100_rx_alloc_skb(nic, rx)) {
1536 e100_rx_clean_list(nic);
1537 return -ENOMEM;
1538 }
1539 }
1540
1541 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1542
1543 return 0;
1544 }
1545
1546 static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1547 {
1548 struct net_device *netdev = dev_id;
1549 struct nic *nic = netdev_priv(netdev);
1550 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1551
1552 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1553
1554 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1555 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1556 return IRQ_NONE;
1557
1558 /* Ack interrupt(s) */
1559 writeb(stat_ack, &nic->csr->scb.stat_ack);
1560
1561 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1562 if(stat_ack & stat_ack_rnr)
1563 nic->ru_running = 0;
1564
1565 #ifdef CONFIG_E100_NAPI
1566 e100_disable_irq(nic);
1567 netif_rx_schedule(netdev);
1568 #else
1569 if(stat_ack & stat_ack_rx)
1570 e100_rx_clean(nic, NULL, 0);
1571 if(stat_ack & stat_ack_tx)
1572 e100_tx_clean(nic);
1573 #endif
1574
1575 return IRQ_HANDLED;
1576 }
1577
1578 #ifdef CONFIG_E100_NAPI
1579 static int e100_poll(struct net_device *netdev, int *budget)
1580 {
1581 struct nic *nic = netdev_priv(netdev);
1582 unsigned int work_to_do = min(netdev->quota, *budget);
1583 unsigned int work_done = 0;
1584 int tx_cleaned;
1585
1586 e100_rx_clean(nic, &work_done, work_to_do);
1587 tx_cleaned = e100_tx_clean(nic);
1588
1589 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1590 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1591 netif_rx_complete(netdev);
1592 e100_enable_irq(nic);
1593 return 0;
1594 }
1595
1596 *budget -= work_done;
1597 netdev->quota -= work_done;
1598
1599 return 1;
1600 }
1601 #endif
1602
1603 #ifdef CONFIG_NET_POLL_CONTROLLER
1604 static void e100_netpoll(struct net_device *netdev)
1605 {
1606 struct nic *nic = netdev_priv(netdev);
1607 e100_disable_irq(nic);
1608 e100_intr(nic->pdev->irq, netdev, NULL);
1609 e100_enable_irq(nic);
1610 }
1611 #endif
1612
1613 static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1614 {
1615 struct nic *nic = netdev_priv(netdev);
1616 return &nic->net_stats;
1617 }
1618
1619 static int e100_set_mac_address(struct net_device *netdev, void *p)
1620 {
1621 struct nic *nic = netdev_priv(netdev);
1622 struct sockaddr *addr = p;
1623
1624 if (!is_valid_ether_addr(addr->sa_data))
1625 return -EADDRNOTAVAIL;
1626
1627 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1628 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1629
1630 return 0;
1631 }
1632
1633 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1634 {
1635 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1636 return -EINVAL;
1637 netdev->mtu = new_mtu;
1638 return 0;
1639 }
1640
1641 static int e100_asf(struct nic *nic)
1642 {
1643 /* ASF can be enabled from eeprom */
1644 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1055) &&
1645 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1646 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1647 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1648 }
1649
1650 static int e100_up(struct nic *nic)
1651 {
1652 int err;
1653
1654 if((err = e100_rx_alloc_list(nic)))
1655 return err;
1656 if((err = e100_alloc_cbs(nic)))
1657 goto err_rx_clean_list;
1658 if((err = e100_hw_init(nic)))
1659 goto err_clean_cbs;
1660 e100_set_multicast_list(nic->netdev);
1661 e100_start_receiver(nic);
1662 mod_timer(&nic->watchdog, jiffies);
1663 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1664 nic->netdev->name, nic->netdev)))
1665 goto err_no_irq;
1666 e100_enable_irq(nic);
1667 netif_wake_queue(nic->netdev);
1668 return 0;
1669
1670 err_no_irq:
1671 del_timer_sync(&nic->watchdog);
1672 err_clean_cbs:
1673 e100_clean_cbs(nic);
1674 err_rx_clean_list:
1675 e100_rx_clean_list(nic);
1676 return err;
1677 }
1678
1679 static void e100_down(struct nic *nic)
1680 {
1681 e100_hw_reset(nic);
1682 free_irq(nic->pdev->irq, nic->netdev);
1683 del_timer_sync(&nic->watchdog);
1684 netif_carrier_off(nic->netdev);
1685 netif_stop_queue(nic->netdev);
1686 e100_clean_cbs(nic);
1687 e100_rx_clean_list(nic);
1688 }
1689
1690 static void e100_tx_timeout(struct net_device *netdev)
1691 {
1692 struct nic *nic = netdev_priv(netdev);
1693
1694 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
1695 readb(&nic->csr->scb.status));
1696 e100_down(netdev_priv(netdev));
1697 e100_up(netdev_priv(netdev));
1698 }
1699
1700 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
1701 {
1702 int err;
1703 struct sk_buff *skb;
1704
1705 /* Use driver resources to perform internal MAC or PHY
1706 * loopback test. A single packet is prepared and transmitted
1707 * in loopback mode, and the test passes if the received
1708 * packet compares byte-for-byte to the transmitted packet. */
1709
1710 if((err = e100_rx_alloc_list(nic)))
1711 return err;
1712 if((err = e100_alloc_cbs(nic)))
1713 goto err_clean_rx;
1714
1715 /* ICH PHY loopback is broken so do MAC loopback instead */
1716 if(nic->flags & ich && loopback_mode == lb_phy)
1717 loopback_mode = lb_mac;
1718
1719 nic->loopback = loopback_mode;
1720 if((err = e100_hw_init(nic)))
1721 goto err_loopback_none;
1722
1723 if(loopback_mode == lb_phy)
1724 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
1725 BMCR_LOOPBACK);
1726
1727 e100_start_receiver(nic);
1728
1729 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
1730 err = -ENOMEM;
1731 goto err_loopback_none;
1732 }
1733 skb_put(skb, ETH_DATA_LEN);
1734 memset(skb->data, 0xFF, ETH_DATA_LEN);
1735 e100_xmit_frame(skb, nic->netdev);
1736
1737 set_current_state(TASK_UNINTERRUPTIBLE);
1738 schedule_timeout(HZ / 100 + 1);
1739
1740 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1741 skb->data, ETH_DATA_LEN))
1742 err = -EAGAIN;
1743
1744 err_loopback_none:
1745 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
1746 nic->loopback = lb_none;
1747 e100_hw_init(nic);
1748 e100_clean_cbs(nic);
1749 err_clean_rx:
1750 e100_rx_clean_list(nic);
1751 return err;
1752 }
1753
1754 #define MII_LED_CONTROL 0x1B
1755 static void e100_blink_led(unsigned long data)
1756 {
1757 struct nic *nic = (struct nic *)data;
1758 enum led_state {
1759 led_on = 0x01,
1760 led_off = 0x04,
1761 led_on_559 = 0x05,
1762 led_on_557 = 0x07,
1763 };
1764
1765 nic->leds = (nic->leds & led_on) ? led_off :
1766 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
1767 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
1768 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
1769 }
1770
1771 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1772 {
1773 struct nic *nic = netdev_priv(netdev);
1774 return mii_ethtool_gset(&nic->mii, cmd);
1775 }
1776
1777 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1778 {
1779 struct nic *nic = netdev_priv(netdev);
1780 int err;
1781
1782 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
1783 err = mii_ethtool_sset(&nic->mii, cmd);
1784 e100_exec_cb(nic, NULL, e100_configure);
1785
1786 return err;
1787 }
1788
1789 static void e100_get_drvinfo(struct net_device *netdev,
1790 struct ethtool_drvinfo *info)
1791 {
1792 struct nic *nic = netdev_priv(netdev);
1793 strcpy(info->driver, DRV_NAME);
1794 strcpy(info->version, DRV_VERSION);
1795 strcpy(info->fw_version, "N/A");
1796 strcpy(info->bus_info, pci_name(nic->pdev));
1797 }
1798
1799 static int e100_get_regs_len(struct net_device *netdev)
1800 {
1801 struct nic *nic = netdev_priv(netdev);
1802 #define E100_PHY_REGS 0x1C
1803 #define E100_REGS_LEN 1 + E100_PHY_REGS + \
1804 sizeof(nic->mem->dump_buf) / sizeof(u32)
1805 return E100_REGS_LEN * sizeof(u32);
1806 }
1807
1808 static void e100_get_regs(struct net_device *netdev,
1809 struct ethtool_regs *regs, void *p)
1810 {
1811 struct nic *nic = netdev_priv(netdev);
1812 u32 *buff = p;
1813 int i;
1814
1815 regs->version = (1 << 24) | nic->rev_id;
1816 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
1817 readb(&nic->csr->scb.cmd_lo) << 16 |
1818 readw(&nic->csr->scb.status);
1819 for(i = E100_PHY_REGS; i >= 0; i--)
1820 buff[1 + E100_PHY_REGS - i] =
1821 mdio_read(netdev, nic->mii.phy_id, i);
1822 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
1823 e100_exec_cb(nic, NULL, e100_dump);
1824 set_current_state(TASK_UNINTERRUPTIBLE);
1825 schedule_timeout(HZ / 100 + 1);
1826 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
1827 sizeof(nic->mem->dump_buf));
1828 }
1829
1830 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1831 {
1832 struct nic *nic = netdev_priv(netdev);
1833 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
1834 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
1835 }
1836
1837 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1838 {
1839 struct nic *nic = netdev_priv(netdev);
1840
1841 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
1842 return -EOPNOTSUPP;
1843
1844 if(wol->wolopts)
1845 nic->flags |= wol_magic;
1846 else
1847 nic->flags &= ~wol_magic;
1848
1849 pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
1850 e100_exec_cb(nic, NULL, e100_configure);
1851
1852 return 0;
1853 }
1854
1855 static u32 e100_get_msglevel(struct net_device *netdev)
1856 {
1857 struct nic *nic = netdev_priv(netdev);
1858 return nic->msg_enable;
1859 }
1860
1861 static void e100_set_msglevel(struct net_device *netdev, u32 value)
1862 {
1863 struct nic *nic = netdev_priv(netdev);
1864 nic->msg_enable = value;
1865 }
1866
1867 static int e100_nway_reset(struct net_device *netdev)
1868 {
1869 struct nic *nic = netdev_priv(netdev);
1870 return mii_nway_restart(&nic->mii);
1871 }
1872
1873 static u32 e100_get_link(struct net_device *netdev)
1874 {
1875 struct nic *nic = netdev_priv(netdev);
1876 return mii_link_ok(&nic->mii);
1877 }
1878
1879 static int e100_get_eeprom_len(struct net_device *netdev)
1880 {
1881 struct nic *nic = netdev_priv(netdev);
1882 return nic->eeprom_wc << 1;
1883 }
1884
1885 #define E100_EEPROM_MAGIC 0x1234
1886 static int e100_get_eeprom(struct net_device *netdev,
1887 struct ethtool_eeprom *eeprom, u8 *bytes)
1888 {
1889 struct nic *nic = netdev_priv(netdev);
1890
1891 eeprom->magic = E100_EEPROM_MAGIC;
1892 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
1893
1894 return 0;
1895 }
1896
1897 static int e100_set_eeprom(struct net_device *netdev,
1898 struct ethtool_eeprom *eeprom, u8 *bytes)
1899 {
1900 struct nic *nic = netdev_priv(netdev);
1901
1902 if(eeprom->magic != E100_EEPROM_MAGIC)
1903 return -EINVAL;
1904
1905 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
1906
1907 return e100_eeprom_save(nic, eeprom->offset >> 1,
1908 (eeprom->len >> 1) + 1);
1909 }
1910
1911 static void e100_get_ringparam(struct net_device *netdev,
1912 struct ethtool_ringparam *ring)
1913 {
1914 struct nic *nic = netdev_priv(netdev);
1915 struct param_range *rfds = &nic->params.rfds;
1916 struct param_range *cbs = &nic->params.cbs;
1917
1918 ring->rx_max_pending = rfds->max;
1919 ring->tx_max_pending = cbs->max;
1920 ring->rx_mini_max_pending = 0;
1921 ring->rx_jumbo_max_pending = 0;
1922 ring->rx_pending = rfds->count;
1923 ring->tx_pending = cbs->count;
1924 ring->rx_mini_pending = 0;
1925 ring->rx_jumbo_pending = 0;
1926 }
1927
1928 static int e100_set_ringparam(struct net_device *netdev,
1929 struct ethtool_ringparam *ring)
1930 {
1931 struct nic *nic = netdev_priv(netdev);
1932 struct param_range *rfds = &nic->params.rfds;
1933 struct param_range *cbs = &nic->params.cbs;
1934
1935 if(netif_running(netdev))
1936 e100_down(nic);
1937 rfds->count = max(ring->rx_pending, rfds->min);
1938 rfds->count = min(rfds->count, rfds->max);
1939 cbs->count = max(ring->tx_pending, cbs->min);
1940 cbs->count = min(cbs->count, cbs->max);
1941 if(netif_running(netdev))
1942 e100_up(nic);
1943
1944 return 0;
1945 }
1946
1947 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
1948 "Link test (on/offline)",
1949 "Eeprom test (on/offline)",
1950 "Self test (offline)",
1951 "Mac loopback (offline)",
1952 "Phy loopback (offline)",
1953 };
1954 #define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
1955
1956 static int e100_diag_test_count(struct net_device *netdev)
1957 {
1958 return E100_TEST_LEN;
1959 }
1960
1961 static void e100_diag_test(struct net_device *netdev,
1962 struct ethtool_test *test, u64 *data)
1963 {
1964 struct nic *nic = netdev_priv(netdev);
1965 int i;
1966
1967 memset(data, 0, E100_TEST_LEN * sizeof(u64));
1968 data[0] = !mii_link_ok(&nic->mii);
1969 data[1] = e100_eeprom_load(nic);
1970 if(test->flags & ETH_TEST_FL_OFFLINE) {
1971 if(netif_running(netdev))
1972 e100_down(nic);
1973 data[2] = e100_self_test(nic);
1974 data[3] = e100_loopback_test(nic, lb_mac);
1975 data[4] = e100_loopback_test(nic, lb_phy);
1976 if(netif_running(netdev))
1977 e100_up(nic);
1978 }
1979 for(i = 0; i < E100_TEST_LEN; i++)
1980 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
1981 }
1982
1983 static int e100_phys_id(struct net_device *netdev, u32 data)
1984 {
1985 struct nic *nic = netdev_priv(netdev);
1986
1987 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1988 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1989 mod_timer(&nic->blink_timer, jiffies);
1990 set_current_state(TASK_INTERRUPTIBLE);
1991 schedule_timeout(data * HZ);
1992 del_timer_sync(&nic->blink_timer);
1993 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
1994
1995 return 0;
1996 }
1997
1998 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
1999 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2000 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2001 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2002 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2003 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2004 "tx_heartbeat_errors", "tx_window_errors",
2005 /* device-specific stats */
2006 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2007 "tx_flow_control_pause", "rx_flow_control_pause",
2008 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2009 };
2010 #define E100_NET_STATS_LEN 21
2011 #define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2012
2013 static int e100_get_stats_count(struct net_device *netdev)
2014 {
2015 return E100_STATS_LEN;
2016 }
2017
2018 static void e100_get_ethtool_stats(struct net_device *netdev,
2019 struct ethtool_stats *stats, u64 *data)
2020 {
2021 struct nic *nic = netdev_priv(netdev);
2022 int i;
2023
2024 for(i = 0; i < E100_NET_STATS_LEN; i++)
2025 data[i] = ((unsigned long *)&nic->net_stats)[i];
2026
2027 data[i++] = nic->tx_deferred;
2028 data[i++] = nic->tx_single_collisions;
2029 data[i++] = nic->tx_multiple_collisions;
2030 data[i++] = nic->tx_fc_pause;
2031 data[i++] = nic->rx_fc_pause;
2032 data[i++] = nic->rx_fc_unsupported;
2033 data[i++] = nic->tx_tco_frames;
2034 data[i++] = nic->rx_tco_frames;
2035 }
2036
2037 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2038 {
2039 switch(stringset) {
2040 case ETH_SS_TEST:
2041 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2042 break;
2043 case ETH_SS_STATS:
2044 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2045 break;
2046 }
2047 }
2048
2049 static struct ethtool_ops e100_ethtool_ops = {
2050 .get_settings = e100_get_settings,
2051 .set_settings = e100_set_settings,
2052 .get_drvinfo = e100_get_drvinfo,
2053 .get_regs_len = e100_get_regs_len,
2054 .get_regs = e100_get_regs,
2055 .get_wol = e100_get_wol,
2056 .set_wol = e100_set_wol,
2057 .get_msglevel = e100_get_msglevel,
2058 .set_msglevel = e100_set_msglevel,
2059 .nway_reset = e100_nway_reset,
2060 .get_link = e100_get_link,
2061 .get_eeprom_len = e100_get_eeprom_len,
2062 .get_eeprom = e100_get_eeprom,
2063 .set_eeprom = e100_set_eeprom,
2064 .get_ringparam = e100_get_ringparam,
2065 .set_ringparam = e100_set_ringparam,
2066 .self_test_count = e100_diag_test_count,
2067 .self_test = e100_diag_test,
2068 .get_strings = e100_get_strings,
2069 .phys_id = e100_phys_id,
2070 .get_stats_count = e100_get_stats_count,
2071 .get_ethtool_stats = e100_get_ethtool_stats,
2072 };
2073
2074 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2075 {
2076 struct nic *nic = netdev_priv(netdev);
2077
2078 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2079 }
2080
2081 static int e100_alloc(struct nic *nic)
2082 {
2083 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2084 &nic->dma_addr);
2085 return nic->mem ? 0 : -ENOMEM;
2086 }
2087
2088 static void e100_free(struct nic *nic)
2089 {
2090 if(nic->mem) {
2091 pci_free_consistent(nic->pdev, sizeof(struct mem),
2092 nic->mem, nic->dma_addr);
2093 nic->mem = NULL;
2094 }
2095 }
2096
2097 static int e100_open(struct net_device *netdev)
2098 {
2099 struct nic *nic = netdev_priv(netdev);
2100 int err = 0;
2101
2102 netif_carrier_off(netdev);
2103 if((err = e100_up(nic)))
2104 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2105 return err;
2106 }
2107
2108 static int e100_close(struct net_device *netdev)
2109 {
2110 e100_down(netdev_priv(netdev));
2111 return 0;
2112 }
2113
2114 static int __devinit e100_probe(struct pci_dev *pdev,
2115 const struct pci_device_id *ent)
2116 {
2117 struct net_device *netdev;
2118 struct nic *nic;
2119 int err;
2120
2121 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2122 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2123 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2124 return -ENOMEM;
2125 }
2126
2127 netdev->open = e100_open;
2128 netdev->stop = e100_close;
2129 netdev->hard_start_xmit = e100_xmit_frame;
2130 netdev->get_stats = e100_get_stats;
2131 netdev->set_multicast_list = e100_set_multicast_list;
2132 netdev->set_mac_address = e100_set_mac_address;
2133 netdev->change_mtu = e100_change_mtu;
2134 netdev->do_ioctl = e100_do_ioctl;
2135 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2136 netdev->tx_timeout = e100_tx_timeout;
2137 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2138 #ifdef CONFIG_E100_NAPI
2139 netdev->poll = e100_poll;
2140 netdev->weight = E100_NAPI_WEIGHT;
2141 #endif
2142 #ifdef CONFIG_NET_POLL_CONTROLLER
2143 netdev->poll_controller = e100_netpoll;
2144 #endif
2145
2146 nic = netdev_priv(netdev);
2147 nic->netdev = netdev;
2148 nic->pdev = pdev;
2149 nic->msg_enable = (1 << debug) - 1;
2150 pci_set_drvdata(pdev, netdev);
2151
2152 if((err = pci_enable_device(pdev))) {
2153 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2154 goto err_out_free_dev;
2155 }
2156
2157 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2158 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2159 "base address, aborting.\n");
2160 err = -ENODEV;
2161 goto err_out_disable_pdev;
2162 }
2163
2164 if((err = pci_request_regions(pdev, DRV_NAME))) {
2165 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2166 goto err_out_disable_pdev;
2167 }
2168
2169 pci_set_master(pdev);
2170
2171 if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
2172 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2173 goto err_out_free_res;
2174 }
2175
2176 SET_MODULE_OWNER(netdev);
2177 SET_NETDEV_DEV(netdev, &pdev->dev);
2178
2179 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2180 if(!nic->csr) {
2181 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2182 err = -ENOMEM;
2183 goto err_out_free_res;
2184 }
2185
2186 if(ent->driver_data)
2187 nic->flags |= ich;
2188 else
2189 nic->flags &= ~ich;
2190
2191 spin_lock_init(&nic->cb_lock);
2192 spin_lock_init(&nic->cmd_lock);
2193
2194 init_timer(&nic->watchdog);
2195 nic->watchdog.function = e100_watchdog;
2196 nic->watchdog.data = (unsigned long)nic;
2197 init_timer(&nic->blink_timer);
2198 nic->blink_timer.function = e100_blink_led;
2199 nic->blink_timer.data = (unsigned long)nic;
2200
2201 if((err = e100_alloc(nic))) {
2202 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2203 goto err_out_iounmap;
2204 }
2205
2206 e100_get_defaults(nic);
2207 e100_hw_reset(nic);
2208 e100_phy_init(nic);
2209
2210 if((err = e100_eeprom_load(nic)))
2211 goto err_out_free;
2212
2213 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2214 if(!is_valid_ether_addr(netdev->dev_addr)) {
2215 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2216 "EEPROM, aborting.\n");
2217 err = -EAGAIN;
2218 goto err_out_free;
2219 }
2220
2221 /* Wol magic packet can be enabled from eeprom */
2222 if((nic->mac >= mac_82558_D101_A4) &&
2223 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2224 nic->flags |= wol_magic;
2225
2226 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2227
2228 if((err = register_netdev(netdev))) {
2229 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2230 goto err_out_free;
2231 }
2232
2233 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2234 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2235 pci_resource_start(pdev, 0), pdev->irq,
2236 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2237 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2238
2239 return 0;
2240
2241 err_out_free:
2242 e100_free(nic);
2243 err_out_iounmap:
2244 iounmap(nic->csr);
2245 err_out_free_res:
2246 pci_release_regions(pdev);
2247 err_out_disable_pdev:
2248 pci_disable_device(pdev);
2249 err_out_free_dev:
2250 pci_set_drvdata(pdev, NULL);
2251 free_netdev(netdev);
2252 return err;
2253 }
2254
2255 static void __devexit e100_remove(struct pci_dev *pdev)
2256 {
2257 struct net_device *netdev = pci_get_drvdata(pdev);
2258
2259 if(netdev) {
2260 struct nic *nic = netdev_priv(netdev);
2261 unregister_netdev(netdev);
2262 e100_free(nic);
2263 iounmap(nic->csr);
2264 free_netdev(netdev);
2265 pci_release_regions(pdev);
2266 pci_disable_device(pdev);
2267 pci_set_drvdata(pdev, NULL);
2268 }
2269 }
2270
2271 #ifdef CONFIG_PM
2272 static int e100_suspend(struct pci_dev *pdev, u32 state)
2273 {
2274 struct net_device *netdev = pci_get_drvdata(pdev);
2275 struct nic *nic = netdev_priv(netdev);
2276
2277 if(netif_running(netdev))
2278 e100_down(nic);
2279 e100_hw_reset(nic);
2280 netif_device_detach(netdev);
2281
2282 pci_save_state(pdev, nic->pm_state);
2283 pci_enable_wake(pdev, state, nic->flags & (wol_magic | e100_asf(nic)));
2284 pci_disable_device(pdev);
2285 pci_set_power_state(pdev, state);
2286
2287 return 0;
2288 }
2289
2290 static int e100_resume(struct pci_dev *pdev)
2291 {
2292 struct net_device *netdev = pci_get_drvdata(pdev);
2293 struct nic *nic = netdev_priv(netdev);
2294
2295 pci_set_power_state(pdev, 0);
2296 pci_restore_state(pdev, nic->pm_state);
2297 e100_hw_init(nic);
2298
2299 netif_device_attach(netdev);
2300 if(netif_running(netdev))
2301 e100_up(nic);
2302
2303 return 0;
2304 }
2305 #endif
2306
2307 static struct pci_driver e100_driver = {
2308 .name = DRV_NAME,
2309 .id_table = e100_id_table,
2310 .probe = e100_probe,
2311 .remove = __devexit_p(e100_remove),
2312 #ifdef CONFIG_PM
2313 .suspend = e100_suspend,
2314 .resume = e100_resume,
2315 #endif
2316 };
2317
2318 static int __init e100_init_module(void)
2319 {
2320 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2321 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2322 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2323 }
2324 return pci_module_init(&e100_driver);
2325 }
2326
2327 static void __exit e100_cleanup_module(void)
2328 {
2329 pci_unregister_driver(&e100_driver);
2330 }
2331
2332 module_init(e100_init_module);
2333 module_exit(e100_cleanup_module);
Historical 2.5/2.6 development