include/asm-i386/msr.h

   1 #ifndef __ASM_MSR_H
   2 #define __ASM_MSR_H
   3
   4 /*
   5  * Access to machine-specific registers (available on 586 and better only)
   6  * Note: the rd* operations modify the parameters directly (without using
   7  * pointer indirection), this allows gcc to optimize better
   8  */
   9
  10 #define rdmsr(msr,val1,val2) \
  11         __asm__ __volatile__("rdmsr" \
  12                           : "=a" (val1), "=d" (val2) \
  13                           : "c" (msr))
  14
  15 #define wrmsr(msr,val1,val2) \
  16         __asm__ __volatile__("wrmsr" \
  17                           : /* no outputs */ \
  18                           : "c" (msr), "a" (val1), "d" (val2))
  19
  20 #define rdmsrl(msr,val) do { \
  21         unsigned long l__,h__; \
  22         rdmsr (msr, l__, h__);  \
  23         val = l__;  \
  24         val |= ((u64)h__<<32);  \
  25 } while(0)
  26
  27 static inline void wrmsrl (unsigned long msr, unsigned long long val)
  28 {
  29         unsigned long lo, hi;
  30         lo = (unsigned long) val;
  31         hi = val >> 32;
  32         wrmsr (msr, lo, hi);
  33 }
  34
  35 #define rdtsc(low,high) \
  36      __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
  37
  38 #define rdtscl(low) \
  39      __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
  40
  41 #define rdtscll(val) \
  42      __asm__ __volatile__("rdtsc" : "=A" (val))
  43
  44 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
  45
  46 #define rdpmc(counter,low,high) \
  47      __asm__ __volatile__("rdpmc" \
  48                           : "=a" (low), "=d" (high) \
  49                           : "c" (counter))
  50
  51 /* symbolic names for some interesting MSRs */
  52 /* Intel defined MSRs. */
  53 #define MSR_IA32_P5_MC_ADDR             0
  54 #define MSR_IA32_P5_MC_TYPE             1
  55 #define MSR_IA32_PLATFORM_ID            0x17
  56 #define MSR_IA32_EBL_CR_POWERON         0x2a
  57
  58 #define MSR_IA32_APICBASE               0x1b
  59 #define MSR_IA32_APICBASE_BSP           (1<<8)
  60 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
  61 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
  62
  63 #define MSR_IA32_UCODE_WRITE            0x79
  64 #define MSR_IA32_UCODE_REV              0x8b
  65
  66 #define MSR_P6_PERFCTR0         0xc1
  67 #define MSR_P6_PERFCTR1         0xc2
  68
  69 #define MSR_IA32_BBL_CR_CTL             0x119
  70
  71 #define MSR_IA32_SYSENTER_CS            0x174
  72 #define MSR_IA32_SYSENTER_ESP           0x175
  73 #define MSR_IA32_SYSENTER_EIP           0x176
  74
  75 #define MSR_IA32_MCG_CAP                0x179
  76 #define MSR_IA32_MCG_STATUS             0x17a
  77 #define MSR_IA32_MCG_CTL                0x17b
  78
  79 /* P4/Xeon+ specific */
  80 #define MSR_IA32_MCG_EAX                0x180
  81 #define MSR_IA32_MCG_EBX                0x181
  82 #define MSR_IA32_MCG_ECX                0x182
  83 #define MSR_IA32_MCG_EDX                0x183
  84 #define MSR_IA32_MCG_ESI                0x184
  85 #define MSR_IA32_MCG_EDI                0x185
  86 #define MSR_IA32_MCG_EBP                0x186
  87 #define MSR_IA32_MCG_ESP                0x187
  88 #define MSR_IA32_MCG_EFLAGS             0x188
  89 #define MSR_IA32_MCG_EIP                0x189
  90 #define MSR_IA32_MCG_RESERVED           0x18A
  91
  92 #define MSR_P6_EVNTSEL0                 0x186
  93 #define MSR_P6_EVNTSEL1                 0x187
  94
  95 #define MSR_IA32_PERF_STATUS            0x198
  96 #define MSR_IA32_PERF_CTL               0x199
  97
  98 #define MSR_IA32_THERM_CONTROL          0x19a
  99 #define MSR_IA32_THERM_INTERRUPT        0x19b
 100 #define MSR_IA32_THERM_STATUS           0x19c
 101 #define MSR_IA32_MISC_ENABLE            0x1a0
 102
 103 #define MSR_IA32_DEBUGCTLMSR            0x1d9
 104 #define MSR_IA32_LASTBRANCHFROMIP       0x1db
 105 #define MSR_IA32_LASTBRANCHTOIP         0x1dc
 106 #define MSR_IA32_LASTINTFROMIP          0x1dd
 107 #define MSR_IA32_LASTINTTOIP            0x1de
 108
 109 #define MSR_IA32_MC0_CTL                0x400
 110 #define MSR_IA32_MC0_STATUS             0x401
 111 #define MSR_IA32_MC0_ADDR               0x402
 112 #define MSR_IA32_MC0_MISC               0x403
 113
 114 /* Pentium IV performance counter MSRs */
 115 #define MSR_P4_BPU_PERFCTR0             0x300
 116 #define MSR_P4_BPU_PERFCTR1             0x301
 117 #define MSR_P4_BPU_PERFCTR2             0x302
 118 #define MSR_P4_BPU_PERFCTR3             0x303
 119 #define MSR_P4_MS_PERFCTR0              0x304
 120 #define MSR_P4_MS_PERFCTR1              0x305
 121 #define MSR_P4_MS_PERFCTR2              0x306
 122 #define MSR_P4_MS_PERFCTR3              0x307
 123 #define MSR_P4_FLAME_PERFCTR0           0x308
 124 #define MSR_P4_FLAME_PERFCTR1           0x309
 125 #define MSR_P4_FLAME_PERFCTR2           0x30a
 126 #define MSR_P4_FLAME_PERFCTR3           0x30b
 127 #define MSR_P4_IQ_PERFCTR0              0x30c
 128 #define MSR_P4_IQ_PERFCTR1              0x30d
 129 #define MSR_P4_IQ_PERFCTR2              0x30e
 130 #define MSR_P4_IQ_PERFCTR3              0x30f
 131 #define MSR_P4_IQ_PERFCTR4              0x310
 132 #define MSR_P4_IQ_PERFCTR5              0x311
 133 #define MSR_P4_BPU_CCCR0                0x360
 134 #define MSR_P4_BPU_CCCR1                0x361
 135 #define MSR_P4_BPU_CCCR2                0x362
 136 #define MSR_P4_BPU_CCCR3                0x363
 137 #define MSR_P4_MS_CCCR0                 0x364
 138 #define MSR_P4_MS_CCCR1                 0x365
 139 #define MSR_P4_MS_CCCR2                 0x366
 140 #define MSR_P4_MS_CCCR3                 0x367
 141 #define MSR_P4_FLAME_CCCR0              0x368
 142 #define MSR_P4_FLAME_CCCR1              0x369
 143 #define MSR_P4_FLAME_CCCR2              0x36a
 144 #define MSR_P4_FLAME_CCCR3              0x36b
 145 #define MSR_P4_IQ_CCCR0                 0x36c
 146 #define MSR_P4_IQ_CCCR1                 0x36d
 147 #define MSR_P4_IQ_CCCR2                 0x36e
 148 #define MSR_P4_IQ_CCCR3                 0x36f
 149 #define MSR_P4_IQ_CCCR4                 0x370
 150 #define MSR_P4_IQ_CCCR5                 0x371
 151 #define MSR_P4_ALF_ESCR0                0x3ca
 152 #define MSR_P4_ALF_ESCR1                0x3cb
 153 #define MSR_P4_BPU_ESCR0                0x3b2
 154 #define MSR_P4_BPU_ESCR1                0x3b3
 155 #define MSR_P4_BSU_ESCR0                0x3a0
 156 #define MSR_P4_BSU_ESCR1                0x3a1
 157 #define MSR_P4_CRU_ESCR0                0x3b8
 158 #define MSR_P4_CRU_ESCR1                0x3b9
 159 #define MSR_P4_CRU_ESCR2                0x3cc
 160 #define MSR_P4_CRU_ESCR3                0x3cd
 161 #define MSR_P4_CRU_ESCR4                0x3e0
 162 #define MSR_P4_CRU_ESCR5                0x3e1
 163 #define MSR_P4_DAC_ESCR0                0x3a8
 164 #define MSR_P4_DAC_ESCR1                0x3a9
 165 #define MSR_P4_FIRM_ESCR0               0x3a4
 166 #define MSR_P4_FIRM_ESCR1               0x3a5
 167 #define MSR_P4_FLAME_ESCR0              0x3a6
 168 #define MSR_P4_FLAME_ESCR1              0x3a7
 169 #define MSR_P4_FSB_ESCR0                0x3a2
 170 #define MSR_P4_FSB_ESCR1                0x3a3
 171 #define MSR_P4_IQ_ESCR0                 0x3ba
 172 #define MSR_P4_IQ_ESCR1                 0x3bb
 173 #define MSR_P4_IS_ESCR0                 0x3b4
 174 #define MSR_P4_IS_ESCR1                 0x3b5
 175 #define MSR_P4_ITLB_ESCR0               0x3b6
 176 #define MSR_P4_ITLB_ESCR1               0x3b7
 177 #define MSR_P4_IX_ESCR0                 0x3c8
 178 #define MSR_P4_IX_ESCR1                 0x3c9
 179 #define MSR_P4_MOB_ESCR0                0x3aa
 180 #define MSR_P4_MOB_ESCR1                0x3ab
 181 #define MSR_P4_MS_ESCR0                 0x3c0
 182 #define MSR_P4_MS_ESCR1                 0x3c1
 183 #define MSR_P4_PMH_ESCR0                0x3ac
 184 #define MSR_P4_PMH_ESCR1                0x3ad
 185 #define MSR_P4_RAT_ESCR0                0x3bc
 186 #define MSR_P4_RAT_ESCR1                0x3bd
 187 #define MSR_P4_SAAT_ESCR0               0x3ae
 188 #define MSR_P4_SAAT_ESCR1               0x3af
 189 #define MSR_P4_SSU_ESCR0                0x3be
 190 #define MSR_P4_SSU_ESCR1                0x3bf    /* guess: not defined in manual */
 191 #define MSR_P4_TBPU_ESCR0               0x3c2
 192 #define MSR_P4_TBPU_ESCR1               0x3c3
 193 #define MSR_P4_TC_ESCR0                 0x3c4
 194 #define MSR_P4_TC_ESCR1                 0x3c5
 195 #define MSR_P4_U2L_ESCR0                0x3b0
 196 #define MSR_P4_U2L_ESCR1                0x3b1
 197
 198 /* AMD Defined MSRs */
 199 #define MSR_K6_EFER                     0xC0000080
 200 #define MSR_K6_STAR                     0xC0000081
 201 #define MSR_K6_WHCR                     0xC0000082
 202 #define MSR_K6_UWCCR                    0xC0000085
 203 #define MSR_K6_EPMR                     0xC0000086
 204 #define MSR_K6_PSOR                     0xC0000087
 205 #define MSR_K6_PFIR                     0xC0000088
 206
 207 #define MSR_K7_EVNTSEL0                 0xC0010000
 208 #define MSR_K7_EVNTSEL1                 0xC0010001
 209 #define MSR_K7_EVNTSEL2                 0xC0010002
 210 #define MSR_K7_EVNTSEL3                 0xC0010003
 211 #define MSR_K7_PERFCTR0                 0xC0010004
 212 #define MSR_K7_PERFCTR1                 0xC0010005
 213 #define MSR_K7_PERFCTR2                 0xC0010006
 214 #define MSR_K7_PERFCTR3                 0xC0010007
 215 #define MSR_K7_HWCR                     0xC0010015
 216 #define MSR_K7_CLK_CTL                  0xC001001b
 217 #define MSR_K7_FID_VID_CTL              0xC0010041
 218 #define MSR_K7_FID_VID_STATUS           0xC0010042
 219
 220 /* Centaur-Hauls/IDT defined MSRs. */
 221 #define MSR_IDT_FCR1                    0x107
 222 #define MSR_IDT_FCR2                    0x108
 223 #define MSR_IDT_FCR3                    0x109
 224 #define MSR_IDT_FCR4                    0x10a
 225
 226 #define MSR_IDT_MCR0                    0x110
 227 #define MSR_IDT_MCR1                    0x111
 228 #define MSR_IDT_MCR2                    0x112
 229 #define MSR_IDT_MCR3                    0x113
 230 #define MSR_IDT_MCR4                    0x114
 231 #define MSR_IDT_MCR5                    0x115
 232 #define MSR_IDT_MCR6                    0x116
 233 #define MSR_IDT_MCR7                    0x117
 234 #define MSR_IDT_MCR_CTRL                0x120
 235
 236 /* VIA Cyrix defined MSRs*/
 237 #define MSR_VIA_FCR                     0x1107
 238 #define MSR_VIA_LONGHAUL                0x110a
 239 #define MSR_VIA_RNG                     0x110b
 240 #define MSR_VIA_BCR2                    0x1147
 241
 242 /* Transmeta defined MSRs */
 243 #define MSR_TMTA_LONGRUN_CTRL           0x80868010
 244 #define MSR_TMTA_LONGRUN_FLAGS          0x80868011
 245 #define MSR_TMTA_LRTI_READOUT           0x80868018
 246 #define MSR_TMTA_LRTI_VOLT_MHZ          0x8086801a
 247
 248 #endif /* __ASM_MSR_H */