| commit | 270c10e00a1e557e068803a22e0556281ceb1830 | |
| author | David S. Miller <davem@davemloft.net> | |
| Sun, 28 Oct 2012 01:05:20 +0000 (27 18:05 -0700) | ||
| committer | David S. Miller <davem@davemloft.net> | |
| Sun, 28 Oct 2012 01:35:27 +0000 (27 18:35 -0700) | ||
| tree | 14df99d0a7f35110d6d72687e6e8e588edce659b | treesnapshot (tar.gz zip) |
| parent | 517ffce4e1a03aea979fe3a18a3dd1761a24fafb | commitdiff |
sparc64: Fix cpu strand yielding.
For atomic backoff, we just loop over an exponentially backed off
counter. This is extremely ineffective as it doesn't actually yield
the cpu strand so that other competing strands can use the cpu core.
In cpus previous to SPARC-T4 we have to do this in a slightly hackish
way, by doing an operation with no side effects that also happens to
mark the strand as unavailable.
The mechanism we choose for this is three reads of the %ccr
(condition-code) register into %g0 (the zero register).
SPARC-T4 has an explicit "pause" instruction, and we'll make use of
that in a subsequent commit.
Yield strands also in cpu_relax(). We really should have done this a
very long time ago.
Signed-off-by: David S. Miller <davem@davemloft.net>
For atomic backoff, we just loop over an exponentially backed off
counter. This is extremely ineffective as it doesn't actually yield
the cpu strand so that other competing strands can use the cpu core.
In cpus previous to SPARC-T4 we have to do this in a slightly hackish
way, by doing an operation with no side effects that also happens to
mark the strand as unavailable.
The mechanism we choose for this is three reads of the %ccr
(condition-code) register into %g0 (the zero register).
SPARC-T4 has an explicit "pause" instruction, and we'll make use of
that in a subsequent commit.
Yield strands also in cpu_relax(). We really should have done this a
very long time ago.
Signed-off-by: David S. Miller <davem@davemloft.net>
| arch/sparc/include/asm/backoff.h | diffblobblamehistory | |
| arch/sparc/include/asm/processor_64.h | diffblobblamehistory |