From b0f20ff9d7e347c284ea7718597c978a2969ad7b Mon Sep 17 00:00:00 2001 From: Santosh Shilimkar Date: Fri, 19 Nov 2010 23:01:05 +0530 Subject: [PATCH] omap4: l2x0: Set share override bit Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption Signed-off-by: Santosh Shilimkar Tested-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap4-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index b3cea78b5f09..2006da10f5f5 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c @@ -80,6 +80,7 @@ static int __init omap_l2_cache_init(void) aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT; } else { aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) | + (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT)); } -- 2.11.4.GIT