drm: Add the basic check for the detailed timing in EDID
commitf059d2ad69b056aeabad4460f706a3df2f77ce50
authorZhao Yakui <yakui.zhao@intel.com>
Wed, 14 Oct 2009 01:11:25 +0000 (14 09:11 +0800)
committerDave Airlie <airlied@redhat.com>
Thu, 15 Oct 2009 22:49:27 +0000 (16 08:49 +1000)
tree93d804337d7bee1f6196dd51811488d6d2d37098
parenta77f171843d466d4af0d527bcb2d314fafa8afd7
drm: Add the basic check for the detailed timing in EDID

Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
   >hsync/vsync width is zero
   >sync is beyond the blank.

So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/drm_edid.c