| commit | d54e88011d0a5fb48d9bb60fede3e83375c75841 | |
| author | Vladimir Zapolskiy <vz@mleia.com> | |
| Wed, 30 Sep 2015 23:23:37 +0000 (1 02:23 +0300) | ||
| committer | Brian Norris <computersforpeace@gmail.com> | |
| Sun, 4 Oct 2015 21:30:49 +0000 (4 22:30 +0100) | ||
| tree | 8c349483fdc14ac36a5d7967097c6aaf400f1bba | treesnapshot (tar.gz zip) |
| parent | 08d3cd5ef0633df84d119e939d8d1b56c6e4a5e7 | commitdiff |
mtd: nand: lpc32xx_slc: fix calculation of timing arcs from given values
According to LPC32xx User's Manual all values measured in clock cycles
are programmable from 1 to 16 clocks (4 bits) starting from 0 in
bitfield, the current version of calculated clock cycles is too
conservative.
Correctness of 0 bitfield value (i.e. programmed 1 clock
timing) is proven with actual NAND chip devices.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
According to LPC32xx User's Manual all values measured in clock cycles
are programmable from 1 to 16 clocks (4 bits) starting from 0 in
bitfield, the current version of calculated clock cycles is too
conservative.
Correctness of 0 bitfield value (i.e. programmed 1 clock
timing) is proven with actual NAND chip devices.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| drivers/mtd/nand/lpc32xx_slc.c | diffblobblamehistory |