| commit | c86a4b621994dbe9361185362c4be6887f04b1a4 | |
| author | Geert Uytterhoeven <geert+renesas@glider.be> | |
| Mon, 15 Feb 2016 20:38:29 +0000 (15 21:38 +0100) | ||
| committer | Simon Horman <horms+renesas@verge.net.au> | |
| Fri, 19 Feb 2016 05:52:21 +0000 (19 14:52 +0900) | ||
| tree | 55dca258775d61ba8ae37f1d1fe33306839256f6 | treesnapshot (tar.gz zip) |
| parent | 57f9156bc620ac561ed46b2316de328e6b280023 | commitdiff |
ARM: dts: r8a73a4: Add L2 cache-controller nodes
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and located in PM domain A3KM.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| arch/arm/boot/dts/r8a73a4.dtsi | diffblobblamehistory |