| commit | b609338b26f5653aa211fc7af83477e2df6e3f0b | |
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | |
| Sat, 1 Apr 2017 13:02:25 +0000 (1 15:02 +0200) | ||
| committer | Jerome Brunet <jbrunet@baylibre.com> | |
| Fri, 7 Apr 2017 15:45:30 +0000 (7 17:45 +0200) | ||
| tree | 78dda6ea81fead69b83a6f39e5899f25f03b89ee | treesnapshot (tar.gz zip) |
| parent | 88e4ac68ea9a09e105c86070ebfa01ca482ca4c2 | commitdiff |
clk: meson: mpll: use 64bit math in rate_from_params
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.
While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.
Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
On Meson8b the MPLL parent clock (fixed_pll) has a rate of 2550MHz.
Multiplying this with SDM_DEN results in a value greater than 32bits.
This is not a problem on the 64bit Meson GX SoCs, but it may result in
undefined behavior on the older 32bit Meson8b SoC.
While rate_from_params was only introduced recently to make the math
reusable from _round_rate and _recalc_rate the original bug exists much
longer.
Fixes: 1c50da4f27 ("clk: meson: add mpll support")
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
[as discussed on the ml, use DIV_ROUND_UP_ULL]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| drivers/clk/meson/clk-mpll.c | diffblobblamehistory |