| commit | 9fae82e1acda8d4a6881be63cc38521b84007ba9 | |
| author | Harini Katakam <harinik@xilinx.com> | |
| Fri, 12 Dec 2014 04:18:26 +0000 (12 09:48 +0530) | ||
| committer | Wolfram Sang <wsa@the-dreams.de> | |
| Tue, 13 Jan 2015 15:21:03 +0000 (13 16:21 +0100) | ||
| tree | 3428a6789cd91a82785a15af9d3e6ff960944820 | treesnapshot (tar.gz zip) |
| parent | 1c57499361c403f18e5423969b9aa2446bdbe622 | commitdiff |
i2c: cadence: Handle > 252 byte transfers
The I2C controller sends a NACK to the slave when transfer size register
reaches zero, irrespective of the hold bit. So, in order to handle transfers
greater than 252 bytes, the transfer size register has to be maintained at a
value >= 1. This patch implements the same.
The interrupt status is cleared at the beginning of the isr instead of
the end, to avoid missing any interrupts.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
[wsa: added braces around else branch]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
The I2C controller sends a NACK to the slave when transfer size register
reaches zero, irrespective of the hold bit. So, in order to handle transfers
greater than 252 bytes, the transfer size register has to be maintained at a
value >= 1. This patch implements the same.
The interrupt status is cleared at the beginning of the isr instead of
the end, to avoid missing any interrupts.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
[wsa: added braces around else branch]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| drivers/i2c/busses/i2c-cadence.c | diffblobblamehistory |