| commit | 94eac9e1abb9f480e4f2d436dc2fea78131f5f16 | |
| author | John Garry <john.garry@huawei.com> | |
| Mon, 25 Jan 2016 18:47:09 +0000 (26 02:47 +0800) | ||
| committer | Martin K. Petersen <martin.petersen@oracle.com> | |
| Wed, 24 Feb 2016 02:27:02 +0000 (23 21:27 -0500) | ||
| tree | 2a96b690ddfecc1c4a3eba157e3d0be893729ffd | treesnapshot (tar.gz zip) |
| parent | 45c901b848aa8fae1fede4d986fd83ed2c53f400 | commitdiff |
hisi_sas: add v2 hw init
Add code to initialise the hardware.
Support is also added to deal with the "am-max-transmissions" (amt)
limitation in hip06 controller #1. This is how many connection requests
we can send on the system bus before waiting for a response. Due to
chip bus design, controller #1 is limited to 32 amt, while, by design, a
controller supports 64. The default value for the nibbles in the
relevant registers is 0x40; these need to be programmed with 0x20.
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Add code to initialise the hardware.
Support is also added to deal with the "am-max-transmissions" (amt)
limitation in hip06 controller #1. This is how many connection requests
we can send on the system bus before waiting for a response. Due to
chip bus design, controller #1 is limited to 32 amt, while, by design, a
controller supports 64. The default value for the nibbles in the
relevant registers is 0x40; these need to be programmed with 0x20.
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
| drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | diffblobblamehistory |