| commit | 8f0767611a0ed719caf975d899d8431834ace2d8 | |
| author | Andrea Venturi <ennesimamail.av@gmail.com> | |
| Mon, 21 Mar 2016 16:10:38 +0000 (21 17:10 +0100) | ||
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | |
| Thu, 21 Apr 2016 22:29:21 +0000 (22 00:29 +0200) | ||
| tree | 5c5bf867e6b491b5c2e408ab8c9191461e96c68c | treesnapshot (tar.gz zip) |
| parent | 92a39d9043ba5ff98adb1c31491f00c7bea5466e | commitdiff |
clk: sunxi: mod1 clock should modify it's parent
add CLK_SET_RATE_PARENT to modify the rate on clk upstream
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
add CLK_SET_RATE_PARENT to modify the rate on clk upstream
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| drivers/clk/sunxi/clk-a10-mod1.c | diffblobblamehistory |