| commit | 7934d69abfa98392433c03136025b71972851733 | |
| author | Sudeep Holla <sudeep.holla@arm.com> | |
| Wed, 21 Jan 2015 12:02:30 +0000 (21 12:02 +0000) | ||
| committer | Arnd Bergmann <arnd@arndb.de> | |
| Wed, 25 Feb 2015 16:12:21 +0000 (25 17:12 +0100) | ||
| tree | ce6d049d6a585d137d15c712189855f0fe68bc6c | treesnapshot (tar.gz zip) |
| parent | c517d838eb7d07bbe9507871fab3931deccff539 | commitdiff |
arm64: Add L2 cache topology to ARM Ltd boards/models
Commit 5d425c18653731af6 ("arm64: kernel: add support for cpu cache
information") adds cacheinfo support for ARM64. Since there's no
architectural way of detecting the cpus that share particular cache,
device tree can be used and the core cacheinfo already supports the
same.
This patch adds the L2 cache topology on Juno board, FVP/RTSM and
foundation models.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit 5d425c18653731af6 ("arm64: kernel: add support for cpu cache
information") adds cacheinfo support for ARM64. Since there's no
architectural way of detecting the cpus that share particular cache,
device tree can be used and the core cacheinfo already supports the
same.
This patch adds the L2 cache topology on Juno board, FVP/RTSM and
foundation models.
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| arch/arm64/boot/dts/arm/foundation-v8.dts | diffblobblamehistory | |
| arch/arm64/boot/dts/arm/juno.dts | diffblobblamehistory | |
| arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | diffblobblamehistory |