| commit | 774dfc9bb7f2ab1950a790a8f13eca3d5c580033 | |
| author | Hiroshi DOYU <hdoyu@nvidia.com> | |
| Thu, 10 May 2012 07:45:32 +0000 (10 10:45 +0300) | ||
| committer | Joerg Roedel <joerg.roedel@amd.com> | |
| Fri, 11 May 2012 09:42:05 +0000 (11 11:42 +0200) | ||
| tree | c93680af050fcef7f5aff981ecfd3cf60abaf570 | treesnapshot (tar.gz zip) |
| parent | 7cffae421e3cd29410ef4d75f2244655fdde3b60 | commitdiff |
iommu/tegra: gart: Fix register offset correctly
DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
DT passes the exact GART register ranges without any overlapping with
MC register ranges. GART register offset needs to be adjusted by one
passed by DT correctly.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
| Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt | diffblobblamehistory | |
| drivers/iommu/tegra-gart.c | diffblobblamehistory |