| commit | 46d4bca0445a052193a99dd361bf57517ac11049 | |
| author | Florian Fainelli <f.fainelli@gmail.com> | |
| Fri, 21 Feb 2014 00:11:28 +0000 (20 16:11 -0800) | ||
| committer | Florian Fainelli <f.fainelli@gmail.com> | |
| Wed, 17 Sep 2014 17:56:07 +0000 (17 10:56 -0700) | ||
| tree | ef66460e003ef6650aad34233365d7c82113a1c6 | treesnapshot (tar.gz zip) |
| parent | b51312bebfa4452470c2bbf179200cb7c16d82d4 | commitdiff |
ARM: BCM63XX: add BCM63138 minimal Device Tree
Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:
- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)
Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add a very minimalistic BCM63138 Device Tree include file which
describes the BCM63138 SoC with only the basic set of required
peripherals:
- Cortex A9 CPUs
- ARM GIC
- ARM SCU
- PL310 Level-2 cache controller
- ARM TWD & Global timers
- ARM TWD watchdog
- legacy MIPS bus (UBUS)
- BCM6345-style UARTs (disabled by default)
Since the PL310 L2 cache controller does not come out of reset with
correct default values, we need to override the 'cache-sets' and
'cache-size' properties to get its geometry right.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| arch/arm/boot/dts/bcm63138.dtsi | [new file with mode: 0644] | blob |