| commit | 22bd1f7ef40a1c0f2ba796ba7cd80013adcb835d | |
| author | Stephen Warren <swarren@nvidia.com> | |
| Thu, 26 Apr 2012 17:19:03 +0000 (26 11:19 -0600) | ||
| committer | Stephen Warren <swarren@nvidia.com> | |
| Thu, 3 May 2012 20:49:08 +0000 (3 14:49 -0600) | ||
| tree | 050f3475bfeeca1aa5d24923bc8d3d108a938afd | treesnapshot (tar.gz zip) |
| parent | b46b0b54dea200973ce380369beb192b136d8934 | commitdiff |
ARM: dt: tegra seaboard: fix I2C2 SCL rate
This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This I2C bus is used for EDID/DDC reads and other "slow" I2C devices.
This requires a 100KHz SCL (clock) rate.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
| arch/arm/boot/dts/tegra-seaboard.dts | diffblobblamehistory |