| commit | 18393f6322ce523efa767e7ed9bd64fe0645e458 | |
| author | Chris Wilson <chris@chris-wilson.co.uk> | |
| Wed, 9 Apr 2014 08:19:40 +0000 (9 09:19 +0100) | ||
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | |
| Mon, 5 May 2014 07:08:36 +0000 (5 09:08 +0200) | ||
| tree | e7b6975c25580d25a3729c04218826f0feb96457 | treesnapshot (tar.gz zip) |
| parent | 93c9c19b3d259a76fc2efa4b8f2478dc9f339bee | commitdiff |
drm/i915: Replace hardcoded cacheline size with macro
For readibility and guess at the meaning behind the constants.
v2: Claim only the meagerest connections with reality.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
For readibility and guess at the meaning behind the constants.
v2: Claim only the meagerest connections with reality.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| drivers/gpu/drm/i915/intel_ringbuffer.c | diffblobblamehistory |