| commit | 0ca583a239a854fd403bf8b659cdff8c603372c9 | |
| author | Hongbo Zhang <hongbo.zhang@freescale.com> | |
| Thu, 16 Jan 2014 06:10:53 +0000 (16 14:10 +0800) | ||
| committer | Vinod Koul <vinod.koul@intel.com> | |
| Mon, 20 Jan 2014 07:43:22 +0000 (20 13:13 +0530) | ||
| tree | a495b019353c869454da1942965955eb38cdbfc6 | treesnapshot (tar.gz zip) |
| parent | 5f9e685a0d463666af080250b2ece11bc81acacd | commitdiff |
DMA: Freescale: change BWC from 256 bytes to 1024 bytes
Freescale DMA has a feature of BandWidth Control (ab. BWC), which is currently
256 bytes and should be changed to 1024 bytes for best DMA throughput.
Changing BWC from 256 to 1024 will improve DMA performance much, in cases
whatever one channel is running or multi channels are running simultanously,
large or small buffers are copied. And this change doesn't impact memory
access performance remarkably, lmbench tests show that for some cases the
memory performance are decreased very slightly, while the others are even
better.
Tested on T4240.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Freescale DMA has a feature of BandWidth Control (ab. BWC), which is currently
256 bytes and should be changed to 1024 bytes for best DMA throughput.
Changing BWC from 256 to 1024 will improve DMA performance much, in cases
whatever one channel is running or multi channels are running simultanously,
large or small buffers are copied. And this change doesn't impact memory
access performance remarkably, lmbench tests show that for some cases the
memory performance are decreased very slightly, while the others are even
better.
Tested on T4240.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| drivers/dma/fsldma.h | diffblobblamehistory |