From fade7ad56d929e168ead0f75e591468afa2fe97c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 27 Sep 2010 11:18:14 +1000 Subject: [PATCH] drm/nva3: split pm backend out from nv50 This will end up quite different, it makes sense for it to be completely separate. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/Makefile | 4 +- drivers/gpu/drm/nouveau/nouveau_pm.h | 6 ++ drivers/gpu/drm/nouveau/nouveau_state.c | 18 ++++- drivers/gpu/drm/nouveau/nv50_pm.c | 56 ++++++---------- drivers/gpu/drm/nouveau/{nv50_pm.c => nva3_pm.c} | 84 +++++------------------- 5 files changed, 57 insertions(+), 111 deletions(-) copy drivers/gpu/drm/nouveau/{nv50_pm.c => nva3_pm.c} (50%) diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index bdbde726778..23fa82d667d 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile @@ -10,7 +10,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ nouveau_dp.o nouveau_ramht.o \ - nouveau_pm.o nouveau_volt.o nouveau_perf.o \ + nouveau_pm.o nouveau_volt.o nouveau_perf.o nouveau_temp.o \ nv04_timer.o \ nv04_mc.o nv40_mc.o nv50_mc.o \ nv04_fb.o nv10_fb.o nv30_fb.o nv40_fb.o nv50_fb.o nvc0_fb.o \ @@ -25,7 +25,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ nv10_gpio.o nv50_gpio.o \ nv50_calc.o \ - nv04_pm.o nv50_pm.o nouveau_temp.o + nv04_pm.o nv50_pm.o nva3_pm.o nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h index babe64ac33c..4a9838ddace 100644 --- a/drivers/gpu/drm/nouveau/nouveau_pm.h +++ b/drivers/gpu/drm/nouveau/nouveau_pm.h @@ -58,6 +58,12 @@ void *nv50_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *, u32 id, int khz); void nv50_pm_clock_set(struct drm_device *, void *); +/* nva3_pm.c */ +int nva3_pm_clock_get(struct drm_device *, u32 id); +void *nva3_pm_clock_pre(struct drm_device *, struct nouveau_pm_level *, + u32 id, int khz); +void nva3_pm_clock_set(struct drm_device *, void *); + /* nouveau_temp.c */ void nouveau_temp_init(struct drm_device *dev); void nouveau_temp_fini(struct drm_device *dev); diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index affcfc2fae1..75bce914e7b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c @@ -375,9 +375,21 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) engine->gpio.get = nv50_gpio_get; engine->gpio.set = nv50_gpio_set; engine->gpio.irq_enable = nv50_gpio_irq_enable; - engine->pm.clock_get = nv50_pm_clock_get; - engine->pm.clock_pre = nv50_pm_clock_pre; - engine->pm.clock_set = nv50_pm_clock_set; + switch (dev_priv->chipset) { + case 0xa3: + case 0xa5: + case 0xa8: + case 0xaf: + engine->pm.clock_get = nva3_pm_clock_get; + engine->pm.clock_pre = nva3_pm_clock_pre; + engine->pm.clock_set = nva3_pm_clock_set; + break; + default: + engine->pm.clock_get = nv50_pm_clock_get; + engine->pm.clock_pre = nv50_pm_clock_pre; + engine->pm.clock_set = nv50_pm_clock_set; + break; + } engine->pm.voltage_get = nouveau_voltage_gpio_get; engine->pm.voltage_set = nouveau_voltage_gpio_set; if (dev_priv->chipset >= 0x84) diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c index 2a9fabdf1b7..7dbb305d7e6 100644 --- a/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/drivers/gpu/drm/nouveau/nv50_pm.c @@ -27,12 +27,6 @@ #include "nouveau_bios.h" #include "nouveau_pm.h" -/*XXX: boards using limits 0x40 need fixing, the register layout - * is correct here, but, there's some other funny magic - * that modifies things, so it's not likely we'll set/read - * the correct timings yet.. working on it... - */ - struct nv50_pm_state { struct nouveau_pm_level *perflvl; struct pll_lims pll; @@ -51,21 +45,13 @@ nv50_pm_clock_get(struct drm_device *dev, u32 id) if (ret) return ret; - if (pll.vco2.maxfreq) { - reg0 = nv_rd32(dev, pll.reg + 0); - reg1 = nv_rd32(dev, pll.reg + 4); - P = (reg0 & 0x00070000) >> 16; - N = (reg1 & 0x0000ff00) >> 8; - M = (reg1 & 0x000000ff); - - return ((pll.refclk * N / M) >> P); - } + reg0 = nv_rd32(dev, pll.reg + 0); + reg1 = nv_rd32(dev, pll.reg + 4); + P = (reg0 & 0x00070000) >> 16; + N = (reg1 & 0x0000ff00) >> 8; + M = (reg1 & 0x000000ff); - reg0 = nv_rd32(dev, pll.reg + 4); - P = (reg0 & 0x003f0000) >> 16; - N = (reg0 & 0x0000ff00) >> 8; - M = (reg0 & 0x000000ff); - return pll.refclk * N / M / P; + return ((pll.refclk * N / M) >> P); } void * @@ -125,23 +111,19 @@ nv50_pm_clock_set(struct drm_device *dev, void *pre_state) nouveau_bios_run_init_table(dev, perflvl->memscript, NULL); } - if (state->pll.vco2.maxfreq) { - if (state->type == PLL_MEMORY) { - nv_wr32(dev, 0x100210, 0); - nv_wr32(dev, 0x1002dc, 1); - } - - tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff; - tmp |= 0x80000000 | (P << 16); - nv_wr32(dev, reg + 0, tmp); - nv_wr32(dev, reg + 4, (N << 8) | M); - - if (state->type == PLL_MEMORY) { - nv_wr32(dev, 0x1002dc, 0); - nv_wr32(dev, 0x100210, 0x80000000); - } - } else { - nv_wr32(dev, reg + 4, (P << 16) | (N << 8) | M); + if (state->type == PLL_MEMORY) { + nv_wr32(dev, 0x100210, 0); + nv_wr32(dev, 0x1002dc, 1); + } + + tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff; + tmp |= 0x80000000 | (P << 16); + nv_wr32(dev, reg + 0, tmp); + nv_wr32(dev, reg + 4, (N << 8) | M); + + if (state->type == PLL_MEMORY) { + nv_wr32(dev, 0x1002dc, 0); + nv_wr32(dev, 0x100210, 0x80000000); } kfree(state); diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c similarity index 50% copy from drivers/gpu/drm/nouveau/nv50_pm.c copy to drivers/gpu/drm/nouveau/nva3_pm.c index 2a9fabdf1b7..dbbafed3640 100644 --- a/drivers/gpu/drm/nouveau/nv50_pm.c +++ b/drivers/gpu/drm/nouveau/nva3_pm.c @@ -33,53 +33,39 @@ * the correct timings yet.. working on it... */ -struct nv50_pm_state { - struct nouveau_pm_level *perflvl; +struct nva3_pm_state { struct pll_lims pll; - enum pll_types type; int N, M, P; }; int -nv50_pm_clock_get(struct drm_device *dev, u32 id) +nva3_pm_clock_get(struct drm_device *dev, u32 id) { struct pll_lims pll; int P, N, M, ret; - u32 reg0, reg1; + u32 reg; ret = get_pll_limits(dev, id, &pll); if (ret) return ret; - if (pll.vco2.maxfreq) { - reg0 = nv_rd32(dev, pll.reg + 0); - reg1 = nv_rd32(dev, pll.reg + 4); - P = (reg0 & 0x00070000) >> 16; - N = (reg1 & 0x0000ff00) >> 8; - M = (reg1 & 0x000000ff); - - return ((pll.refclk * N / M) >> P); - } - - reg0 = nv_rd32(dev, pll.reg + 4); - P = (reg0 & 0x003f0000) >> 16; - N = (reg0 & 0x0000ff00) >> 8; - M = (reg0 & 0x000000ff); + reg = nv_rd32(dev, pll.reg + 4); + P = (reg & 0x003f0000) >> 16; + N = (reg & 0x0000ff00) >> 8; + M = (reg & 0x000000ff); return pll.refclk * N / M / P; } void * -nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl, +nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl, u32 id, int khz) { - struct nv50_pm_state *state; + struct nva3_pm_state *state; int dummy, ret; state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) return ERR_PTR(-ENOMEM); - state->type = id; - state->perflvl = perflvl; ret = get_pll_limits(dev, id, &state->pll); if (ret < 0) { @@ -87,8 +73,8 @@ nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl, return (ret == -ENOENT) ? NULL : ERR_PTR(ret); } - ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M, - &dummy, &dummy, &state->P); + ret = nv50_calc_pll2(dev, &state->pll, khz, &state->N, &dummy, + &state->M, &state->P); if (ret < 0) { kfree(state); return ERR_PTR(ret); @@ -98,52 +84,12 @@ nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl, } void -nv50_pm_clock_set(struct drm_device *dev, void *pre_state) +nva3_pm_clock_set(struct drm_device *dev, void *pre_state) { - struct nv50_pm_state *state = pre_state; - struct nouveau_pm_level *perflvl = state->perflvl; - u32 reg = state->pll.reg, tmp; - struct bit_entry BIT_M; - u16 script; - int N = state->N; - int M = state->M; - int P = state->P; - - if (state->type == PLL_MEMORY && perflvl->memscript && - bit_table(dev, 'M', &BIT_M) == 0 && - BIT_M.version == 1 && BIT_M.length >= 0x0b) { - script = ROM16(BIT_M.data[0x05]); - if (script) - nouveau_bios_run_init_table(dev, script, NULL); - script = ROM16(BIT_M.data[0x07]); - if (script) - nouveau_bios_run_init_table(dev, script, NULL); - script = ROM16(BIT_M.data[0x09]); - if (script) - nouveau_bios_run_init_table(dev, script, NULL); - - nouveau_bios_run_init_table(dev, perflvl->memscript, NULL); - } - - if (state->pll.vco2.maxfreq) { - if (state->type == PLL_MEMORY) { - nv_wr32(dev, 0x100210, 0); - nv_wr32(dev, 0x1002dc, 1); - } - - tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff; - tmp |= 0x80000000 | (P << 16); - nv_wr32(dev, reg + 0, tmp); - nv_wr32(dev, reg + 4, (N << 8) | M); - - if (state->type == PLL_MEMORY) { - nv_wr32(dev, 0x1002dc, 0); - nv_wr32(dev, 0x100210, 0x80000000); - } - } else { - nv_wr32(dev, reg + 4, (P << 16) | (N << 8) | M); - } + struct nva3_pm_state *state = pre_state; + u32 reg = state->pll.reg; + nv_wr32(dev, reg + 4, (state->P << 16) | (state->N << 8) | state->M); kfree(state); } -- 2.11.4.GIT